Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51151034	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24230526

1

T1

105

T2

522

T3

651

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11778330	1			T1	49		T2	204		T3	305
values[0x0]	31740602	1			T1	166		T2	666		T3	836
values[0x1]	31862628	1			T1	171		T2	626		T3	872

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44549160	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30832400

1

T1

147

T2

654

T3

815

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	227083	1			T2	4		T11	3		T4	3
valid_sources[0x01]	228801	1			T2	4		T11	3		T4	1
valid_sources[0x02]	231691	1			T2	8		T11	5		T4	5
valid_sources[0x03]	239714	1			T2	7		T11	4		T4	2
valid_sources[0x04]	237231	1			T2	11		T11	2		T4	4
valid_sources[0x05]	226616	1			T2	1		T11	6		T4	2
valid_sources[0x06]	647404	1			T1	30		T2	5		T11	2
valid_sources[0x07]	257248	1			T2	2		T11	1		T4	1
valid_sources[0x08]	228556	1			T2	15		T11	1		T12	22
valid_sources[0x09]	226109	1			T2	11		T11	5		T5	10
valid_sources[0x0a]	228348	1			T2	3		T11	3		T12	14
valid_sources[0x0b]	229852	1			T2	4		T11	6		T4	1
valid_sources[0x0c]	264009	1			T2	2		T11	3		T4	1
valid_sources[0x0d]	226944	1			T2	7		T11	3		T5	3
valid_sources[0x0e]	230005	1			T11	4		T4	1		T12	39
valid_sources[0x0f]	229257	1			T2	3		T11	3		T12	28
valid_sources[0x10]	225674	1			T2	4		T11	5		T12	15
valid_sources[0x11]	601862	1			T2	4		T11	1		T4	1
valid_sources[0x12]	228346	1			T2	6		T11	2		T5	5
valid_sources[0x13]	227180	1			T2	3		T11	2		T4	1
valid_sources[0x14]	227538	1			T2	5		T11	3		T4	1
valid_sources[0x15]	227549	1			T2	7		T11	4		T4	4
valid_sources[0x16]	226647	1			T1	48		T2	3		T11	7
valid_sources[0x17]	228470	1			T1	7		T2	3		T11	7
valid_sources[0x18]	689765	1			T11	2		T4	5		T12	49
valid_sources[0x19]	226860	1			T1	4		T2	2		T11	4
valid_sources[0x1a]	230389	1			T2	5		T11	5		T4	2
valid_sources[0x1b]	229049	1			T2	4		T11	5		T4	1
valid_sources[0x1c]	229741	1			T2	3		T11	3		T4	1
valid_sources[0x1d]	228669	1			T2	5		T11	3		T4	1
valid_sources[0x1e]	237723	1			T2	7		T11	5		T5	13
valid_sources[0x1f]	704519	1			T2	3		T11	6		T4	2
valid_sources[0x20]	226967	1			T2	7		T11	3		T4	2
valid_sources[0x21]	662323	1			T2	3		T11	2		T5	15
valid_sources[0x22]	686312	1			T2	10		T11	4		T4	1
valid_sources[0x23]	232260	1			T2	7		T11	5		T4	3
valid_sources[0x24]	225958	1			T2	4		T11	6		T4	3
valid_sources[0x25]	228957	1			T2	6		T11	2		T12	21
valid_sources[0x26]	229940	1			T2	3		T11	6		T5	4
valid_sources[0x27]	228645	1			T2	4		T11	2		T4	1
valid_sources[0x28]	226133	1			T2	8		T11	2		T4	1
valid_sources[0x29]	227417	1			T2	4		T11	1		T4	1
valid_sources[0x2a]	226326	1			T2	5		T11	4		T4	3
valid_sources[0x2b]	226489	1			T2	9		T11	2		T4	1
valid_sources[0x2c]	236589	1			T2	10		T11	1		T4	4
valid_sources[0x2d]	228331	1			T2	2		T11	4		T4	6
valid_sources[0x2e]	225648	1			T2	9		T11	3		T4	1
valid_sources[0x2f]	226988	1			T2	5		T11	4		T4	1
valid_sources[0x30]	257459	1			T1	25		T2	5		T11	7
valid_sources[0x31]	229346	1			T2	14		T11	1		T4	8
valid_sources[0x32]	233638	1			T2	11		T11	7		T9	1910
valid_sources[0x33]	228483	1			T1	12		T2	5		T11	6
valid_sources[0x34]	227113	1			T2	5		T11	7		T4	2
valid_sources[0x35]	232550	1			T1	14		T2	7		T11	6
valid_sources[0x36]	628718	1			T2	10		T11	4		T4	1
valid_sources[0x37]	228014	1			T2	7		T11	8		T4	2
valid_sources[0x38]	226928	1			T2	4		T11	4		T4	3
valid_sources[0x39]	225264	1			T2	9		T11	3		T4	3
valid_sources[0x3a]	942788	1			T2	10		T11	5		T4	1
valid_sources[0x3b]	226792	1			T1	21		T2	3		T11	6
valid_sources[0x3c]	228715	1			T2	4		T11	6		T4	3
valid_sources[0x3d]	266110	1			T1	27		T2	12		T11	2
valid_sources[0x3e]	232802	1			T2	3		T11	3		T4	4
valid_sources[0x3f]	233553	1			T2	4		T11	5		T4	2
valid_sources[0x40]	237157	1			T2	6		T11	2		T5	14
valid_sources[0x41]	237229	1			T2	6		T11	4		T12	34
valid_sources[0x42]	657617	1			T2	4		T11	2		T4	3
valid_sources[0x43]	227898	1			T2	13		T11	2		T5	23
valid_sources[0x44]	227524	1			T2	4		T11	6		T4	2
valid_sources[0x45]	228933	1			T2	1		T11	6		T4	2
valid_sources[0x46]	477695	1			T2	2		T11	2		T5	13
valid_sources[0x47]	228627	1			T2	6		T11	1		T5	12
valid_sources[0x48]	244975	1			T2	8		T11	3		T12	25
valid_sources[0x49]	244654	1			T2	10		T11	7		T4	2
valid_sources[0x4a]	235805	1			T2	10		T11	3		T4	1
valid_sources[0x4b]	228979	1			T2	4		T11	1		T12	32
valid_sources[0x4c]	227978	1			T2	7		T11	5		T4	1
valid_sources[0x4d]	227039	1			T2	5		T11	3		T4	5
valid_sources[0x4e]	228426	1			T2	10		T11	9		T4	3
valid_sources[0x4f]	712520	1			T2	7		T11	6		T4	2
valid_sources[0x50]	571018	1			T2	4		T11	5		T4	6
valid_sources[0x51]	229808	1			T2	4		T11	5		T4	2
valid_sources[0x52]	231662	1			T2	2		T11	5		T4	4
valid_sources[0x53]	226908	1			T2	6		T11	4		T4	3
valid_sources[0x54]	225919	1			T2	2		T11	5		T4	1
valid_sources[0x55]	433993	1			T2	6		T11	5		T12	38
valid_sources[0x56]	536463	1			T2	8		T11	6		T4	1
valid_sources[0x57]	487445	1			T2	2		T11	4		T4	4
valid_sources[0x58]	229845	1			T2	9		T11	4		T4	4
valid_sources[0x59]	226420	1			T2	3		T11	6		T4	2
valid_sources[0x5a]	230440	1			T2	7		T11	2		T4	2
valid_sources[0x5b]	236580	1			T2	5		T11	3		T4	3
valid_sources[0x5c]	225696	1			T2	5		T11	4		T4	2
valid_sources[0x5d]	233254	1			T2	5		T11	11		T4	1
valid_sources[0x5e]	525940	1			T2	6		T11	6		T4	3
valid_sources[0x5f]	229810	1			T2	4		T11	9		T4	3
valid_sources[0x60]	463833	1			T2	7		T11	5		T4	3
valid_sources[0x61]	225443	1			T2	5		T11	4		T12	26
valid_sources[0x62]	226473	1			T2	6		T11	4		T4	3
valid_sources[0x63]	667105	1			T2	11		T11	3		T12	17
valid_sources[0x64]	228537	1			T2	12		T11	3		T4	4
valid_sources[0x65]	228004	1			T2	4		T11	2		T12	19
valid_sources[0x66]	562882	1			T1	14		T2	3		T11	2
valid_sources[0x67]	229377	1			T1	15		T2	6		T11	6
valid_sources[0x68]	227396	1			T2	8		T11	3		T12	25
valid_sources[0x69]	228480	1			T2	6		T11	2		T4	1
valid_sources[0x6a]	679729	1			T2	2		T11	6		T4	1
valid_sources[0x6b]	228815	1			T2	4		T11	1		T4	4
valid_sources[0x6c]	225902	1			T2	5		T11	2		T5	1
valid_sources[0x6d]	225231	1			T2	2		T11	1		T4	1
valid_sources[0x6e]	269913	1			T2	4		T11	4		T12	23
valid_sources[0x6f]	228043	1			T2	4		T11	4		T4	1
valid_sources[0x70]	229386	1			T2	6		T11	6		T4	1
valid_sources[0x71]	231744	1			T2	3		T11	1		T4	3
valid_sources[0x72]	241734	1			T2	3		T11	3		T5	12
valid_sources[0x73]	685028	1			T2	11		T11	8		T4	1
valid_sources[0x74]	224131	1			T1	7		T2	1		T11	6
valid_sources[0x75]	517177	1			T2	4		T11	5		T4	1
valid_sources[0x76]	225196	1			T2	3		T11	2		T12	23
valid_sources[0x77]	273030	1			T2	5		T11	4		T4	2
valid_sources[0x78]	229526	1			T2	2		T11	3		T12	20
valid_sources[0x79]	226833	1			T2	4		T11	3		T4	4
valid_sources[0x7a]	500130	1			T11	3		T5	5		T12	31
valid_sources[0x7b]	225392	1			T2	5		T11	2		T4	2
valid_sources[0x7c]	239692	1			T2	6		T11	3		T4	2
valid_sources[0x7d]	227026	1			T2	6		T11	5		T4	3
valid_sources[0x7e]	229648	1			T2	5		T11	3		T4	1
valid_sources[0x7f]	228301	1			T2	10		T11	4		T5	28
valid_sources[0x80]	233643	1			T2	5		T11	4		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5686228

1

T1

22

T2

104

T3

139

values[0x0]

all_enables

biggest_size

11842918

1

T1

50

T2

260

T3

313

values[0x1]

all_enables

biggest_size

6701380

1

T1

33

T2

158

T3

199