Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T9
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T22,T51
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15026	0	0
DisabledNoTrigBkwd_A	2147483647	730185	0	0
DisabledNoTrigFwd_A	2147483647	1132906981	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15026	0	0
T1	4132	990	0	0
T6	44863	0	0	0
T7	103945	0	0	0
T13	17225	0	0	0
T14	290194	0	0	0
T18	20441	0	0	0
T22	1956	306	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T31	33955	0	0	0
T33	65469	0	0	0
T40	20262	0	0	0
T42	17850	0	0	0
T48	23232	0	0	0
T49	85053	0	0	0
T50	7702	0	0	0
T51	0	900	0	0
T55	1601	821	0	0
T76	0	395	0	0
T83	41108	0	0	0
T88	189600	0	0	0
T105	89174	0	0	0
T235	0	1165	0	0
T236	0	626	0	0
T237	0	1521	0	0
T238	0	347	0	0
T239	0	163	0	0
T240	0	1054	0	0
T241	0	537	0	0
T242	0	832	0	0
T243	0	617	0	0
T244	0	1390	0	0
T245	0	579	0	0
T246	0	329	0	0
T247	0	1065	0	0
T248	0	800	0	0
T249	0	589	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	730185	0	0
T1	4132	24	0	0
T2	21892	10	0	0
T3	33210	0	0	0
T4	118128	0	0	0
T5	132801	0	0	0
T6	44863	0	0	0
T9	64515	0	0	0
T11	38883	0	0	0
T12	121292	68	0	0
T13	51675	24	0	0
T21	226408	2	0	0
T22	3912	2	0	0
T23	122858	7	0	0
T24	137830	68	0	0
T25	7373	0	0	0
T27	0	73	0	0
T28	0	22	0	0
T36	0	5	0	0
T39	0	115	0	0
T42	17850	6	0	0
T43	0	24	0	0
T44	0	2	0	0
T49	85053	0	0	0
T50	0	6	0	0
T51	0	20	0	0
T52	0	155	0	0
T53	0	6	0	0
T54	0	16	0	0
T55	0	16	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1132906981	0	0
T1	16528	11359	0	0
T2	43784	27457	0	0
T3	66420	38842	0	0
T4	157504	7380	0	0
T5	177068	75076	0	0
T9	86020	75947	0	0
T11	51844	32683	0	0
T12	121292	27230	0	0
T21	226408	177831	0	0
T22	3912	2416	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T11 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T9
1	1	Covered	T2,T3,T9

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T235,T236
1	1	Covered	T2,T3,T9

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T12,T21

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	551568653	5477	0	0
DisabledNoTrigBkwd_A	551568653	199783	0	0
DisabledNoTrigFwd_A	551568653	289840542	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	5477	0	0
T6	44863	0	0	0
T7	103945	0	0	0
T13	17225	0	0	0
T22	978	306	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T42	17850	0	0	0
T49	85053	0	0	0
T50	7702	0	0	0
T235	0	1165	0	0
T236	0	626	0	0
T238	0	347	0	0
T245	0	579	0	0
T247	0	1065	0	0
T248	0	800	0	0
T249	0	589	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	199783	0	0
T2	10946	10	0	0
T3	16605	0	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	36	0	0
T13	17225	0	0	0
T21	56602	2	0	0
T22	978	2	0	0
T23	0	6	0	0
T24	0	68	0	0
T27	0	73	0	0
T39	0	113	0	0
T42	0	6	0	0
T50	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	289840542	0	0
T1	4132	2807	0	0
T2	10946	2057	0	0
T3	16605	6267	0	0
T4	39376	1839	0	0
T5	44267	18769	0	0
T9	21505	16080	0	0
T11	12961	12876	0	0
T12	30323	597	0	0
T21	56602	8322	0	0
T22	978	598	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T11 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T4,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T237,T240
1	1	Covered	T3,T4,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T12,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	551568653	5777	0	0
DisabledNoTrigBkwd_A	551568653	159002	0	0
DisabledNoTrigFwd_A	551568653	287202971	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	5777	0	0
T14	290194	0	0	0
T18	20441	0	0	0
T31	33955	0	0	0
T33	65469	0	0	0
T40	20262	0	0	0
T48	23232	0	0	0
T55	1601	821	0	0
T76	0	395	0	0
T83	41108	0	0	0
T88	189600	0	0	0
T105	89174	0	0	0
T237	0	1521	0	0
T240	0	1054	0	0
T241	0	537	0	0
T242	0	832	0	0
T243	0	617	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	159002	0	0
T6	44863	0	0	0
T12	30323	17	0	0
T13	17225	13	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	1	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T28	0	22	0	0
T36	0	1	0	0
T42	17850	0	0	0
T43	0	4	0	0
T44	0	2	0	0
T49	85053	0	0	0
T50	0	3	0	0
T54	0	16	0	0
T55	0	16	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	287202971	0	0
T1	4132	2836	0	0
T2	10946	10859	0	0
T3	16605	11054	0	0
T4	39376	1843	0	0
T5	44267	18769	0	0
T9	21505	21433	0	0
T11	12961	12876	0	0
T12	30323	10864	0	0
T21	56602	56503	0	0
T22	978	602	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T12,T23
1	1	Covered	T1,T3,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T51,T246
1	1	Covered	T1,T3,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T12,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	551568653	2219	0	0
DisabledNoTrigBkwd_A	551568653	204366	0	0
DisabledNoTrigFwd_A	551568653	267474598	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	2219	0	0
T1	4132	990	0	0
T2	10946	0	0	0
T3	16605	0	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T51	0	900	0	0
T246	0	329	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	204366	0	0
T1	4132	24	0	0
T2	10946	0	0	0
T3	16605	0	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	15	0	0
T13	0	11	0	0
T21	56602	0	0	0
T22	978	0	0	0
T36	0	4	0	0
T39	0	2	0	0
T43	0	20	0	0
T50	0	1	0	0
T51	0	20	0	0
T52	0	155	0	0
T53	0	6	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	267474598	0	0
T1	4132	2850	0	0
T2	10946	7264	0	0
T3	16605	10445	0	0
T4	39376	1847	0	0
T5	44267	18769	0	0
T9	21505	19211	0	0
T11	12961	3452	0	0
T12	30323	13308	0	0
T21	56602	56503	0	0
T22	978	606	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T11 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T12,T23
1	1	Covered	T3,T11,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T239,T244
1	1	Covered	T3,T11,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	551568653	1553	0	0
DisabledNoTrigBkwd_A	551568653	167034	0	0
DisabledNoTrigFwd_A	551568653	288388870	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1553	0	0
T30	17242	0	0	0
T37	752721	0	0	0
T90	118428	0	0	0
T91	33675	0	0	0
T115	15296	0	0	0
T239	860	163	0	0
T244	0	1390	0	0
T250	621890	0	0	0
T251	52117	0	0	0
T252	162394	0	0	0
T253	17669	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	167034	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	9	0	0
T12	30323	33	0	0
T13	17225	9	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T28	0	2	0	0
T44	0	17	0	0
T52	0	186	0	0
T53	0	9	0	0
T54	0	2	0	0
T104	0	2	0	0
T122	0	162	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	288388870	0	0
T1	4132	2866	0	0
T2	10946	7277	0	0
T3	16605	11076	0	0
T4	39376	1851	0	0
T5	44267	18769	0	0
T9	21505	19223	0	0
T11	12961	3479	0	0
T12	30323	2461	0	0
T21	56602	56503	0	0
T22	978	610	0	0