Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	43306	1			T55	14		T46	1		T43	132
class_i[0x1]	35524	1			T43	845		T22	2		T24	3
class_i[0x2]	71864	1			T10	1170		T17	2315		T55	4
class_i[0x3]	46908	1			T55	126		T42	373		T43	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	52432	1			T10	14		T17	829		T55	88
alert[0x1]	46486	1			T10	1127		T17	861		T55	22
alert[0x2]	50048	1			T10	12		T17	612		T55	16
alert[0x3]	48636	1			T10	17		T17	13		T55	18

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

197335

1

T10

1170

T17

2315

T55

144

esc_ping_fail

267

1

T22

2

T23

2

T24

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	52355	1			T10	14		T17	829		T55	88
esc_integrity_fail	alert[0x1]	46411	1			T10	1127		T17	861		T55	22
esc_integrity_fail	alert[0x2]	49991	1			T10	12		T17	612		T55	16
esc_integrity_fail	alert[0x3]	48578	1			T10	17		T17	13		T55	18
esc_ping_fail	alert[0x0]	77	1			T22	1		T267	2		T92	1
esc_ping_fail	alert[0x1]	75	1			T22	1		T23	1		T24	1
esc_ping_fail	alert[0x2]	57	1			T23	1		T24	1		T92	2
esc_ping_fail	alert[0x3]	58	1			T24	1		T348	1		T30	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	43216	1			T55	14		T46	1		T43	132
esc_integrity_fail	class_i[0x1]	35456	1			T43	845		T22	2		T103	518
esc_integrity_fail	class_i[0x2]	71818	1			T10	1170		T17	2315		T55	4
esc_integrity_fail	class_i[0x3]	46845	1			T55	126		T42	373		T43	1
esc_ping_fail	class_i[0x0]	90	1			T22	2		T23	1		T267	3
esc_ping_fail	class_i[0x1]	68	1			T24	3		T267	1		T347	1
esc_ping_fail	class_i[0x2]	46	1			T23	1		T30	1		T351	3
esc_ping_fail	class_i[0x3]	63	1			T92	5		T347	1		T352	2