Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	543226663	0	0	618
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	543226663	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	543226663	543070428	0	0
tb.dut.CheckAccuCntDw	0	0	618	618	0	0
tb.dut.CheckEscCntDw	0	0	618	618	0	0
tb.dut.CheckNAlerts	0	0	618	618	0	0
tb.dut.CheckNClasses	0	0	618	618	0	0
tb.dut.CheckNEscSev	0	0	618	618	0	0
tb.dut.CrashdumpKnownO_A	0	0	543226663	543070428	0	0
tb.dut.EdnKnownO_A	0	0	543226663	543070428	0	0
tb.dut.EscPKnownO_A	0	0	543226663	543070428	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	543226663	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	543226663	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	543226663	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	543226663	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	543226663	70	0	0
tb.dut.IrqAKnownO_A	0	0	543226663	543070428	0	0
tb.dut.IrqBKnownO_A	0	0	543226663	543070428	0	0
tb.dut.IrqCKnownO_A	0	0	543226663	543070428	0	0
tb.dut.IrqDKnownO_A	0	0	543226663	543070428	0	0
tb.dut.TlAReadyKnownO_A	0	0	543226663	543070428	0	0
tb.dut.TlDValidKnownO_A	0	0	543226663	543070428	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	568836832	221500	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	568836832	12413	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	568836832	12690	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	568836832	12262	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	568836832	12346	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	568836832	12272	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	568836832	12700	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	568836832	12558	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	568836832	12446	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	568836832	12512	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	568836832	12452	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	568836832	12603	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	568836832	12260	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	568836832	12627	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	568836832	12277	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	568836832	12210	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	568836832	12342	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	568836832	12482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	568836832	12331	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	568836832	12443	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	568836832	12458	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	568836832	12210	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	568836832	12386	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	568836832	12260	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	568836832	12450	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	568836832	12364	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	568836832	12433	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	568836832	12332	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	568836832	12085	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	568836832	12284	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	568836832	12879	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	568836832	12015	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	568836832	12191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	568836832	12683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	568836832	12567	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	568836832	12368	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	568836832	12268	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	568836832	12530	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	568836832	12680	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	568836832	12168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	568836832	12663	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	568836832	12533	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	568836832	12196	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	568836832	12375	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	568836832	12569	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	568836832	12547	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	568836832	12214	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	568836832	12062	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	568836832	12619	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	568836832	12687	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	568836832	12558	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	568836832	12315	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	568836832	12429	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	568836832	12888	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	568836832	12413	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	568836832	12601	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	568836832	12428	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	568836832	12482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	568836832	12343	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	568836832	12388	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	568836832	12226	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	568836832	12324	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	568836832	12501	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	568836832	12531	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	568836832	12402	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	568836832	12273	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	568836832	12655	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	568836832	12252	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	568836832	12381	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	568836832	12345	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	568836832	23074	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	568836832	12844	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	568836832	12334	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	568836832	12514	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	568836832	12601	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	568836832	12541	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	568836832	12435	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	568836832	12314	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	568836832	12352	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	543226663	5281	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	543226663	134424	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	543226663	292732929	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	543226663	247	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	543226663	762	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	543226663	36	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	543226663	359	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	542902733	244516868	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	543226663	838	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	543226663	817	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	543226663	801	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	543226663	775	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	543226663	851	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	543226663	120215	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	543226663	749	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	543226663	62	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	543226663	1086	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	543226663	876	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	542900546	542833363	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	618	618	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	543226663	543070428	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	543226663	5773	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	543226663	176984	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	543226663	315315583	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	543226663	227	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	543226663	438	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	543226663	25	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	543226663	214	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	542902733	253035245	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	543226663	515	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	543226663	505	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	543226663	495	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	543226663	487	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	543226663	598	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	543226663	78822	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	543226663	505	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	543226663	64	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	543226663	1047	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	543226663	837	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	542900546	542833363	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	618	618	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	543226663	543070428	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	543226663	1971	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	543226663	146148	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	543226663	313353950	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	543226663	185	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	543226663	465	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	543226663	28	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	543226663	229	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	542902733	243096490	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	543226663	533	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	543226663	521	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	543226663	506	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	543226663	501	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	543226663	519	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	543226663	65795	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	543226663	433	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	543226663	55	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	543226663	1090	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	543226663	880	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	542900546	542833363	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	618	618	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	543226663	543070428	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	543226663	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	543226663	836	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	543226663	175111	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	543226663	290474206	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	543226663	185	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	543226663	446	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	543226663	24	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	543226663	206	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	542902733	229827764	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	543226663	514	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	543226663	503	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	543226663	495	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	543226663	483	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	543226663	724	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	543226663	91091	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	543226663	630	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	543226663	62	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	543226663	1188	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	543226663	978	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	542900546	542833363	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	618	618	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	543226663	543070428	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	568836832	78579015	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	568836832	568168922	0	0
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tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	823	823	0	0

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