Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.22	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	4	40	90.91

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	4	40	90.91	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	159	1			T17	1		T15	1		T56	1
index[0x1]	135	1			T1	1		T17	1		T56	1
index[0x2]	163	1			T46	1		T42	1		T60	1
index[0x3]	149	1			T17	1		T15	2		T54	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	213	1			T17	1		T46	1		T42	1
lens_less_than_1000[1]	104	1			T17	1		T56	2		T42	2
lens_less_than_1000[2]	75	1			T1	1		T60	1		T260	1
lens_less_than_1000[3]	60	1			T15	1		T54	1		T60	1
lens_less_than_1000[4]	52	1			T17	1		T15	1		T58	1
lens_less_than_1000[5]	34	1			T15	1		T89	1		T144	1
lens_less_than_1000[6]	16	1			T125	1		T48	1		T275	1
lens_less_than_1000[7]	27	1			T87	1		T276	1		T64	1
lens_less_than_1000[8]	11	1			T277	1		T70	1		T278	1
lens_less_than_1000[9]	2	1			T279	1		T280	1		-	-
len_2	12	1			T281	1		T282	1		T283	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	4	40	90.91	4

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0] , index[0x1]]	[lens_less_than_1000[9]]	--	--	2
[index[0x2]]	[len_2]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	48	1			T48	2		T112	1		T33	1
index[0x0]	lens_less_than_1000[1]	29	1			T17	1		T56	1		T59	1
index[0x0]	lens_less_than_1000[2]	22	1			T60	1		T61	1		T104	1
index[0x0]	lens_less_than_1000[3]	16	1			T15	1		T284	1		T92	1
index[0x0]	lens_less_than_1000[4]	11	1			T111	1		T114	1		T285	1
index[0x0]	lens_less_than_1000[5]	10	1			T144	1		T36	1		T67	1
index[0x0]	lens_less_than_1000[6]	2	1			T125	1		T69	1		-	-
index[0x0]	lens_less_than_1000[7]	14	1			T64	1		T34	7		T286	1
index[0x0]	lens_less_than_1000[8]	3	1			T278	1		T287	1		T288	1
index[0x0]	len_2	4	1			T283	2		T120	1		T163	1
index[0x1]	lens_less_than_1000[0]	51	1			T42	1		T43	1		T289	2
index[0x1]	lens_less_than_1000[1]	25	1			T56	1		T33	2		T290	1
index[0x1]	lens_less_than_1000[2]	14	1			T1	1		T91	1		T32	1
index[0x1]	lens_less_than_1000[3]	14	1			T291	1		T127	1		T69	1
index[0x1]	lens_less_than_1000[4]	13	1			T17	1		T58	1		T49	1
index[0x1]	lens_less_than_1000[5]	7	1			T89	1		T71	1		T292	1
index[0x1]	lens_less_than_1000[6]	2	1			T275	1		T293	1		-	-
index[0x1]	lens_less_than_1000[7]	2	1			T268	1		T294	1		-	-
index[0x1]	lens_less_than_1000[8]	2	1			T277	1		T295	1		-	-
index[0x1]	len_2	5	1			T281	1		T296	2		T297	1
index[0x2]	lens_less_than_1000[0]	50	1			T46	1		T99	1		T112	1
index[0x2]	lens_less_than_1000[1]	24	1			T42	1		T49	1		T115	2
index[0x2]	lens_less_than_1000[2]	20	1			T260	1		T284	1		T133	1
index[0x2]	lens_less_than_1000[3]	25	1			T60	1		T62	4		T78	1
index[0x2]	lens_less_than_1000[4]	16	1			T43	1		T49	1		T150	1
index[0x2]	lens_less_than_1000[5]	12	1			T155	4		T298	8		-	-
index[0x2]	lens_less_than_1000[6]	5	1			T277	1		T162	1		T299	1
index[0x2]	lens_less_than_1000[7]	8	1			T87	1		T300	1		T72	1
index[0x2]	lens_less_than_1000[8]	1	1			T301	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	2	1			T279	1		T280	1		-	-
index[0x3]	lens_less_than_1000[0]	64	1			T17	1		T43	1		T99	1
index[0x3]	lens_less_than_1000[1]	26	1			T42	1		T60	1		T302	1
index[0x3]	lens_less_than_1000[2]	19	1			T107	1		T49	1		T117	1
index[0x3]	lens_less_than_1000[3]	5	1			T54	1		T112	1		T303	1
index[0x3]	lens_less_than_1000[4]	12	1			T15	1		T50	1		T150	1
index[0x3]	lens_less_than_1000[5]	5	1			T15	1		T50	1		T142	1
index[0x3]	lens_less_than_1000[6]	7	1			T48	1		T137	3		T304	1
index[0x3]	lens_less_than_1000[7]	3	1			T276	1		T142	1		T152	1
index[0x3]	lens_less_than_1000[8]	5	1			T70	1		T152	1		T305	1
index[0x3]	len_2	3	1			T282	1		T306	1		T307	1