Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	62	1			T17	1		T42	1		T99	1
class_index[0x1]	64	1			T12	1		T17	1		T42	1
class_index[0x2]	55	1			T42	1		T112	1		T33	1
class_index[0x3]	62	1			T17	1		T101	1		T111	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	113	1			T42	1		T101	1		T111	1
intr_timeout_cnt[1]	45	1			T12	1		T17	1		T49	1
intr_timeout_cnt[2]	22	1			T90	2		T148	1		T115	1
intr_timeout_cnt[3]	13	1			T42	1		T114	1		T62	1
intr_timeout_cnt[4]	12	1			T112	1		T64	1		T308	1
intr_timeout_cnt[5]	11	1			T99	2		T35	1		T115	1
intr_timeout_cnt[6]	8	1			T113	1		T162	1		T309	1
intr_timeout_cnt[7]	7	1			T17	1		T42	1		T117	1
intr_timeout_cnt[8]	6	1			T49	1		T310	1		T311	1
intr_timeout_cnt[9]	6	1			T17	1		T162	1		T312	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	23	1			T33	2		T113	2		T62	1
class_index[0x0]	intr_timeout_cnt[1]	12	1			T49	1		T313	1		T314	1
class_index[0x0]	intr_timeout_cnt[2]	3	1			T39	1		T293	2		-	-
class_index[0x0]	intr_timeout_cnt[3]	3	1			T114	1		T315	1		T316	1
class_index[0x0]	intr_timeout_cnt[4]	6	1			T64	1		T128	1		T317	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T99	1		T318	1		T69	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T162	1		T309	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T42	1		T117	1		T319	1
class_index[0x0]	intr_timeout_cnt[8]	2	1			T320	1		T321	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T17	1		T312	1		T320	1
class_index[0x1]	intr_timeout_cnt[0]	29	1			T113	1		T32	1		T62	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T12	1		T17	1		T33	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T90	2		T162	1		T322	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T42	1		T323	1		T312	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T308	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T99	1		T324	2		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T325	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T311	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T49	1		T310	1		T160	1
class_index[0x1]	intr_timeout_cnt[9]	1	1			T158	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	28	1			T42	1		T33	1		T113	1
class_index[0x2]	intr_timeout_cnt[1]	13	1			T118	1		T69	1		T142	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T115	1		T77	1		T326	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T62	1		T65	1		T69	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T112	1		T69	1		T163	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T35	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T327	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T158	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T162	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	33	1			T101	1		T111	1		T104	1
class_index[0x3]	intr_timeout_cnt[1]	8	1			T145	1		T68	2		T328	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T148	1		T69	1		T128	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T320	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T69	1		T329	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	2	1			T115	1		T162	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	4	1			T113	1		T330	1		T287	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T17	1		T142	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T311	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T316	1		-	-		-	-