Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278256	1			T1	11		T9	21		T12	39
all_values[1]	278256	1			T1	11		T9	21		T12	39
all_values[2]	278256	1			T1	11		T9	21		T12	39
all_values[3]	278256	1			T1	11		T9	21		T12	39

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

553362

1

T1

21

T9

39

T12

69

auto[1]

559662

1

T1

23

T9

45

T12

87

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

660985

1

T1

39

T9

78

T12

83

auto[1]

452039

1

T1

5

T9

6

T12

73

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	78249	1			T1	3		T9	11		T12	12
all_values[0]	auto[0]	auto[1]	59669	1			T1	3		T9	4		T12	12
all_values[0]	auto[1]	auto[0]	80227	1			T1	3		T9	4		T12	8
all_values[0]	auto[1]	auto[1]	60111	1			T1	2		T9	2		T12	7
all_values[1]	auto[0]	auto[0]	84363	1			T1	4		T9	9		T12	6
all_values[1]	auto[0]	auto[1]	55119	1			T12	6		T10	7		T14	3
all_values[1]	auto[1]	auto[0]	84248	1			T1	7		T9	12		T12	15
all_values[1]	auto[1]	auto[1]	54526	1			T12	12		T10	6		T14	4
all_values[2]	auto[0]	auto[0]	82579	1			T1	5		T9	13		T12	6
all_values[2]	auto[0]	auto[1]	55439	1			T12	6		T10	4		T14	6
all_values[2]	auto[1]	auto[0]	84290	1			T1	6		T9	8		T12	14
all_values[2]	auto[1]	auto[1]	55948	1			T12	13		T10	10		T14	1
all_values[3]	auto[0]	auto[0]	82350	1			T1	6		T9	2		T12	13
all_values[3]	auto[0]	auto[1]	55594	1			T12	8		T10	7		T14	4
all_values[3]	auto[1]	auto[0]	84679	1			T1	5		T9	19		T12	9
all_values[3]	auto[1]	auto[1]	55633	1			T12	9		T10	7		T14	2