Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	278256	1			T1	11		T9	21		T12	39
all_pins[1]	278256	1			T1	11		T9	21		T12	39
all_pins[2]	278256	1			T1	11		T9	21		T12	39
all_pins[3]	278256	1			T1	11		T9	21		T12	39

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	886806	1			T1	42		T9	82		T12	115
values[0x1]	226218	1			T1	2		T9	2		T12	41
transitions[0x0=>0x1]	150780	1			T1	2		T9	2		T12	22
transitions[0x1=>0x0]	151038	1			T1	2		T9	2		T12	22

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	218145	1			T1	9		T9	19		T12	32
all_pins[0]	values[0x1]	60111	1			T1	2		T9	2		T12	7
all_pins[0]	transitions[0x0=>0x1]	59598	1			T1	2		T9	2		T12	7
all_pins[0]	transitions[0x1=>0x0]	55378	1			T12	9		T10	7		T14	2
all_pins[1]	values[0x0]	223730	1			T1	11		T9	21		T12	27
all_pins[1]	values[0x1]	54526	1			T12	12		T10	6		T14	4
all_pins[1]	transitions[0x0=>0x1]	29573	1			T12	8		T10	5		T14	3
all_pins[1]	transitions[0x1=>0x0]	35158	1			T1	2		T9	2		T12	3
all_pins[2]	values[0x0]	222308	1			T1	11		T9	21		T12	26
all_pins[2]	values[0x1]	55948	1			T12	13		T10	10		T14	1
all_pins[2]	transitions[0x0=>0x1]	31140	1			T12	4		T10	6		T14	1
all_pins[2]	transitions[0x1=>0x0]	29718	1			T12	3		T10	2		T14	4
all_pins[3]	values[0x0]	222623	1			T1	11		T9	21		T12	30
all_pins[3]	values[0x1]	55633	1			T12	9		T10	7		T14	2
all_pins[3]	transitions[0x0=>0x1]	30469	1			T12	3		T10	2		T14	2
all_pins[3]	transitions[0x1=>0x0]	30784	1			T12	7		T10	5		T14	1