Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T207	4		T209	4		T274	4
all_values[1]	269	1			T207	4		T209	4		T274	4
all_values[2]	269	1			T207	4		T209	4		T274	4
all_values[3]	269	1			T207	4		T209	4		T274	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

556

1

T207

12

T209

6

T274

10

auto[1]

520

1

T207

4

T209

10

T274

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

419

1

T207

6

T209

11

T274

8

auto[1]

657

1

T207

10

T209

5

T274

8

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

638

1

T207

10

T209

12

T274

10

auto[1]

438

1

T207

6

T209

4

T274

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

57

1

T207

3

T209

2

T274

2

all_values[0]

auto[0]

auto[0]

auto[1]

22

1

T409

1

T410

1

T411

1

all_values[0]

auto[0]

auto[1]

auto[0]

54

1

T209

2

T274

2

T266

1

all_values[0]

auto[0]

auto[1]

auto[1]

32

1

T409

1

T410

1

T412

1

all_values[0]

auto[1]

auto[0]

auto[1]

53

1

T207

1

T266

1

T413

2

all_values[0]

auto[1]

auto[1]

auto[1]

51

1

T266

2

T409

2

T410

2

all_values[1]

auto[0]

auto[0]

auto[0]

74

1

T207

2

T209

1

T274

1

all_values[1]

auto[0]

auto[0]

auto[1]

19

1

T207

1

T266

1

T410

1

all_values[1]

auto[0]

auto[1]

auto[0]

46

1

T209

1

T266

1

T412

1

all_values[1]

auto[0]

auto[1]

auto[1]

25

1

T274

1

T409

1

T410

2

all_values[1]

auto[1]

auto[0]

auto[1]

51

1

T274

2

T266

1

T409

1

all_values[1]

auto[1]

auto[1]

auto[1]

54

1

T207

1

T209

2

T409

2

all_values[2]

auto[0]

auto[0]

auto[0]

50

1

T409

4

T413

2

T414

1

all_values[2]

auto[0]

auto[0]

auto[1]

25

1

T207

1

T266

1

T410

1

all_values[2]

auto[0]

auto[1]

auto[0]

39

1

T209

2

T274

1

T410

4

all_values[2]

auto[0]

auto[1]

auto[1]

40

1

T207

1

T209

1

T274

1

all_values[2]

auto[1]

auto[0]

auto[1]

63

1

T207

1

T274

2

T266

1

all_values[2]

auto[1]

auto[1]

auto[1]

52

1

T207

1

T209

1

T266

1

all_values[3]

auto[0]

auto[0]

auto[0]

52

1

T207

1

T209

2

T274

2

all_values[3]

auto[0]

auto[0]

auto[1]

23

1

T207

1

T410

1

T411

1

all_values[3]

auto[0]

auto[1]

auto[0]

47

1

T209

1

T266

1

T409

2

all_values[3]

auto[0]

auto[1]

auto[1]

33

1

T413

1

T410

1

T411

1

all_values[3]

auto[1]

auto[0]

auto[1]

67

1

T207

1

T209

1

T274

1

all_values[3]

auto[1]

auto[1]

auto[1]

47

1

T207

1

T274

1

T266

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal