Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	75621	1			T341	148		T19	641		T300	12
accum_cnt_1000	168818	1			T10	15		T42	4		T161	34
accum_cnt_100	19583	1			T12	3		T96	6		T134	1
accum_cnt_50	45447	1			T1	3		T12	44		T14	2
accum_cnt_10	133456	1			T1	4		T9	17		T12	7
accum_cnt_0	346542	1			T1	25		T9	51		T12	54

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	206652	1			T1	8		T9	17		T12	27
class_index[0x1]	206652	1			T1	8		T9	17		T12	27
class_index[0x2]	206652	1			T1	8		T9	17		T12	27
class_index[0x3]	206652	1			T1	8		T9	17		T12	27

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	18774	1			T19	87		T162	89		T342	342
class_index[0x0]	accum_cnt_1000	48779	1			T113	9		T78	53		T63	94
class_index[0x0]	accum_cnt_100	5345	1			T12	3		T134	1		T43	21
class_index[0x0]	accum_cnt_50	11421	1			T1	3		T12	21		T20	9
class_index[0x0]	accum_cnt_10	35360	1			T1	4		T9	17		T12	3
class_index[0x0]	accum_cnt_0	81276	1			T1	1		T10	20		T18	1
class_index[0x1]	accum_cnt_2000	18140	1			T341	4		T19	248		T162	166
class_index[0x1]	accum_cnt_1000	39956	1			T284	6		T343	21		T341	588
class_index[0x1]	accum_cnt_100	4155	1			T96	6		T43	13		T284	20
class_index[0x1]	accum_cnt_50	10812	1			T12	23		T96	26		T97	20
class_index[0x1]	accum_cnt_10	29445	1			T12	4		T14	13		T17	11
class_index[0x1]	accum_cnt_0	93975	1			T1	8		T9	17		T10	20
class_index[0x2]	accum_cnt_2000	17127	1			T341	144		T65	4		T162	19
class_index[0x2]	accum_cnt_1000	41187	1			T10	15		T161	34		T344	45
class_index[0x2]	accum_cnt_100	5425	1			T161	17		T344	21		T345	9
class_index[0x2]	accum_cnt_50	11975	1			T20	8		T97	16		T43	2
class_index[0x2]	accum_cnt_10	32241	1			T10	5		T14	10		T20	7
class_index[0x2]	accum_cnt_0	89927	1			T1	8		T9	17		T12	27
class_index[0x3]	accum_cnt_2000	21580	1			T19	306		T300	12		T346	421
class_index[0x3]	accum_cnt_1000	38896	1			T42	4		T284	3		T344	40
class_index[0x3]	accum_cnt_100	4658	1			T87	14		T284	17		T344	24
class_index[0x3]	accum_cnt_50	11239	1			T14	2		T15	11		T131	19
class_index[0x3]	accum_cnt_10	36410	1			T14	12		T17	6		T15	5
class_index[0x3]	accum_cnt_0	81364	1			T1	8		T9	17		T12	27