Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2324	1			T46	17		T23	1		T48	2
alert[0x1]	2935	1			T48	3		T148	1		T114	36
alert[0x2]	7977	1			T275	1		T32	4		T19	6
alert[0x3]	3410	1			T86	1		T285	2		T117	2
alert[0x4]	5720	1			T267	1		T347	1		T115	1
alert[0x5]	2841	1			T92	1		T30	1		T50	80
alert[0x6]	2869	1			T347	1		T263	1		T148	11
alert[0x7]	5208	1			T10	3		T275	1		T279	1
alert[0x8]	6010	1			T107	2		T50	1		T86	1
alert[0x9]	5447	1			T48	2		T263	1		T19	2402
alert[0xa]	12620	1			T24	1		T114	3		T331	1
alert[0xb]	4105	1			T23	1		T267	2		T90	5
alert[0xc]	4028	1			T59	3		T43	5		T107	6
alert[0xd]	6162	1			T113	1		T50	17		T115	1
alert[0xe]	7423	1			T43	1		T348	1		T263	1
alert[0xf]	5051	1			T24	1		T92	1		T30	1
alert[0x10]	5584	1			T22	1		T113	12		T86	1
alert[0x11]	2215	1			T46	3		T347	1		T263	1
alert[0x12]	7491	1			T17	2		T48	3		T112	4
alert[0x13]	4899	1			T275	2		T19	13		T349	1
alert[0x14]	3899	1			T263	1		T285	1		T350	1
alert[0x15]	1979	1			T24	1		T92	1		T50	12
alert[0x16]	2990	1			T46	13		T48	1		T33	7
alert[0x17]	5892	1			T275	1		T35	18		T351	1
alert[0x18]	3261	1			T351	1		T86	1		T64	19
alert[0x19]	4716	1			T92	1		T50	4		T19	6
alert[0x1a]	2284	1			T347	1		T33	2		T263	1
alert[0x1b]	8105	1			T347	1		T35	1		T114	5
alert[0x1c]	3202	1			T17	1		T33	2		T352	1
alert[0x1d]	9151	1			T348	1		T115	1		T350	1
alert[0x1e]	6854	1			T114	9		T115	16		T353	1
alert[0x1f]	3908	1			T92	1		T33	1		T352	1
alert[0x20]	5704	1			T48	2		T35	4		T352	1
alert[0x21]	3302	1			T43	2		T267	1		T275	1
alert[0x22]	5516	1			T347	1		T285	2		T350	1
alert[0x23]	4048	1			T30	1		T275	1		T33	1
alert[0x24]	5687	1			T24	1		T275	2		T263	1
alert[0x25]	2734	1			T59	4		T263	1		T351	1
alert[0x26]	8871	1			T10	3		T43	1		T347	2
alert[0x27]	12410	1			T92	1		T48	4		T30	1
alert[0x28]	4611	1			T48	1		T112	6		T351	2
alert[0x29]	4539	1			T347	1		T113	3		T19	9
alert[0x2a]	9680	1			T46	10		T352	2		T62	1
alert[0x2b]	6405	1			T50	8		T86	1		T19	996
alert[0x2c]	4782	1			T46	1		T23	1		T24	1
alert[0x2d]	2433	1			T92	1		T347	2		T275	1
alert[0x2e]	6450	1			T35	5		T50	9		T114	10
alert[0x2f]	10207	1			T30	1		T50	99		T114	5
alert[0x30]	5852	1			T24	1		T103	1		T48	1
alert[0x31]	1999	1			T103	17		T30	1		T347	1
alert[0x32]	3527	1			T267	1		T33	2		T352	1
alert[0x33]	4672	1			T10	4		T33	1		T117	5
alert[0x34]	5503	1			T50	2		T115	12		T308	34
alert[0x35]	6910	1			T22	1		T92	1		T348	1
alert[0x36]	6916	1			T19	148		T65	2		T70	15
alert[0x37]	5350	1			T22	1		T92	1		T85	1
alert[0x38]	6892	1			T348	1		T347	1		T275	1
alert[0x39]	7038	1			T85	1		T117	2		T150	7
alert[0x3a]	6847	1			T267	1		T347	1		T275	1
alert[0x3b]	5069	1			T23	1		T348	1		T48	2
alert[0x3c]	2748	1			T30	1		T113	6		T115	1
alert[0x3d]	5463	1			T92	1		T354	11		T65	2
alert[0x3e]	10087	1			T24	1		T347	1		T275	1
alert[0x3f]	8084	1			T103	5		T355	1		T67	126
alert[0x40]	7398	1			T48	2		T35	10		T19	4416

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	102234	1			T10	3		T17	2		T46	23
class_i[0x1]	123812	1			T10	3		T46	21		T43	2
class_i[0x2]	28111	1			T43	7		T107	2		T22	1
class_i[0x3]	104137	1			T10	4		T17	1		T107	6

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

357718

1

T10

10

T17

3

T46

44

alert_ping_fail

576

1

T22

3

T23

4

T24

7

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2316	1			T46	17		T48	2		T33	9
alert_integrity_fail	alert[0x1]	2926	1			T48	3		T148	1		T114	36
alert_integrity_fail	alert[0x2]	7974	1			T32	4		T19	6		T117	2
alert_integrity_fail	alert[0x3]	3400	1			T117	2		T68	2		T70	310
alert_integrity_fail	alert[0x4]	5711	1			T115	1		T19	220		T67	4
alert_integrity_fail	alert[0x5]	2826	1			T50	80		T19	36		T64	6
alert_integrity_fail	alert[0x6]	2857	1			T148	11		T145	1		T117	15
alert_integrity_fail	alert[0x7]	5198	1			T10	3		T67	44		T68	1
alert_integrity_fail	alert[0x8]	5997	1			T107	2		T50	1		T19	95
alert_integrity_fail	alert[0x9]	5440	1			T48	2		T19	2402		T67	138
alert_integrity_fail	alert[0xa]	12611	1			T114	3		T64	2		T354	2
alert_integrity_fail	alert[0xb]	4098	1			T90	5		T19	115		T64	1
alert_integrity_fail	alert[0xc]	4020	1			T59	3		T43	5		T107	6
alert_integrity_fail	alert[0xd]	6158	1			T113	1		T50	17		T115	1
alert_integrity_fail	alert[0xe]	7416	1			T43	1		T114	1		T356	1
alert_integrity_fail	alert[0xf]	5034	1			T117	9		T354	9		T162	9
alert_integrity_fail	alert[0x10]	5577	1			T113	12		T19	241		T64	4
alert_integrity_fail	alert[0x11]	2208	1			T46	3		T68	1		T127	3
alert_integrity_fail	alert[0x12]	7487	1			T17	2		T48	3		T112	4
alert_integrity_fail	alert[0x13]	4886	1			T19	13		T67	33		T68	31
alert_integrity_fail	alert[0x14]	3889	1			T67	40		T357	383		T358	2
alert_integrity_fail	alert[0x15]	1965	1			T50	12		T19	16		T64	4
alert_integrity_fail	alert[0x16]	2980	1			T46	13		T48	1		T33	7
alert_integrity_fail	alert[0x17]	5890	1			T35	18		T115	4		T19	39
alert_integrity_fail	alert[0x18]	3249	1			T64	19		T68	3		T127	5
alert_integrity_fail	alert[0x19]	4710	1			T50	4		T19	6		T150	6
alert_integrity_fail	alert[0x1a]	2275	1			T33	2		T114	4		T162	2
alert_integrity_fail	alert[0x1b]	8089	1			T35	1		T114	5		T19	104
alert_integrity_fail	alert[0x1c]	3196	1			T17	1		T33	2		T50	28
alert_integrity_fail	alert[0x1d]	9141	1			T115	1		T137	8		T357	29
alert_integrity_fail	alert[0x1e]	6847	1			T114	9		T115	16		T359	183
alert_integrity_fail	alert[0x1f]	3895	1			T33	1		T50	8		T162	1
alert_integrity_fail	alert[0x20]	5691	1			T48	2		T35	4		T113	1
alert_integrity_fail	alert[0x21]	3294	1			T43	2		T360	1		T137	82
alert_integrity_fail	alert[0x22]	5504	1			T361	1		T142	1		T362	2
alert_integrity_fail	alert[0x23]	4038	1			T33	1		T35	3		T162	1
alert_integrity_fail	alert[0x24]	5677	1			T19	17		T117	26		T360	4
alert_integrity_fail	alert[0x25]	2727	1			T59	4		T114	1		T32	3
alert_integrity_fail	alert[0x26]	8860	1			T10	3		T43	1		T35	12
alert_integrity_fail	alert[0x27]	12405	1			T48	4		T148	2		T50	15
alert_integrity_fail	alert[0x28]	4601	1			T48	1		T112	6		T50	4
alert_integrity_fail	alert[0x29]	4526	1			T113	3		T19	9		T67	17
alert_integrity_fail	alert[0x2a]	9674	1			T46	10		T62	1		T19	20
alert_integrity_fail	alert[0x2b]	6394	1			T50	8		T19	996		T150	3
alert_integrity_fail	alert[0x2c]	4771	1			T46	1		T50	1		T354	4
alert_integrity_fail	alert[0x2d]	2424	1			T68	8		T359	57		T363	39
alert_integrity_fail	alert[0x2e]	6440	1			T35	5		T50	9		T114	10
alert_integrity_fail	alert[0x2f]	10200	1			T50	99		T114	5		T19	45
alert_integrity_fail	alert[0x30]	5841	1			T103	1		T48	1		T50	93
alert_integrity_fail	alert[0x31]	1990	1			T103	17		T148	3		T50	4
alert_integrity_fail	alert[0x32]	3519	1			T33	2		T50	50		T64	2
alert_integrity_fail	alert[0x33]	4666	1			T10	4		T33	1		T117	5
alert_integrity_fail	alert[0x34]	5493	1			T50	2		T115	12		T308	34
alert_integrity_fail	alert[0x35]	6903	1			T117	4		T354	7		T162	4
alert_integrity_fail	alert[0x36]	6915	1			T19	148		T65	2		T70	15
alert_integrity_fail	alert[0x37]	5338	1			T127	3		T71	184		T137	1979
alert_integrity_fail	alert[0x38]	6882	1			T19	7		T68	3		T70	283
alert_integrity_fail	alert[0x39]	7031	1			T117	2		T150	7		T162	4
alert_integrity_fail	alert[0x3a]	6840	1			T32	5		T70	12		T71	1098
alert_integrity_fail	alert[0x3b]	5057	1			T48	2		T64	6		T364	7
alert_integrity_fail	alert[0x3c]	2740	1			T113	6		T115	1		T117	7
alert_integrity_fail	alert[0x3d]	5459	1			T354	11		T65	2		T162	1
alert_integrity_fail	alert[0x3e]	10079	1			T148	2		T50	4		T114	2
alert_integrity_fail	alert[0x3f]	8080	1			T103	5		T67	126		T324	3
alert_integrity_fail	alert[0x40]	7393	1			T48	2		T35	10		T19	4416
alert_ping_fail	alert[0x0]	8	1			T23	1		T263	1		T285	1
alert_ping_fail	alert[0x1]	9	1			T86	2		T349	1		T365	1
alert_ping_fail	alert[0x2]	3	1			T275	1		T353	1		T366	1
alert_ping_fail	alert[0x3]	10	1			T86	1		T285	2		T349	1
alert_ping_fail	alert[0x4]	9	1			T267	1		T347	1		T355	1
alert_ping_fail	alert[0x5]	15	1			T92	1		T30	1		T285	1
alert_ping_fail	alert[0x6]	12	1			T347	1		T263	1		T350	1
alert_ping_fail	alert[0x7]	10	1			T275	1		T279	1		T365	1
alert_ping_fail	alert[0x8]	13	1			T86	1		T331	1		T350	1
alert_ping_fail	alert[0x9]	7	1			T263	1		T355	1		T367	1
alert_ping_fail	alert[0xa]	9	1			T24	1		T331	1		T368	1
alert_ping_fail	alert[0xb]	7	1			T23	1		T267	2		T92	1
alert_ping_fail	alert[0xc]	8	1			T30	1		T347	1		T368	1
alert_ping_fail	alert[0xd]	4	1			T349	1		T367	1		T369	1
alert_ping_fail	alert[0xe]	7	1			T348	1		T263	1		T370	1
alert_ping_fail	alert[0xf]	17	1			T24	1		T92	1		T30	1
alert_ping_fail	alert[0x10]	7	1			T22	1		T86	1		T355	1
alert_ping_fail	alert[0x11]	7	1			T347	1		T263	1		T285	1
alert_ping_fail	alert[0x12]	4	1			T355	1		T369	1		T371	1
alert_ping_fail	alert[0x13]	13	1			T275	2		T349	1		T367	1
alert_ping_fail	alert[0x14]	10	1			T263	1		T285	1		T350	1
alert_ping_fail	alert[0x15]	14	1			T24	1		T92	1		T86	1
alert_ping_fail	alert[0x16]	10	1			T263	1		T368	1		T278	1
alert_ping_fail	alert[0x17]	2	1			T275	1		T351	1		-	-
alert_ping_fail	alert[0x18]	12	1			T351	1		T86	1		T355	1
alert_ping_fail	alert[0x19]	6	1			T92	1		T368	1		T372	1
alert_ping_fail	alert[0x1a]	9	1			T347	1		T263	1		T373	1
alert_ping_fail	alert[0x1b]	16	1			T347	1		T349	1		T350	2
alert_ping_fail	alert[0x1c]	6	1			T352	1		T86	1		T374	1
alert_ping_fail	alert[0x1d]	10	1			T348	1		T350	1		T375	1
alert_ping_fail	alert[0x1e]	7	1			T353	1		T376	1		T377	1
alert_ping_fail	alert[0x1f]	13	1			T92	1		T352	1		T86	1
alert_ping_fail	alert[0x20]	13	1			T352	1		T86	2		T349	1
alert_ping_fail	alert[0x21]	8	1			T267	1		T275	1		T263	1
alert_ping_fail	alert[0x22]	12	1			T347	1		T285	2		T350	1
alert_ping_fail	alert[0x23]	10	1			T30	1		T275	1		T263	1
alert_ping_fail	alert[0x24]	10	1			T24	1		T275	2		T263	1
alert_ping_fail	alert[0x25]	7	1			T263	1		T351	1		T85	1
alert_ping_fail	alert[0x26]	11	1			T347	2		T378	2		T379	1
alert_ping_fail	alert[0x27]	5	1			T92	1		T30	1		T379	1
alert_ping_fail	alert[0x28]	10	1			T351	2		T380	1		T381	1
alert_ping_fail	alert[0x29]	13	1			T347	1		T378	1		T353	1
alert_ping_fail	alert[0x2a]	6	1			T352	2		T373	1		T370	1
alert_ping_fail	alert[0x2b]	11	1			T86	1		T279	1		T349	1
alert_ping_fail	alert[0x2c]	11	1			T23	1		T24	1		T285	2
alert_ping_fail	alert[0x2d]	9	1			T92	1		T347	2		T275	1
alert_ping_fail	alert[0x2e]	10	1			T355	1		T350	1		T278	1
alert_ping_fail	alert[0x2f]	7	1			T30	1		T85	1		T368	1
alert_ping_fail	alert[0x30]	11	1			T24	1		T30	1		T285	1
alert_ping_fail	alert[0x31]	9	1			T30	1		T347	1		T379	1
alert_ping_fail	alert[0x32]	8	1			T267	1		T352	1		T355	1
alert_ping_fail	alert[0x33]	6	1			T353	1		T365	1		T369	1
alert_ping_fail	alert[0x34]	10	1			T373	1		T370	1		T369	1
alert_ping_fail	alert[0x35]	7	1			T22	1		T92	1		T348	1
alert_ping_fail	alert[0x36]	1	1			T369	1		-	-		-	-
alert_ping_fail	alert[0x37]	12	1			T22	1		T92	1		T85	1
alert_ping_fail	alert[0x38]	10	1			T348	1		T347	1		T275	1
alert_ping_fail	alert[0x39]	7	1			T85	1		T378	2		T370	1
alert_ping_fail	alert[0x3a]	7	1			T267	1		T347	1		T275	1
alert_ping_fail	alert[0x3b]	12	1			T23	1		T348	1		T275	1
alert_ping_fail	alert[0x3c]	8	1			T30	1		T349	1		T278	2
alert_ping_fail	alert[0x3d]	4	1			T92	1		T373	1		T369	1
alert_ping_fail	alert[0x3e]	8	1			T24	1		T347	1		T275	1
alert_ping_fail	alert[0x3f]	4	1			T355	1		T370	1		T379	1
alert_ping_fail	alert[0x40]	5	1			T380	1		T382	1		T383	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	102020	1			T10	3		T17	2		T46	23
alert_integrity_fail	class_i[0x1]	123695	1			T10	3		T46	21		T43	2
alert_integrity_fail	class_i[0x2]	27960	1			T43	7		T107	2		T48	3
alert_integrity_fail	class_i[0x3]	104043	1			T10	4		T17	1		T107	6
alert_ping_fail	class_i[0x0]	214	1			T23	1		T24	7		T92	9
alert_ping_fail	class_i[0x1]	117	1			T22	1		T23	1		T267	3
alert_ping_fail	class_i[0x2]	151	1			T22	1		T23	1		T267	3
alert_ping_fail	class_i[0x3]	94	1			T22	1		T23	1		T347	3