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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.62 99.99 98.69 92.65 100.00 100.00 99.38 99.60


Total test records in report: 823
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T780 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.79602449 Sep 01 06:45:28 PM UTC 24 Sep 01 06:45:38 PM UTC 24 35710994 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3481410417 Sep 01 06:45:36 PM UTC 24 Sep 01 06:45:46 PM UTC 24 118900848 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1680522142 Sep 01 06:35:43 PM UTC 24 Sep 01 06:45:51 PM UTC 24 27969775888 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1666551573 Sep 01 06:32:14 PM UTC 24 Sep 01 06:45:54 PM UTC 24 16559945897 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.62292144 Sep 01 06:45:56 PM UTC 24 Sep 01 06:46:00 PM UTC 24 10066781 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.3079544698 Sep 01 06:45:54 PM UTC 24 Sep 01 06:46:07 PM UTC 24 974645187 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.3707779768 Sep 01 06:46:00 PM UTC 24 Sep 01 06:46:11 PM UTC 24 69851096 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3109603676 Sep 01 06:46:08 PM UTC 24 Sep 01 06:46:19 PM UTC 24 137704799 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2574358027 Sep 01 06:44:30 PM UTC 24 Sep 01 06:46:31 PM UTC 24 2743899878 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.2506399430 Sep 01 06:46:20 PM UTC 24 Sep 01 06:46:32 PM UTC 24 169751862 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.4233354033 Sep 01 06:46:32 PM UTC 24 Sep 01 06:46:36 PM UTC 24 16138270 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3168656121 Sep 01 06:46:32 PM UTC 24 Sep 01 06:46:37 PM UTC 24 113384394 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.766126266 Sep 01 06:46:08 PM UTC 24 Sep 01 06:46:38 PM UTC 24 250932244 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1079175748 Sep 01 06:42:42 PM UTC 24 Sep 01 06:46:41 PM UTC 24 1917407407 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2315278200 Sep 01 06:46:43 PM UTC 24 Sep 01 06:46:46 PM UTC 24 10159020 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.270470185 Sep 01 06:46:43 PM UTC 24 Sep 01 06:46:46 PM UTC 24 18182700 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.3874250873 Sep 01 06:46:43 PM UTC 24 Sep 01 06:46:46 PM UTC 24 9759848 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.3096280399 Sep 01 06:46:37 PM UTC 24 Sep 01 06:46:49 PM UTC 24 96048543 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.3395506459 Sep 01 06:46:47 PM UTC 24 Sep 01 06:46:50 PM UTC 24 7264143 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.4203726825 Sep 01 06:46:47 PM UTC 24 Sep 01 06:46:50 PM UTC 24 7386888 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.1552357269 Sep 01 06:46:47 PM UTC 24 Sep 01 06:46:50 PM UTC 24 10682646 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2458203411 Sep 01 06:38:02 PM UTC 24 Sep 01 06:46:53 PM UTC 24 5496697142 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.361976438 Sep 01 06:45:30 PM UTC 24 Sep 01 06:46:53 PM UTC 24 2768444777 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.3436226308 Sep 01 06:46:50 PM UTC 24 Sep 01 06:46:54 PM UTC 24 12442738 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1697002511 Sep 01 06:46:42 PM UTC 24 Sep 01 06:46:57 PM UTC 24 497595572 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.2160617146 Sep 01 06:46:54 PM UTC 24 Sep 01 06:46:57 PM UTC 24 11032603 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2108746138 Sep 01 06:46:54 PM UTC 24 Sep 01 06:46:57 PM UTC 24 19391365 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.2360698987 Sep 01 06:46:54 PM UTC 24 Sep 01 06:46:57 PM UTC 24 31264309 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.3400183660 Sep 01 06:46:54 PM UTC 24 Sep 01 06:46:57 PM UTC 24 9220470 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.1666157151 Sep 01 06:46:55 PM UTC 24 Sep 01 06:46:58 PM UTC 24 9921852 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1040804179 Sep 01 06:46:55 PM UTC 24 Sep 01 06:46:58 PM UTC 24 16568910 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3855589318 Sep 01 06:46:55 PM UTC 24 Sep 01 06:46:59 PM UTC 24 13855578 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2531429963 Sep 01 06:45:54 PM UTC 24 Sep 01 06:47:00 PM UTC 24 1189989099 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3580362299 Sep 01 06:46:57 PM UTC 24 Sep 01 06:47:00 PM UTC 24 9057720 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1022370030 Sep 01 06:46:58 PM UTC 24 Sep 01 06:47:01 PM UTC 24 14606548 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.161612065 Sep 01 06:46:58 PM UTC 24 Sep 01 06:47:02 PM UTC 24 8271290 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.863508357 Sep 01 06:46:58 PM UTC 24 Sep 01 06:47:02 PM UTC 24 8747856 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.2080680499 Sep 01 06:46:58 PM UTC 24 Sep 01 06:47:02 PM UTC 24 11295338 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.2552850122 Sep 01 06:46:58 PM UTC 24 Sep 01 06:47:02 PM UTC 24 8029484 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2664209728 Sep 01 06:47:00 PM UTC 24 Sep 01 06:47:03 PM UTC 24 14454677 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.3001995064 Sep 01 06:47:00 PM UTC 24 Sep 01 06:47:04 PM UTC 24 15554151 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.4072645522 Sep 01 06:47:00 PM UTC 24 Sep 01 06:47:04 PM UTC 24 58514788 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.1097758583 Sep 01 06:47:00 PM UTC 24 Sep 01 06:47:04 PM UTC 24 18503956 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2399633696 Sep 01 06:47:02 PM UTC 24 Sep 01 06:47:05 PM UTC 24 13216553 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.2285032132 Sep 01 06:47:02 PM UTC 24 Sep 01 06:47:06 PM UTC 24 8035406 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.2433172987 Sep 01 06:47:03 PM UTC 24 Sep 01 06:47:07 PM UTC 24 9705049 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.1266182520 Sep 01 06:47:03 PM UTC 24 Sep 01 06:47:07 PM UTC 24 7639078 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.1376202314 Sep 01 06:47:03 PM UTC 24 Sep 01 06:47:07 PM UTC 24 15219227 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.1630462454 Sep 01 06:47:03 PM UTC 24 Sep 01 06:47:07 PM UTC 24 7428798 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2559553640 Sep 01 06:34:00 PM UTC 24 Sep 01 06:47:33 PM UTC 24 17157502350 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2884427676 Sep 01 06:44:02 PM UTC 24 Sep 01 06:47:41 PM UTC 24 2940125050 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4032623886 Sep 01 06:46:38 PM UTC 24 Sep 01 06:47:41 PM UTC 24 2699705224 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1356204801 Sep 01 06:45:19 PM UTC 24 Sep 01 06:47:46 PM UTC 24 779394488 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.477362909 Sep 01 06:40:24 PM UTC 24 Sep 01 06:47:48 PM UTC 24 4736593548 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.841511845 Sep 01 06:39:58 PM UTC 24 Sep 01 06:48:32 PM UTC 24 5604310996 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.665586829 Sep 01 06:34:29 PM UTC 24 Sep 01 06:49:23 PM UTC 24 9212733663 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2809632128 Sep 01 06:42:32 PM UTC 24 Sep 01 06:49:59 PM UTC 24 2324341617 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3570982422 Sep 01 06:46:12 PM UTC 24 Sep 01 06:50:15 PM UTC 24 5535531421 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3519176216 Sep 01 06:43:32 PM UTC 24 Sep 01 06:50:38 PM UTC 24 9482479104 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2919719395 Sep 01 06:39:56 PM UTC 24 Sep 01 06:50:49 PM UTC 24 6315768958 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1181245649 Sep 01 06:45:47 PM UTC 24 Sep 01 06:51:01 PM UTC 24 2437934180 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3383384538 Sep 01 06:38:24 PM UTC 24 Sep 01 06:52:34 PM UTC 24 8810651211 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.776955316 Sep 01 06:43:58 PM UTC 24 Sep 01 06:52:57 PM UTC 24 24068868046 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2628585122 Sep 01 06:30:58 PM UTC 24 Sep 01 06:53:12 PM UTC 24 31526398750 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2252647189 Sep 01 06:44:29 PM UTC 24 Sep 01 06:53:57 PM UTC 24 14099973628 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1700743988 Sep 01 06:45:03 PM UTC 24 Sep 01 06:55:19 PM UTC 24 5994122571 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.112672799 Sep 01 06:39:24 PM UTC 24 Sep 01 06:55:20 PM UTC 24 17801874237 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2249418899 Sep 01 06:46:08 PM UTC 24 Sep 01 06:58:43 PM UTC 24 8677601959 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.511186193 Sep 01 06:45:39 PM UTC 24 Sep 01 06:59:55 PM UTC 24 8381489919 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2324255688 Sep 01 06:40:20 PM UTC 24 Sep 01 07:00:43 PM UTC 24 82117641558 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3846226368 Sep 01 06:37:44 PM UTC 24 Sep 01 07:01:25 PM UTC 24 16851128438 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3781129131 Sep 01 06:41:35 PM UTC 24 Sep 01 07:01:35 PM UTC 24 51957832251 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3557673618 Sep 01 06:43:24 PM UTC 24 Sep 01 07:05:08 PM UTC 24 31277115065 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.3204691698
Short name T12
Test name
Test status
Simulation time 3157519507 ps
CPU time 34.56 seconds
Started Sep 01 04:55:29 PM UTC 24
Finished Sep 01 04:56:05 PM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204691698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3204691698
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.1789610920
Short name T17
Test name
Test status
Simulation time 542337074 ps
CPU time 18.91 seconds
Started Sep 01 04:55:57 PM UTC 24
Finished Sep 01 04:56:17 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789610920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1789610920
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.720575640
Short name T25
Test name
Test status
Simulation time 1578669459 ps
CPU time 13.44 seconds
Started Sep 01 04:56:18 PM UTC 24
Finished Sep 01 04:56:33 PM UTC 24
Peak memory 263300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720575640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.720575640
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all_with_rand_reset.4192758669
Short name T32
Test name
Test status
Simulation time 4971759080 ps
CPU time 480.29 seconds
Started Sep 01 05:00:30 PM UTC 24
Finished Sep 01 05:08:37 PM UTC 24
Peak memory 279480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4192758669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.al
ert_handler_stress_all_with_rand_reset.4192758669
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.866916561
Short name T43
Test name
Test status
Simulation time 5301566003 ps
CPU time 93.2 seconds
Started Sep 01 04:56:00 PM UTC 24
Finished Sep 01 04:57:35 PM UTC 24
Peak memory 265016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866916561 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.866916561
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.1369860762
Short name T4
Test name
Test status
Simulation time 323248587 ps
CPU time 14.86 seconds
Started Sep 01 04:55:56 PM UTC 24
Finished Sep 01 04:56:12 PM UTC 24
Peak memory 297388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369860762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1369860762
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1424807111
Short name T211
Test name
Test status
Simulation time 3538378949 ps
CPU time 97.4 seconds
Started Sep 01 06:37:17 PM UTC 24
Finished Sep 01 06:38:57 PM UTC 24
Peak memory 252648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424807111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1424807111
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.4165300476
Short name T15
Test name
Test status
Simulation time 1504084799 ps
CPU time 33.23 seconds
Started Sep 01 04:55:56 PM UTC 24
Finished Sep 01 04:56:31 PM UTC 24
Peak memory 263324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165300476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.4165300476
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.3071439531
Short name T67
Test name
Test status
Simulation time 16574840196 ps
CPU time 1104.01 seconds
Started Sep 01 05:05:03 PM UTC 24
Finished Sep 01 05:23:41 PM UTC 24
Peak memory 285492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071439531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3071439531
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.2756602659
Short name T71
Test name
Test status
Simulation time 47577714449 ps
CPU time 2108.72 seconds
Started Sep 01 04:55:37 PM UTC 24
Finished Sep 01 05:31:11 PM UTC 24
Peak memory 304936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756602659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2756602659
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.1062553017
Short name T298
Test name
Test status
Simulation time 169884822025 ps
CPU time 2927.31 seconds
Started Sep 01 06:11:28 PM UTC 24
Finished Sep 01 07:00:51 PM UTC 24
Peak memory 314912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062553017 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.1062553017
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3249467419
Short name T171
Test name
Test status
Simulation time 3467191418 ps
CPU time 304.57 seconds
Started Sep 01 06:34:42 PM UTC 24
Finished Sep 01 06:39:51 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249467419 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.3249467419
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.1371703679
Short name T333
Test name
Test status
Simulation time 30709617614 ps
CPU time 2300.5 seconds
Started Sep 01 04:56:08 PM UTC 24
Finished Sep 01 05:34:57 PM UTC 24
Peak memory 302252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371703679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1371703679
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.1429088718
Short name T20
Test name
Test status
Simulation time 1259697134 ps
CPU time 28.91 seconds
Started Sep 01 04:55:56 PM UTC 24
Finished Sep 01 04:56:26 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429088718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1429088718
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.3322862848
Short name T137
Test name
Test status
Simulation time 63776622930 ps
CPU time 2144.99 seconds
Started Sep 01 04:57:13 PM UTC 24
Finished Sep 01 05:33:26 PM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322862848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3322862848
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.841511845
Short name T179
Test name
Test status
Simulation time 5604310996 ps
CPU time 506.39 seconds
Started Sep 01 06:39:58 PM UTC 24
Finished Sep 01 06:48:32 PM UTC 24
Peak memory 285604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841511845 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.841511845
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.2992423551
Short name T99
Test name
Test status
Simulation time 1851805131 ps
CPU time 46.36 seconds
Started Sep 01 04:57:41 PM UTC 24
Finished Sep 01 04:58:29 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992423551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2992423551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1666551573
Short name T176
Test name
Test status
Simulation time 16559945897 ps
CPU time 809.84 seconds
Started Sep 01 06:32:14 PM UTC 24
Finished Sep 01 06:45:54 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666551573 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shado
w_reg_errors_with_csr_rw.1666551573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.2172189258
Short name T288
Test name
Test status
Simulation time 121159503053 ps
CPU time 2443.63 seconds
Started Sep 01 05:58:38 PM UTC 24
Finished Sep 01 06:39:52 PM UTC 24
Peak memory 318336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172189258 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.2172189258
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.789647073
Short name T347
Test name
Test status
Simulation time 21198846302 ps
CPU time 518.09 seconds
Started Sep 01 04:55:37 PM UTC 24
Finished Sep 01 05:04:22 PM UTC 24
Peak memory 269444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789647073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.789647073
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2628585122
Short name T196
Test name
Test status
Simulation time 31526398750 ps
CPU time 1317.28 seconds
Started Sep 01 06:30:58 PM UTC 24
Finished Sep 01 06:53:12 PM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628585122 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shado
w_reg_errors_with_csr_rw.2628585122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.2235542834
Short name T340
Test name
Test status
Simulation time 32302265111 ps
CPU time 2256.76 seconds
Started Sep 01 05:03:13 PM UTC 24
Finished Sep 01 05:41:17 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235542834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2235542834
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.441117940
Short name T208
Test name
Test status
Simulation time 47782837 ps
CPU time 8.98 seconds
Started Sep 01 06:30:20 PM UTC 24
Finished Sep 01 06:30:31 PM UTC 24
Peak memory 262616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441117940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.441117940
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.3960564063
Short name T19
Test name
Test status
Simulation time 10399977586 ps
CPU time 984.83 seconds
Started Sep 01 04:57:52 PM UTC 24
Finished Sep 01 05:14:31 PM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960564063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3960564063
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.2255800941
Short name T411
Test name
Test status
Simulation time 8997055 ps
CPU time 2.42 seconds
Started Sep 01 06:38:59 PM UTC 24
Finished Sep 01 06:39:03 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255800941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2255800941
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3781129131
Short name T201
Test name
Test status
Simulation time 51957832251 ps
CPU time 1184.02 seconds
Started Sep 01 06:41:35 PM UTC 24
Finished Sep 01 07:01:35 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781129131 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad
ow_reg_errors_with_csr_rw.3781129131
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.2114871967
Short name T10
Test name
Test status
Simulation time 342826721 ps
CPU time 32.1 seconds
Started Sep 01 04:55:34 PM UTC 24
Finished Sep 01 04:56:07 PM UTC 24
Peak memory 269408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114871967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2114871967
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2804572717
Short name T167
Test name
Test status
Simulation time 2987620185 ps
CPU time 187.35 seconds
Started Sep 01 06:29:58 PM UTC 24
Finished Sep 01 06:33:09 PM UTC 24
Peak memory 279460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804572717 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.2804572717
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.3586529110
Short name T86
Test name
Test status
Simulation time 11791800467 ps
CPU time 520.09 seconds
Started Sep 01 05:02:01 PM UTC 24
Finished Sep 01 05:10:48 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586529110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3586529110
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.3940729316
Short name T107
Test name
Test status
Simulation time 3692605965 ps
CPU time 127.9 seconds
Started Sep 01 04:56:43 PM UTC 24
Finished Sep 01 04:58:54 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940729316 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.3940729316
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.2970531207
Short name T385
Test name
Test status
Simulation time 99486377105 ps
CPU time 3150.91 seconds
Started Sep 01 05:13:19 PM UTC 24
Finished Sep 01 06:06:28 PM UTC 24
Peak memory 298536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970531207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2970531207
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.2239757012
Short name T162
Test name
Test status
Simulation time 59243279099 ps
CPU time 1398.27 seconds
Started Sep 01 04:57:16 PM UTC 24
Finished Sep 01 05:20:52 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239757012 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.2239757012
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1181245649
Short name T195
Test name
Test status
Simulation time 2437934180 ps
CPU time 309.06 seconds
Started Sep 01 06:45:47 PM UTC 24
Finished Sep 01 06:51:01 PM UTC 24
Peak memory 285668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181245649 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.1181245649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.208662563
Short name T369
Test name
Test status
Simulation time 34598219506 ps
CPU time 329.1 seconds
Started Sep 01 05:48:15 PM UTC 24
Finished Sep 01 05:53:49 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208662563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.208662563
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all_with_rand_reset.3156632548
Short name T49
Test name
Test status
Simulation time 16213277675 ps
CPU time 128.25 seconds
Started Sep 01 05:01:17 PM UTC 24
Finished Sep 01 05:03:28 PM UTC 24
Peak memory 279804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3156632548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.al
ert_handler_stress_all_with_rand_reset.3156632548
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.112672799
Short name T199
Test name
Test status
Simulation time 17801874237 ps
CPU time 942.89 seconds
Started Sep 01 06:39:24 PM UTC 24
Finished Sep 01 06:55:20 PM UTC 24
Peak memory 285600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112672799 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow
_reg_errors_with_csr_rw.112672799
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.694959320
Short name T295
Test name
Test status
Simulation time 70523996785 ps
CPU time 3397.67 seconds
Started Sep 01 05:05:17 PM UTC 24
Finished Sep 01 06:02:36 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694959320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.694959320
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all_with_rand_reset.904977291
Short name T69
Test name
Test status
Simulation time 18516542357 ps
CPU time 227.07 seconds
Started Sep 01 05:24:41 PM UTC 24
Finished Sep 01 05:28:32 PM UTC 24
Peak memory 279492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=904977291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.al
ert_handler_stress_all_with_rand_reset.904977291
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.2846527013
Short name T393
Test name
Test status
Simulation time 46627126825 ps
CPU time 2532.95 seconds
Started Sep 01 05:02:03 PM UTC 24
Finished Sep 01 05:44:45 PM UTC 24
Peak memory 300512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846527013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2846527013
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.2020945409
Short name T376
Test name
Test status
Simulation time 13848610727 ps
CPU time 642.79 seconds
Started Sep 01 05:43:28 PM UTC 24
Finished Sep 01 05:54:19 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020945409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2020945409
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.1434334319
Short name T397
Test name
Test status
Simulation time 59974594887 ps
CPU time 1970.78 seconds
Started Sep 01 05:20:32 PM UTC 24
Finished Sep 01 05:53:45 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434334319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1434334319
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.2397496422
Short name T379
Test name
Test status
Simulation time 8184589082 ps
CPU time 350.59 seconds
Started Sep 01 05:41:17 PM UTC 24
Finished Sep 01 05:47:12 PM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397496422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2397496422
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.491264471
Short name T275
Test name
Test status
Simulation time 29563998816 ps
CPU time 425.85 seconds
Started Sep 01 04:57:15 PM UTC 24
Finished Sep 01 05:04:26 PM UTC 24
Peak memory 269188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491264471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.491264471
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.2306842379
Short name T136
Test name
Test status
Simulation time 4408060349 ps
CPU time 87.36 seconds
Started Sep 01 04:56:04 PM UTC 24
Finished Sep 01 04:57:34 PM UTC 24
Peak memory 263324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306842379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2306842379
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2324255688
Short name T420
Test name
Test status
Simulation time 82117641558 ps
CPU time 1208.64 seconds
Started Sep 01 06:40:20 PM UTC 24
Finished Sep 01 07:00:43 PM UTC 24
Peak memory 285800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324255688 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shad
ow_reg_errors_with_csr_rw.2324255688
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.2237129554
Short name T141
Test name
Test status
Simulation time 24854673615 ps
CPU time 2097 seconds
Started Sep 01 05:22:38 PM UTC 24
Finished Sep 01 05:58:00 PM UTC 24
Peak memory 295808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237129554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2237129554
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.1908669164
Short name T87
Test name
Test status
Simulation time 5654805980 ps
CPU time 146.95 seconds
Started Sep 01 04:55:33 PM UTC 24
Finished Sep 01 04:58:03 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908669164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1908669164
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.477362909
Short name T175
Test name
Test status
Simulation time 4736593548 ps
CPU time 437.04 seconds
Started Sep 01 06:40:24 PM UTC 24
Finished Sep 01 06:47:48 PM UTC 24
Peak memory 279460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477362909 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.477362909
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.4010818224
Short name T207
Test name
Test status
Simulation time 8615639 ps
CPU time 2.03 seconds
Started Sep 01 06:30:19 PM UTC 24
Finished Sep 01 06:30:22 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010818224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.4010818224
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3139936354
Short name T419
Test name
Test status
Simulation time 8207655429 ps
CPU time 262.87 seconds
Started Sep 01 06:33:16 PM UTC 24
Finished Sep 01 06:37:43 PM UTC 24
Peak memory 250460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139936354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3139936354
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.1264489281
Short name T712
Test name
Test status
Simulation time 230995043137 ps
CPU time 2707.49 seconds
Started Sep 01 06:28:00 PM UTC 24
Finished Sep 01 07:13:39 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264489281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1264489281
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.4113161193
Short name T316
Test name
Test status
Simulation time 889644478 ps
CPU time 42.39 seconds
Started Sep 01 06:26:55 PM UTC 24
Finished Sep 01 06:27:38 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113161193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4113161193
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.3285287611
Short name T120
Test name
Test status
Simulation time 32631131884 ps
CPU time 2300.74 seconds
Started Sep 01 05:29:50 PM UTC 24
Finished Sep 01 06:08:36 PM UTC 24
Peak memory 285820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285287611 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.3285287611
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.1101161885
Short name T363
Test name
Test status
Simulation time 27984431294 ps
CPU time 1252.96 seconds
Started Sep 01 05:15:37 PM UTC 24
Finished Sep 01 05:36:46 PM UTC 24
Peak memory 285824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101161885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1101161885
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.1840953332
Short name T319
Test name
Test status
Simulation time 227917753266 ps
CPU time 3480.82 seconds
Started Sep 01 06:00:58 PM UTC 24
Finished Sep 01 06:59:38 PM UTC 24
Peak memory 314840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840953332 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.1840953332
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.3162168351
Short name T387
Test name
Test status
Simulation time 17451782567 ps
CPU time 1744.73 seconds
Started Sep 01 05:04:11 PM UTC 24
Finished Sep 01 05:33:39 PM UTC 24
Peak memory 296068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162168351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3162168351
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.160790146
Short name T370
Test name
Test status
Simulation time 14961848036 ps
CPU time 804.21 seconds
Started Sep 01 05:32:12 PM UTC 24
Finished Sep 01 05:45:47 PM UTC 24
Peak memory 263368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160790146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.160790146
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.2468201430
Short name T280
Test name
Test status
Simulation time 107783296873 ps
CPU time 1941.52 seconds
Started Sep 01 05:45:30 PM UTC 24
Finished Sep 01 06:18:16 PM UTC 24
Peak memory 296060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468201430 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.2468201430
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.2185297593
Short name T382
Test name
Test status
Simulation time 8185488233 ps
CPU time 210.95 seconds
Started Sep 01 06:02:18 PM UTC 24
Finished Sep 01 06:05:52 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185297593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2185297593
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.289534149
Short name T70
Test name
Test status
Simulation time 13152121920 ps
CPU time 1564.33 seconds
Started Sep 01 05:04:23 PM UTC 24
Finished Sep 01 05:30:46 PM UTC 24
Peak memory 302204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289534149 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.289534149
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.2820508449
Short name T158
Test name
Test status
Simulation time 50234915626 ps
CPU time 4032.86 seconds
Started Sep 01 05:47:00 PM UTC 24
Finished Sep 01 06:55:03 PM UTC 24
Peak memory 315168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820508449 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.2820508449
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all_with_rand_reset.4106267602
Short name T48
Test name
Test status
Simulation time 5767675064 ps
CPU time 295 seconds
Started Sep 01 04:58:16 PM UTC 24
Finished Sep 01 05:03:15 PM UTC 24
Peak memory 279476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4106267602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.al
ert_handler_stress_all_with_rand_reset.4106267602
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.575989313
Short name T210
Test name
Test status
Simulation time 165216364 ps
CPU time 4.42 seconds
Started Sep 01 06:38:17 PM UTC 24
Finished Sep 01 06:38:23 PM UTC 24
Peak memory 250528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575989313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.575989313
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.2147472411
Short name T692
Test name
Test status
Simulation time 91071587151 ps
CPU time 2666.2 seconds
Started Sep 01 06:02:32 PM UTC 24
Finished Sep 01 06:47:29 PM UTC 24
Peak memory 315168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147472411 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.2147472411
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.589546050
Short name T3
Test name
Test status
Simulation time 72718374 ps
CPU time 3.49 seconds
Started Sep 01 04:55:54 PM UTC 24
Finished Sep 01 04:55:58 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589546050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.589546050
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1079175748
Short name T190
Test name
Test status
Simulation time 1917407407 ps
CPU time 234.28 seconds
Started Sep 01 06:42:42 PM UTC 24
Finished Sep 01 06:46:41 PM UTC 24
Peak memory 269088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079175748 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.1079175748
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.4003937949
Short name T40
Test name
Test status
Simulation time 31288405597 ps
CPU time 2065.13 seconds
Started Sep 01 05:36:17 PM UTC 24
Finished Sep 01 06:11:07 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003937949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4003937949
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.2122465300
Short name T13
Test name
Test status
Simulation time 197535046 ps
CPU time 4.65 seconds
Started Sep 01 04:56:00 PM UTC 24
Finished Sep 01 04:56:05 PM UTC 24
Peak memory 263168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122465300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2122465300
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.1531147161
Short name T251
Test name
Test status
Simulation time 161105592 ps
CPU time 5.56 seconds
Started Sep 01 05:02:36 PM UTC 24
Finished Sep 01 05:02:43 PM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531147161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1531147161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.196123056
Short name T252
Test name
Test status
Simulation time 16206104 ps
CPU time 4.3 seconds
Started Sep 01 05:04:27 PM UTC 24
Finished Sep 01 05:04:33 PM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196123056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.196123056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.1855898467
Short name T320
Test name
Test status
Simulation time 42499084382 ps
CPU time 2927.63 seconds
Started Sep 01 05:41:34 PM UTC 24
Finished Sep 01 06:30:56 PM UTC 24
Peak memory 300896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855898467 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.1855898467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all_with_rand_reset.3894015450
Short name T311
Test name
Test status
Simulation time 3094786116 ps
CPU time 266.79 seconds
Started Sep 01 06:13:14 PM UTC 24
Finished Sep 01 06:17:45 PM UTC 24
Peak memory 279548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3894015450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.a
lert_handler_stress_all_with_rand_reset.3894015450
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2626368038
Short name T241
Test name
Test status
Simulation time 5295525484 ps
CPU time 272.41 seconds
Started Sep 01 06:30:32 PM UTC 24
Finished Sep 01 06:35:09 PM UTC 24
Peak memory 252636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626368038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2626368038
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1356204801
Short name T193
Test name
Test status
Simulation time 779394488 ps
CPU time 143.38 seconds
Started Sep 01 06:45:19 PM UTC 24
Finished Sep 01 06:47:46 PM UTC 24
Peak memory 279324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356204801 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.1356204801
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.1395801837
Short name T21
Test name
Test status
Simulation time 41196927389 ps
CPU time 2467.96 seconds
Started Sep 01 05:58:12 PM UTC 24
Finished Sep 01 06:39:47 PM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395801837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1395801837
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.3675147566
Short name T160
Test name
Test status
Simulation time 63363844283 ps
CPU time 2690.37 seconds
Started Sep 01 06:09:09 PM UTC 24
Finished Sep 01 06:54:33 PM UTC 24
Peak memory 304992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675147566 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.3675147566
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.782370953
Short name T204
Test name
Test status
Simulation time 61280330 ps
CPU time 5.63 seconds
Started Sep 01 06:30:12 PM UTC 24
Finished Sep 01 06:30:19 PM UTC 24
Peak memory 250448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782370953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.782370953
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.4108828604
Short name T92
Test name
Test status
Simulation time 84216626059 ps
CPU time 303.56 seconds
Started Sep 01 04:56:07 PM UTC 24
Finished Sep 01 05:01:14 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108828604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4108828604
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.2336414528
Short name T351
Test name
Test status
Simulation time 3471054021 ps
CPU time 211.12 seconds
Started Sep 01 05:03:56 PM UTC 24
Finished Sep 01 05:07:32 PM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336414528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2336414528
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.3123154500
Short name T39
Test name
Test status
Simulation time 69120623545 ps
CPU time 1610.92 seconds
Started Sep 01 05:38:39 PM UTC 24
Finished Sep 01 06:05:49 PM UTC 24
Peak memory 318260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123154500 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.3123154500
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.1004500339
Short name T42
Test name
Test status
Simulation time 124523715 ps
CPU time 22.95 seconds
Started Sep 01 04:56:34 PM UTC 24
Finished Sep 01 04:56:58 PM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004500339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1004500339
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.3781251397
Short name T739
Test name
Test status
Simulation time 10685325 ps
CPU time 2.45 seconds
Started Sep 01 06:40:14 PM UTC 24
Finished Sep 01 06:40:17 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781251397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3781251397
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2919719395
Short name T197
Test name
Test status
Simulation time 6315768958 ps
CPU time 643.66 seconds
Started Sep 01 06:39:56 PM UTC 24
Finished Sep 01 06:50:49 PM UTC 24
Peak memory 281500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919719395 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad
ow_reg_errors_with_csr_rw.2919719395
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.3874962350
Short name T341
Test name
Test status
Simulation time 62765700595 ps
CPU time 586.65 seconds
Started Sep 01 04:56:00 PM UTC 24
Finished Sep 01 05:05:54 PM UTC 24
Peak memory 279352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874962350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3874962350
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.958420026
Short name T35
Test name
Test status
Simulation time 795984077 ps
CPU time 64.07 seconds
Started Sep 01 05:03:51 PM UTC 24
Finished Sep 01 05:04:57 PM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958420026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.958420026
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all_with_rand_reset.1554234438
Short name T115
Test name
Test status
Simulation time 9874145979 ps
CPU time 319.52 seconds
Started Sep 01 05:05:32 PM UTC 24
Finished Sep 01 05:10:56 PM UTC 24
Peak memory 281596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1554234438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.a
lert_handler_stress_all_with_rand_reset.1554234438
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.280809222
Short name T276
Test name
Test status
Simulation time 1970339410 ps
CPU time 36.45 seconds
Started Sep 01 05:07:32 PM UTC 24
Finished Sep 01 05:08:10 PM UTC 24
Peak memory 269156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280809222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.280809222
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.1699123354
Short name T282
Test name
Test status
Simulation time 659602665 ps
CPU time 26.24 seconds
Started Sep 01 05:12:09 PM UTC 24
Finished Sep 01 05:12:37 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699123354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1699123354
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.1851645184
Short name T308
Test name
Test status
Simulation time 334424922 ps
CPU time 26.88 seconds
Started Sep 01 05:15:34 PM UTC 24
Finished Sep 01 05:16:02 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851645184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1851645184
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.719364523
Short name T334
Test name
Test status
Simulation time 13612272395 ps
CPU time 1288.17 seconds
Started Sep 01 05:24:07 PM UTC 24
Finished Sep 01 05:45:51 PM UTC 24
Peak memory 295808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719364523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.719364523
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all_with_rand_reset.1453845390
Short name T268
Test name
Test status
Simulation time 9413764125 ps
CPU time 254.06 seconds
Started Sep 01 05:39:25 PM UTC 24
Finished Sep 01 05:43:43 PM UTC 24
Peak memory 279548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1453845390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.a
lert_handler_stress_all_with_rand_reset.1453845390
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.333847261
Short name T297
Test name
Test status
Simulation time 61851451781 ps
CPU time 2153.34 seconds
Started Sep 01 05:43:23 PM UTC 24
Finished Sep 01 06:19:42 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333847261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.333847261
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.2001044820
Short name T327
Test name
Test status
Simulation time 65271115675 ps
CPU time 4319.22 seconds
Started Sep 01 05:52:59 PM UTC 24
Finished Sep 01 07:05:49 PM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001044820 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.2001044820
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.755973208
Short name T395
Test name
Test status
Simulation time 466421346651 ps
CPU time 2187.37 seconds
Started Sep 01 06:15:30 PM UTC 24
Finished Sep 01 06:52:24 PM UTC 24
Peak memory 301956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755973208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.755973208
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.734849469
Short name T325
Test name
Test status
Simulation time 2334598813 ps
CPU time 83.81 seconds
Started Sep 01 06:23:31 PM UTC 24
Finished Sep 01 06:24:56 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734849469 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.734849469
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.2869952537
Short name T301
Test name
Test status
Simulation time 9989956904 ps
CPU time 1570.84 seconds
Started Sep 01 06:28:02 PM UTC 24
Finished Sep 01 06:54:34 PM UTC 24
Peak memory 300168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869952537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2869952537
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.401255041
Short name T7
Test name
Test status
Simulation time 492303173 ps
CPU time 36.16 seconds
Started Sep 01 04:56:00 PM UTC 24
Finished Sep 01 04:56:37 PM UTC 24
Peak memory 297388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401255041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.401255041
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3158946512
Short name T168
Test name
Test status
Simulation time 975349079 ps
CPU time 159.1 seconds
Started Sep 01 06:31:00 PM UTC 24
Finished Sep 01 06:33:42 PM UTC 24
Peak memory 269224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158946512 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.3158946512
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2912240047
Short name T212
Test name
Test status
Simulation time 609159004 ps
CPU time 59.54 seconds
Started Sep 01 06:42:18 PM UTC 24
Finished Sep 01 06:43:20 PM UTC 24
Peak memory 252436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912240047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2912240047
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3519176216
Short name T188
Test name
Test status
Simulation time 9482479104 ps
CPU time 420.34 seconds
Started Sep 01 06:43:32 PM UTC 24
Finished Sep 01 06:50:38 PM UTC 24
Peak memory 279528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519176216 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.3519176216
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.383500984
Short name T173
Test name
Test status
Simulation time 5380834271 ps
CPU time 387.75 seconds
Started Sep 01 06:35:47 PM UTC 24
Finished Sep 01 06:42:20 PM UTC 24
Peak memory 279528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383500984 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.383500984
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.3192654579
Short name T1
Test name
Test status
Simulation time 147353250 ps
CPU time 12.64 seconds
Started Sep 01 04:55:28 PM UTC 24
Finished Sep 01 04:55:42 PM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192654579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3192654579
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.2399032766
Short name T157
Test name
Test status
Simulation time 709179831 ps
CPU time 73.81 seconds
Started Sep 01 06:03:47 PM UTC 24
Finished Sep 01 06:05:03 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399032766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2399032766
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3604207958
Short name T213
Test name
Test status
Simulation time 93523329 ps
CPU time 3.71 seconds
Started Sep 01 06:44:11 PM UTC 24
Finished Sep 01 06:44:16 PM UTC 24
Peak memory 252508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604207958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3604207958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3865455147
Short name T218
Test name
Test status
Simulation time 30133280 ps
CPU time 4.54 seconds
Started Sep 01 06:40:09 PM UTC 24
Finished Sep 01 06:40:15 PM UTC 24
Peak memory 250388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865455147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3865455147
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3316383347
Short name T219
Test name
Test status
Simulation time 29573749 ps
CPU time 4.47 seconds
Started Sep 01 06:43:08 PM UTC 24
Finished Sep 01 06:43:13 PM UTC 24
Peak memory 250524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316383347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3316383347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.18879265
Short name T221
Test name
Test status
Simulation time 87617842 ps
CPU time 8.3 seconds
Started Sep 01 06:44:43 PM UTC 24
Finished Sep 01 06:44:52 PM UTC 24
Peak memory 250532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18879265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.18879265
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3057772222
Short name T214
Test name
Test status
Simulation time 114697319 ps
CPU time 7.14 seconds
Started Sep 01 06:36:31 PM UTC 24
Finished Sep 01 06:36:40 PM UTC 24
Peak memory 250400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057772222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3057772222
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.577135472
Short name T2
Test name
Test status
Simulation time 197693926 ps
CPU time 10.11 seconds
Started Sep 01 04:55:43 PM UTC 24
Finished Sep 01 04:55:55 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577135472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.577135472
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.832510381
Short name T205
Test name
Test status
Simulation time 34591320 ps
CPU time 4.7 seconds
Started Sep 01 06:31:39 PM UTC 24
Finished Sep 01 06:31:45 PM UTC 24
Peak memory 250524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832510381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.832510381
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4027619650
Short name T220
Test name
Test status
Simulation time 930282381 ps
CPU time 103.34 seconds
Started Sep 01 06:40:46 PM UTC 24
Finished Sep 01 06:42:31 PM UTC 24
Peak memory 252436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027619650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.4027619650
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.144261650
Short name T222
Test name
Test status
Simulation time 109852864 ps
CPU time 5.31 seconds
Started Sep 01 06:43:39 PM UTC 24
Finished Sep 01 06:43:45 PM UTC 24
Peak memory 250392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144261650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.144261650
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.74768927
Short name T223
Test name
Test status
Simulation time 57680152 ps
CPU time 3.4 seconds
Started Sep 01 06:45:21 PM UTC 24
Finished Sep 01 06:45:27 PM UTC 24
Peak memory 250468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74768927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.74768927
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2531429963
Short name T228
Test name
Test status
Simulation time 1189989099 ps
CPU time 63.75 seconds
Started Sep 01 06:45:54 PM UTC 24
Finished Sep 01 06:47:00 PM UTC 24
Peak memory 252572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531429963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2531429963
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3168656121
Short name T215
Test name
Test status
Simulation time 113384394 ps
CPU time 3.33 seconds
Started Sep 01 06:46:32 PM UTC 24
Finished Sep 01 06:46:37 PM UTC 24
Peak memory 250524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168656121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3168656121
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1561853541
Short name T216
Test name
Test status
Simulation time 101301131 ps
CPU time 4.13 seconds
Started Sep 01 06:34:04 PM UTC 24
Finished Sep 01 06:34:09 PM UTC 24
Peak memory 250400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561853541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1561853541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3256012636
Short name T227
Test name
Test status
Simulation time 604562580 ps
CPU time 49.34 seconds
Started Sep 01 06:34:55 PM UTC 24
Finished Sep 01 06:35:46 PM UTC 24
Peak memory 260644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256012636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3256012636
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2649499325
Short name T217
Test name
Test status
Simulation time 1257305917 ps
CPU time 57.44 seconds
Started Sep 01 06:38:58 PM UTC 24
Finished Sep 01 06:39:58 PM UTC 24
Peak memory 250396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649499325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2649499325
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4240594455
Short name T226
Test name
Test status
Simulation time 112212661 ps
CPU time 5.21 seconds
Started Sep 01 06:39:44 PM UTC 24
Finished Sep 01 06:39:51 PM UTC 24
Peak memory 252520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240594455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4240594455
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2438884022
Short name T773
Test name
Test status
Simulation time 47386130689 ps
CPU time 861.85 seconds
Started Sep 01 06:30:27 PM UTC 24
Finished Sep 01 06:45:00 PM UTC 24
Peak memory 250596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438884022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2438884022
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1375393145
Short name T225
Test name
Test status
Simulation time 31995570 ps
CPU time 8.18 seconds
Started Sep 01 06:30:49 PM UTC 24
Finished Sep 01 06:30:58 PM UTC 24
Peak memory 269088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375393145 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_
rw_with_rand_reset.1375393145
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.1985077500
Short name T224
Test name
Test status
Simulation time 1234218331 ps
CPU time 10.28 seconds
Started Sep 01 06:30:24 PM UTC 24
Finished Sep 01 06:30:35 PM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985077500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1985077500
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1352011845
Short name T233
Test name
Test status
Simulation time 272008422 ps
CPU time 37.1 seconds
Started Sep 01 06:30:36 PM UTC 24
Finished Sep 01 06:31:15 PM UTC 24
Peak memory 260704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352011845 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.1352011845
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.38927909
Short name T170
Test name
Test status
Simulation time 6257764130 ps
CPU time 629.61 seconds
Started Sep 01 06:28:50 PM UTC 24
Finished Sep 01 06:39:28 PM UTC 24
Peak memory 283552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38927909 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_
reg_errors_with_csr_rw.38927909
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.3708942236
Short name T272
Test name
Test status
Simulation time 1672965072 ps
CPU time 39.66 seconds
Started Sep 01 06:30:07 PM UTC 24
Finished Sep 01 06:30:48 PM UTC 24
Peak memory 262828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708942236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3708942236
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2125434131
Short name T242
Test name
Test status
Simulation time 6899594488 ps
CPU time 206.28 seconds
Started Sep 01 06:31:57 PM UTC 24
Finished Sep 01 06:35:27 PM UTC 24
Peak memory 250596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125434131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2125434131
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1795064983
Short name T422
Test name
Test status
Simulation time 3044890072 ps
CPU time 280.59 seconds
Started Sep 01 06:31:51 PM UTC 24
Finished Sep 01 06:36:36 PM UTC 24
Peak memory 250460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795064983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1795064983
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1370855852
Short name T234
Test name
Test status
Simulation time 76925691 ps
CPU time 7.15 seconds
Started Sep 01 06:31:47 PM UTC 24
Finished Sep 01 06:31:56 PM UTC 24
Peak memory 262692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370855852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1370855852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.809392522
Short name T416
Test name
Test status
Simulation time 126057908 ps
CPU time 8.29 seconds
Started Sep 01 06:32:04 PM UTC 24
Finished Sep 01 06:32:13 PM UTC 24
Peak memory 252504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809392522 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_r
w_with_rand_reset.809392522
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.1519734760
Short name T246
Test name
Test status
Simulation time 219206705 ps
CPU time 9.59 seconds
Started Sep 01 06:31:50 PM UTC 24
Finished Sep 01 06:32:00 PM UTC 24
Peak memory 250332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519734760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1519734760
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.783587058
Short name T209
Test name
Test status
Simulation time 9108063 ps
CPU time 2.04 seconds
Started Sep 01 06:31:46 PM UTC 24
Finished Sep 01 06:31:49 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783587058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.783587058
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.335021925
Short name T240
Test name
Test status
Simulation time 266770843 ps
CPU time 38.05 seconds
Started Sep 01 06:32:01 PM UTC 24
Finished Sep 01 06:32:40 PM UTC 24
Peak memory 262680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335021925 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.335021925
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.3462669529
Short name T715
Test name
Test status
Simulation time 824102168 ps
CPU time 31.88 seconds
Started Sep 01 06:31:16 PM UTC 24
Finished Sep 01 06:31:49 PM UTC 24
Peak memory 262956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462669529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3462669529
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3932666741
Short name T742
Test name
Test status
Simulation time 390657141 ps
CPU time 23.69 seconds
Started Sep 01 06:40:18 PM UTC 24
Finished Sep 01 06:40:43 PM UTC 24
Peak memory 264788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932666741 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem
_rw_with_rand_reset.3932666741
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.3620537329
Short name T740
Test name
Test status
Simulation time 22841164 ps
CPU time 4.07 seconds
Started Sep 01 06:40:15 PM UTC 24
Finished Sep 01 06:40:20 PM UTC 24
Peak memory 250464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620537329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3620537329
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2479432051
Short name T743
Test name
Test status
Simulation time 351453468 ps
CPU time 27.33 seconds
Started Sep 01 06:40:16 PM UTC 24
Finished Sep 01 06:40:45 PM UTC 24
Peak memory 260832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479432051 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.2479432051
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.2586120657
Short name T741
Test name
Test status
Simulation time 1296446762 ps
CPU time 20.36 seconds
Started Sep 01 06:40:02 PM UTC 24
Finished Sep 01 06:40:23 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586120657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2586120657
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2379828138
Short name T748
Test name
Test status
Simulation time 396077520 ps
CPU time 13.67 seconds
Started Sep 01 06:41:19 PM UTC 24
Finished Sep 01 06:41:34 PM UTC 24
Peak memory 252636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379828138 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem
_rw_with_rand_reset.2379828138
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.3162721487
Short name T747
Test name
Test status
Simulation time 210653722 ps
CPU time 9.1 seconds
Started Sep 01 06:41:08 PM UTC 24
Finished Sep 01 06:41:18 PM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162721487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3162721487
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.3433464330
Short name T746
Test name
Test status
Simulation time 9426307 ps
CPU time 2.29 seconds
Started Sep 01 06:41:05 PM UTC 24
Finished Sep 01 06:41:08 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433464330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3433464330
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2453135325
Short name T749
Test name
Test status
Simulation time 643987330 ps
CPU time 40.24 seconds
Started Sep 01 06:41:09 PM UTC 24
Finished Sep 01 06:41:51 PM UTC 24
Peak memory 260628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453135325 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.2453135325
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.3298904573
Short name T744
Test name
Test status
Simulation time 639217019 ps
CPU time 18.74 seconds
Started Sep 01 06:40:43 PM UTC 24
Finished Sep 01 06:41:04 PM UTC 24
Peak memory 266912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298904573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3298904573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2485511525
Short name T753
Test name
Test status
Simulation time 235398192 ps
CPU time 7.89 seconds
Started Sep 01 06:42:32 PM UTC 24
Finished Sep 01 06:42:42 PM UTC 24
Peak memory 250568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485511525 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem
_rw_with_rand_reset.2485511525
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.398480735
Short name T752
Test name
Test status
Simulation time 200820322 ps
CPU time 8.73 seconds
Started Sep 01 06:42:21 PM UTC 24
Finished Sep 01 06:42:31 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398480735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.398480735
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.1548681641
Short name T751
Test name
Test status
Simulation time 8899680 ps
CPU time 2.4 seconds
Started Sep 01 06:42:21 PM UTC 24
Finished Sep 01 06:42:24 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548681641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1548681641
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1476040126
Short name T754
Test name
Test status
Simulation time 172939588 ps
CPU time 40.25 seconds
Started Sep 01 06:42:25 PM UTC 24
Finished Sep 01 06:43:07 PM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476040126 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.1476040126
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3069001798
Short name T182
Test name
Test status
Simulation time 865912004 ps
CPU time 175.43 seconds
Started Sep 01 06:41:52 PM UTC 24
Finished Sep 01 06:44:50 PM UTC 24
Peak memory 279464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069001798 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.3069001798
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.3357898879
Short name T750
Test name
Test status
Simulation time 52739960 ps
CPU time 11.8 seconds
Started Sep 01 06:42:04 PM UTC 24
Finished Sep 01 06:42:17 PM UTC 24
Peak memory 262756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357898879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3357898879
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3568775904
Short name T758
Test name
Test status
Simulation time 146780485 ps
CPU time 8.74 seconds
Started Sep 01 06:43:21 PM UTC 24
Finished Sep 01 06:43:31 PM UTC 24
Peak memory 262876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568775904 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem
_rw_with_rand_reset.3568775904
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.3260000726
Short name T757
Test name
Test status
Simulation time 105956771 ps
CPU time 9.19 seconds
Started Sep 01 06:43:13 PM UTC 24
Finished Sep 01 06:43:23 PM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260000726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3260000726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.4108393980
Short name T756
Test name
Test status
Simulation time 19226013 ps
CPU time 2.1 seconds
Started Sep 01 06:43:09 PM UTC 24
Finished Sep 01 06:43:12 PM UTC 24
Peak memory 248424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108393980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.4108393980
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1924839629
Short name T764
Test name
Test status
Simulation time 588157832 ps
CPU time 54.13 seconds
Started Sep 01 06:43:14 PM UTC 24
Finished Sep 01 06:44:10 PM UTC 24
Peak memory 260628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924839629 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.1924839629
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2809632128
Short name T185
Test name
Test status
Simulation time 2324341617 ps
CPU time 440.01 seconds
Started Sep 01 06:42:32 PM UTC 24
Finished Sep 01 06:49:59 PM UTC 24
Peak memory 279448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809632128 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shad
ow_reg_errors_with_csr_rw.2809632128
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.2134283183
Short name T755
Test name
Test status
Simulation time 80922975 ps
CPU time 9.33 seconds
Started Sep 01 06:42:58 PM UTC 24
Finished Sep 01 06:43:08 PM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134283183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2134283183
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3784238798
Short name T763
Test name
Test status
Simulation time 231492230 ps
CPU time 14.46 seconds
Started Sep 01 06:43:54 PM UTC 24
Finished Sep 01 06:44:09 PM UTC 24
Peak memory 252572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784238798 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem
_rw_with_rand_reset.3784238798
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.1096951479
Short name T762
Test name
Test status
Simulation time 106274415 ps
CPU time 13.33 seconds
Started Sep 01 06:43:46 PM UTC 24
Finished Sep 01 06:44:01 PM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096951479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1096951479
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.64040308
Short name T759
Test name
Test status
Simulation time 19711831 ps
CPU time 2.33 seconds
Started Sep 01 06:43:43 PM UTC 24
Finished Sep 01 06:43:47 PM UTC 24
Peak memory 250340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64040308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.64040308
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2854521765
Short name T765
Test name
Test status
Simulation time 97934725 ps
CPU time 21.37 seconds
Started Sep 01 06:43:47 PM UTC 24
Finished Sep 01 06:44:10 PM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854521765 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.2854521765
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3557673618
Short name T823
Test name
Test status
Simulation time 31277115065 ps
CPU time 1287.54 seconds
Started Sep 01 06:43:24 PM UTC 24
Finished Sep 01 07:05:08 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557673618 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shad
ow_reg_errors_with_csr_rw.3557673618
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.1720264127
Short name T761
Test name
Test status
Simulation time 142443005 ps
CPU time 17.17 seconds
Started Sep 01 06:43:38 PM UTC 24
Finished Sep 01 06:43:57 PM UTC 24
Peak memory 262828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720264127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1720264127
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3313139009
Short name T768
Test name
Test status
Simulation time 38736268 ps
CPU time 9.63 seconds
Started Sep 01 06:44:17 PM UTC 24
Finished Sep 01 06:44:28 PM UTC 24
Peak memory 269020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313139009 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem
_rw_with_rand_reset.3313139009
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.1022202506
Short name T769
Test name
Test status
Simulation time 251213091 ps
CPU time 14.66 seconds
Started Sep 01 06:44:14 PM UTC 24
Finished Sep 01 06:44:30 PM UTC 24
Peak memory 250400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022202506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1022202506
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.759311293
Short name T767
Test name
Test status
Simulation time 29274546 ps
CPU time 2.34 seconds
Started Sep 01 06:44:11 PM UTC 24
Finished Sep 01 06:44:15 PM UTC 24
Peak memory 250344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759311293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.759311293
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2759223284
Short name T770
Test name
Test status
Simulation time 90454742 ps
CPU time 20.22 seconds
Started Sep 01 06:44:16 PM UTC 24
Finished Sep 01 06:44:37 PM UTC 24
Peak memory 252440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759223284 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.2759223284
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2884427676
Short name T184
Test name
Test status
Simulation time 2940125050 ps
CPU time 215.49 seconds
Started Sep 01 06:44:02 PM UTC 24
Finished Sep 01 06:47:41 PM UTC 24
Peak memory 279448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884427676 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.2884427676
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.776955316
Short name T200
Test name
Test status
Simulation time 24068868046 ps
CPU time 531.45 seconds
Started Sep 01 06:43:58 PM UTC 24
Finished Sep 01 06:52:57 PM UTC 24
Peak memory 279532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776955316 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shado
w_reg_errors_with_csr_rw.776955316
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.1711440143
Short name T771
Test name
Test status
Simulation time 5761554427 ps
CPU time 30.39 seconds
Started Sep 01 06:44:10 PM UTC 24
Finished Sep 01 06:44:42 PM UTC 24
Peak memory 262880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711440143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1711440143
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2357679206
Short name T777
Test name
Test status
Simulation time 2616775562 ps
CPU time 17.29 seconds
Started Sep 01 06:45:02 PM UTC 24
Finished Sep 01 06:45:20 PM UTC 24
Peak memory 252628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357679206 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem
_rw_with_rand_reset.2357679206
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.2779349502
Short name T774
Test name
Test status
Simulation time 281717853 ps
CPU time 7.92 seconds
Started Sep 01 06:44:53 PM UTC 24
Finished Sep 01 06:45:02 PM UTC 24
Peak memory 250400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779349502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2779349502
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.1443080485
Short name T772
Test name
Test status
Simulation time 15389282 ps
CPU time 1.97 seconds
Started Sep 01 06:44:51 PM UTC 24
Finished Sep 01 06:44:54 PM UTC 24
Peak memory 246796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443080485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1443080485
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3075150517
Short name T775
Test name
Test status
Simulation time 176985384 ps
CPU time 21.88 seconds
Started Sep 01 06:44:55 PM UTC 24
Finished Sep 01 06:45:18 PM UTC 24
Peak memory 260768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075150517 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.3075150517
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2574358027
Short name T191
Test name
Test status
Simulation time 2743899878 ps
CPU time 118.55 seconds
Started Sep 01 06:44:30 PM UTC 24
Finished Sep 01 06:46:31 PM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574358027 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.2574358027
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2252647189
Short name T186
Test name
Test status
Simulation time 14099973628 ps
CPU time 560.16 seconds
Started Sep 01 06:44:29 PM UTC 24
Finished Sep 01 06:53:57 PM UTC 24
Peak memory 283552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252647189 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad
ow_reg_errors_with_csr_rw.2252647189
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.1665337832
Short name T776
Test name
Test status
Simulation time 1502635905 ps
CPU time 38.69 seconds
Started Sep 01 06:44:38 PM UTC 24
Finished Sep 01 06:45:19 PM UTC 24
Peak memory 262892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665337832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1665337832
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3481410417
Short name T781
Test name
Test status
Simulation time 118900848 ps
CPU time 8.51 seconds
Started Sep 01 06:45:36 PM UTC 24
Finished Sep 01 06:45:46 PM UTC 24
Peak memory 262812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481410417 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem
_rw_with_rand_reset.3481410417
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.79602449
Short name T780
Test name
Test status
Simulation time 35710994 ps
CPU time 8.86 seconds
Started Sep 01 06:45:28 PM UTC 24
Finished Sep 01 06:45:38 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79602449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_han
dler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.79602449
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.3878382911
Short name T778
Test name
Test status
Simulation time 9352000 ps
CPU time 2.49 seconds
Started Sep 01 06:45:24 PM UTC 24
Finished Sep 01 06:45:28 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878382911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3878382911
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.361976438
Short name T796
Test name
Test status
Simulation time 2768444777 ps
CPU time 80.8 seconds
Started Sep 01 06:45:30 PM UTC 24
Finished Sep 01 06:46:53 PM UTC 24
Peak memory 262880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361976438 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.361976438
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1700743988
Short name T421
Test name
Test status
Simulation time 5994122571 ps
CPU time 607.78 seconds
Started Sep 01 06:45:03 PM UTC 24
Finished Sep 01 06:55:19 PM UTC 24
Peak memory 279656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700743988 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad
ow_reg_errors_with_csr_rw.1700743988
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.3155928308
Short name T779
Test name
Test status
Simulation time 62034097 ps
CPU time 12.59 seconds
Started Sep 01 06:45:20 PM UTC 24
Finished Sep 01 06:45:35 PM UTC 24
Peak memory 262756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155928308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3155928308
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3109603676
Short name T785
Test name
Test status
Simulation time 137704799 ps
CPU time 9.91 seconds
Started Sep 01 06:46:08 PM UTC 24
Finished Sep 01 06:46:19 PM UTC 24
Peak memory 268884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109603676 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem
_rw_with_rand_reset.3109603676
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.3707779768
Short name T784
Test name
Test status
Simulation time 69851096 ps
CPU time 9.15 seconds
Started Sep 01 06:46:00 PM UTC 24
Finished Sep 01 06:46:11 PM UTC 24
Peak memory 250464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707779768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3707779768
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.62292144
Short name T782
Test name
Test status
Simulation time 10066781 ps
CPU time 2.34 seconds
Started Sep 01 06:45:56 PM UTC 24
Finished Sep 01 06:46:00 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62292144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.62292144
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.766126266
Short name T788
Test name
Test status
Simulation time 250932244 ps
CPU time 28.6 seconds
Started Sep 01 06:46:08 PM UTC 24
Finished Sep 01 06:46:38 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766126266 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.766126266
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.511186193
Short name T202
Test name
Test status
Simulation time 8381489919 ps
CPU time 844.19 seconds
Started Sep 01 06:45:39 PM UTC 24
Finished Sep 01 06:59:55 PM UTC 24
Peak memory 279460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511186193 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shado
w_reg_errors_with_csr_rw.511186193
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.3079544698
Short name T783
Test name
Test status
Simulation time 974645187 ps
CPU time 11.62 seconds
Started Sep 01 06:45:54 PM UTC 24
Finished Sep 01 06:46:07 PM UTC 24
Peak memory 266852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079544698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3079544698
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1697002511
Short name T798
Test name
Test status
Simulation time 497595572 ps
CPU time 12.89 seconds
Started Sep 01 06:46:42 PM UTC 24
Finished Sep 01 06:46:57 PM UTC 24
Peak memory 250652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697002511 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem
_rw_with_rand_reset.1697002511
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.3096280399
Short name T792
Test name
Test status
Simulation time 96048543 ps
CPU time 11.57 seconds
Started Sep 01 06:46:37 PM UTC 24
Finished Sep 01 06:46:49 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096280399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3096280399
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.4233354033
Short name T787
Test name
Test status
Simulation time 16138270 ps
CPU time 2.41 seconds
Started Sep 01 06:46:32 PM UTC 24
Finished Sep 01 06:46:36 PM UTC 24
Peak memory 250408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233354033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.4233354033
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4032623886
Short name T822
Test name
Test status
Simulation time 2699705224 ps
CPU time 61.62 seconds
Started Sep 01 06:46:38 PM UTC 24
Finished Sep 01 06:47:41 PM UTC 24
Peak memory 260696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032623886 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.4032623886
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3570982422
Short name T189
Test name
Test status
Simulation time 5535531421 ps
CPU time 239.39 seconds
Started Sep 01 06:46:12 PM UTC 24
Finished Sep 01 06:50:15 PM UTC 24
Peak memory 285732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570982422 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.3570982422
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2249418899
Short name T203
Test name
Test status
Simulation time 8677601959 ps
CPU time 744.63 seconds
Started Sep 01 06:46:08 PM UTC 24
Finished Sep 01 06:58:43 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249418899 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad
ow_reg_errors_with_csr_rw.2249418899
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.2506399430
Short name T786
Test name
Test status
Simulation time 169751862 ps
CPU time 10.68 seconds
Started Sep 01 06:46:20 PM UTC 24
Finished Sep 01 06:46:32 PM UTC 24
Peak memory 262824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506399430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2506399430
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1845264446
Short name T245
Test name
Test status
Simulation time 1138421481 ps
CPU time 230.87 seconds
Started Sep 01 06:33:22 PM UTC 24
Finished Sep 01 06:37:16 PM UTC 24
Peak memory 252380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845264446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1845264446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.762320207
Short name T235
Test name
Test status
Simulation time 66212836 ps
CPU time 9.59 seconds
Started Sep 01 06:33:10 PM UTC 24
Finished Sep 01 06:33:21 PM UTC 24
Peak memory 262616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762320207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.762320207
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2804579368
Short name T273
Test name
Test status
Simulation time 126548560 ps
CPU time 16.47 seconds
Started Sep 01 06:33:43 PM UTC 24
Finished Sep 01 06:34:01 PM UTC 24
Peak memory 252636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804579368 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_
rw_with_rand_reset.2804579368
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.413223469
Short name T247
Test name
Test status
Simulation time 469945516 ps
CPU time 16.4 seconds
Started Sep 01 06:33:14 PM UTC 24
Finished Sep 01 06:33:32 PM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413223469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.413223469
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.3433057259
Short name T274
Test name
Test status
Simulation time 11999025 ps
CPU time 2.64 seconds
Started Sep 01 06:33:10 PM UTC 24
Finished Sep 01 06:33:14 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433057259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3433057259
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1821416198
Short name T236
Test name
Test status
Simulation time 1022039836 ps
CPU time 31.49 seconds
Started Sep 01 06:33:33 PM UTC 24
Finished Sep 01 06:34:07 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821416198 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.1821416198
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1783706746
Short name T169
Test name
Test status
Simulation time 797623461 ps
CPU time 134.94 seconds
Started Sep 01 06:32:26 PM UTC 24
Finished Sep 01 06:34:43 PM UTC 24
Peak memory 279332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783706746 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.1783706746
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.677712005
Short name T716
Test name
Test status
Simulation time 851264562 ps
CPU time 21.42 seconds
Started Sep 01 06:32:41 PM UTC 24
Finished Sep 01 06:33:04 PM UTC 24
Peak memory 262756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677712005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.677712005
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2415847947
Short name T206
Test name
Test status
Simulation time 60455760 ps
CPU time 3.85 seconds
Started Sep 01 06:33:04 PM UTC 24
Finished Sep 01 06:33:09 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415847947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2415847947
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.270470185
Short name T790
Test name
Test status
Simulation time 18182700 ps
CPU time 2.16 seconds
Started Sep 01 06:46:43 PM UTC 24
Finished Sep 01 06:46:46 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270470185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.270470185
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2315278200
Short name T789
Test name
Test status
Simulation time 10159020 ps
CPU time 2 seconds
Started Sep 01 06:46:43 PM UTC 24
Finished Sep 01 06:46:46 PM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315278200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2315278200
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.3874250873
Short name T791
Test name
Test status
Simulation time 9759848 ps
CPU time 2.51 seconds
Started Sep 01 06:46:43 PM UTC 24
Finished Sep 01 06:46:46 PM UTC 24
Peak memory 250540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874250873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3874250873
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.4203726825
Short name T794
Test name
Test status
Simulation time 7386888 ps
CPU time 2.24 seconds
Started Sep 01 06:46:47 PM UTC 24
Finished Sep 01 06:46:50 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203726825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.4203726825
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.3395506459
Short name T793
Test name
Test status
Simulation time 7264143 ps
CPU time 2.04 seconds
Started Sep 01 06:46:47 PM UTC 24
Finished Sep 01 06:46:50 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395506459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3395506459
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.1552357269
Short name T795
Test name
Test status
Simulation time 10682646 ps
CPU time 2.41 seconds
Started Sep 01 06:46:47 PM UTC 24
Finished Sep 01 06:46:50 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552357269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1552357269
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.3436226308
Short name T797
Test name
Test status
Simulation time 12442738 ps
CPU time 2.58 seconds
Started Sep 01 06:46:50 PM UTC 24
Finished Sep 01 06:46:54 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436226308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3436226308
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.2160617146
Short name T799
Test name
Test status
Simulation time 11032603 ps
CPU time 2 seconds
Started Sep 01 06:46:54 PM UTC 24
Finished Sep 01 06:46:57 PM UTC 24
Peak memory 248780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160617146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2160617146
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.3400183660
Short name T802
Test name
Test status
Simulation time 9220470 ps
CPU time 2.5 seconds
Started Sep 01 06:46:54 PM UTC 24
Finished Sep 01 06:46:57 PM UTC 24
Peak memory 250348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400183660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3400183660
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2108746138
Short name T800
Test name
Test status
Simulation time 19391365 ps
CPU time 2.22 seconds
Started Sep 01 06:46:54 PM UTC 24
Finished Sep 01 06:46:57 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108746138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2108746138
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2166578576
Short name T722
Test name
Test status
Simulation time 15208501317 ps
CPU time 186.72 seconds
Started Sep 01 06:34:14 PM UTC 24
Finished Sep 01 06:37:24 PM UTC 24
Peak memory 252708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166578576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2166578576
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2918132987
Short name T766
Test name
Test status
Simulation time 14814771455 ps
CPU time 593.92 seconds
Started Sep 01 06:34:10 PM UTC 24
Finished Sep 01 06:44:12 PM UTC 24
Peak memory 250456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918132987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2918132987
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.6488735
Short name T237
Test name
Test status
Simulation time 148287182 ps
CPU time 6.33 seconds
Started Sep 01 06:34:08 PM UTC 24
Finished Sep 01 06:34:15 PM UTC 24
Peak memory 262808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6488735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +U
VM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.6488735
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2258449078
Short name T415
Test name
Test status
Simulation time 76364296 ps
CPU time 9.47 seconds
Started Sep 01 06:34:18 PM UTC 24
Finished Sep 01 06:34:29 PM UTC 24
Peak memory 264792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258449078 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_
rw_with_rand_reset.2258449078
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.2634869211
Short name T417
Test name
Test status
Simulation time 121257947 ps
CPU time 8.65 seconds
Started Sep 01 06:34:08 PM UTC 24
Finished Sep 01 06:34:18 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634869211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2634869211
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.3380836351
Short name T266
Test name
Test status
Simulation time 6346674 ps
CPU time 2.24 seconds
Started Sep 01 06:34:04 PM UTC 24
Finished Sep 01 06:34:07 PM UTC 24
Peak memory 250540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380836351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3380836351
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2134372224
Short name T238
Test name
Test status
Simulation time 891556375 ps
CPU time 36.67 seconds
Started Sep 01 06:34:16 PM UTC 24
Finished Sep 01 06:34:54 PM UTC 24
Peak memory 262680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134372224 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.2134372224
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1218129202
Short name T180
Test name
Test status
Simulation time 22420193887 ps
CPU time 570.83 seconds
Started Sep 01 06:34:00 PM UTC 24
Finished Sep 01 06:43:38 PM UTC 24
Peak memory 279596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218129202 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.1218129202
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2559553640
Short name T194
Test name
Test status
Simulation time 17157502350 ps
CPU time 802.61 seconds
Started Sep 01 06:34:00 PM UTC 24
Finished Sep 01 06:47:33 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559553640 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado
w_reg_errors_with_csr_rw.2559553640
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.795519896
Short name T717
Test name
Test status
Simulation time 121413677 ps
CPU time 9.36 seconds
Started Sep 01 06:34:02 PM UTC 24
Finished Sep 01 06:34:13 PM UTC 24
Peak memory 264876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795519896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.795519896
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.2360698987
Short name T801
Test name
Test status
Simulation time 31264309 ps
CPU time 2.27 seconds
Started Sep 01 06:46:54 PM UTC 24
Finished Sep 01 06:46:57 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360698987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2360698987
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.1666157151
Short name T803
Test name
Test status
Simulation time 9921852 ps
CPU time 2.17 seconds
Started Sep 01 06:46:55 PM UTC 24
Finished Sep 01 06:46:58 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666157151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1666157151
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1040804179
Short name T804
Test name
Test status
Simulation time 16568910 ps
CPU time 2.17 seconds
Started Sep 01 06:46:55 PM UTC 24
Finished Sep 01 06:46:58 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040804179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1040804179
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3855589318
Short name T805
Test name
Test status
Simulation time 13855578 ps
CPU time 2.7 seconds
Started Sep 01 06:46:55 PM UTC 24
Finished Sep 01 06:46:59 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855589318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3855589318
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3580362299
Short name T806
Test name
Test status
Simulation time 9057720 ps
CPU time 2.38 seconds
Started Sep 01 06:46:57 PM UTC 24
Finished Sep 01 06:47:00 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580362299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3580362299
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.863508357
Short name T809
Test name
Test status
Simulation time 8747856 ps
CPU time 2.41 seconds
Started Sep 01 06:46:58 PM UTC 24
Finished Sep 01 06:47:02 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863508357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.863508357
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1022370030
Short name T807
Test name
Test status
Simulation time 14606548 ps
CPU time 2.07 seconds
Started Sep 01 06:46:58 PM UTC 24
Finished Sep 01 06:47:01 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022370030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1022370030
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.2080680499
Short name T810
Test name
Test status
Simulation time 11295338 ps
CPU time 2.5 seconds
Started Sep 01 06:46:58 PM UTC 24
Finished Sep 01 06:47:02 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080680499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2080680499
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.161612065
Short name T808
Test name
Test status
Simulation time 8271290 ps
CPU time 2.12 seconds
Started Sep 01 06:46:58 PM UTC 24
Finished Sep 01 06:47:02 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161612065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.161612065
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.2552850122
Short name T811
Test name
Test status
Simulation time 8029484 ps
CPU time 2.42 seconds
Started Sep 01 06:46:58 PM UTC 24
Finished Sep 01 06:47:02 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552850122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2552850122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3986057767
Short name T727
Test name
Test status
Simulation time 1744796764 ps
CPU time 173.76 seconds
Started Sep 01 06:35:20 PM UTC 24
Finished Sep 01 06:38:17 PM UTC 24
Peak memory 250468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986057767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3986057767
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4227987342
Short name T760
Test name
Test status
Simulation time 5962423369 ps
CPU time 506.13 seconds
Started Sep 01 06:35:19 PM UTC 24
Finished Sep 01 06:43:52 PM UTC 24
Peak memory 252508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227987342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.4227987342
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.176816061
Short name T719
Test name
Test status
Simulation time 108465020 ps
CPU time 8.35 seconds
Started Sep 01 06:35:10 PM UTC 24
Finished Sep 01 06:35:20 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176816061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.176816061
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2463930651
Short name T418
Test name
Test status
Simulation time 412099814 ps
CPU time 13.32 seconds
Started Sep 01 06:35:27 PM UTC 24
Finished Sep 01 06:35:42 PM UTC 24
Peak memory 250588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463930651 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_
rw_with_rand_reset.2463930651
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.2534846529
Short name T239
Test name
Test status
Simulation time 68631488 ps
CPU time 6.25 seconds
Started Sep 01 06:35:13 PM UTC 24
Finished Sep 01 06:35:20 PM UTC 24
Peak memory 250528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534846529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2534846529
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.3116839178
Short name T409
Test name
Test status
Simulation time 7910450 ps
CPU time 2.15 seconds
Started Sep 01 06:35:09 PM UTC 24
Finished Sep 01 06:35:12 PM UTC 24
Peak memory 250340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116839178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3116839178
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2239802638
Short name T243
Test name
Test status
Simulation time 1031289966 ps
CPU time 40.59 seconds
Started Sep 01 06:35:21 PM UTC 24
Finished Sep 01 06:36:04 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239802638 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.2239802638
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.665586829
Short name T192
Test name
Test status
Simulation time 9212733663 ps
CPU time 882.19 seconds
Started Sep 01 06:34:29 PM UTC 24
Finished Sep 01 06:49:23 PM UTC 24
Peak memory 285804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665586829 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow
_reg_errors_with_csr_rw.665586829
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.3173849052
Short name T718
Test name
Test status
Simulation time 353551931 ps
CPU time 21.85 seconds
Started Sep 01 06:34:45 PM UTC 24
Finished Sep 01 06:35:08 PM UTC 24
Peak memory 262756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173849052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3173849052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.3001995064
Short name T813
Test name
Test status
Simulation time 15554151 ps
CPU time 2.37 seconds
Started Sep 01 06:47:00 PM UTC 24
Finished Sep 01 06:47:04 PM UTC 24
Peak memory 250408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001995064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3001995064
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.4072645522
Short name T814
Test name
Test status
Simulation time 58514788 ps
CPU time 2.32 seconds
Started Sep 01 06:47:00 PM UTC 24
Finished Sep 01 06:47:04 PM UTC 24
Peak memory 250332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072645522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.4072645522
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2664209728
Short name T812
Test name
Test status
Simulation time 14454677 ps
CPU time 2.1 seconds
Started Sep 01 06:47:00 PM UTC 24
Finished Sep 01 06:47:03 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664209728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2664209728
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.1097758583
Short name T815
Test name
Test status
Simulation time 18503956 ps
CPU time 2.08 seconds
Started Sep 01 06:47:00 PM UTC 24
Finished Sep 01 06:47:04 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097758583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1097758583
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.2285032132
Short name T817
Test name
Test status
Simulation time 8035406 ps
CPU time 2.33 seconds
Started Sep 01 06:47:02 PM UTC 24
Finished Sep 01 06:47:06 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285032132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2285032132
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2399633696
Short name T816
Test name
Test status
Simulation time 13216553 ps
CPU time 1.55 seconds
Started Sep 01 06:47:02 PM UTC 24
Finished Sep 01 06:47:05 PM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399633696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2399633696
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.1630462454
Short name T821
Test name
Test status
Simulation time 7428798 ps
CPU time 2.32 seconds
Started Sep 01 06:47:03 PM UTC 24
Finished Sep 01 06:47:07 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630462454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1630462454
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.2433172987
Short name T818
Test name
Test status
Simulation time 9705049 ps
CPU time 2.01 seconds
Started Sep 01 06:47:03 PM UTC 24
Finished Sep 01 06:47:07 PM UTC 24
Peak memory 248752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433172987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2433172987
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.1376202314
Short name T820
Test name
Test status
Simulation time 15219227 ps
CPU time 2.05 seconds
Started Sep 01 06:47:03 PM UTC 24
Finished Sep 01 06:47:07 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376202314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1376202314
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.1266182520
Short name T819
Test name
Test status
Simulation time 7639078 ps
CPU time 2.08 seconds
Started Sep 01 06:47:03 PM UTC 24
Finished Sep 01 06:47:07 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266182520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1266182520
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1472695400
Short name T423
Test name
Test status
Simulation time 1048598612 ps
CPU time 13.26 seconds
Started Sep 01 06:36:48 PM UTC 24
Finished Sep 01 06:37:02 PM UTC 24
Peak memory 264860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472695400 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_
rw_with_rand_reset.1472695400
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.3400672377
Short name T244
Test name
Test status
Simulation time 41541756 ps
CPU time 5.54 seconds
Started Sep 01 06:36:40 PM UTC 24
Finished Sep 01 06:36:47 PM UTC 24
Peak memory 250464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400672377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3400672377
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.4031250399
Short name T413
Test name
Test status
Simulation time 7301685 ps
CPU time 2.41 seconds
Started Sep 01 06:36:36 PM UTC 24
Finished Sep 01 06:36:40 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031250399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4031250399
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.645274430
Short name T721
Test name
Test status
Simulation time 180382904 ps
CPU time 34.58 seconds
Started Sep 01 06:36:41 PM UTC 24
Finished Sep 01 06:37:17 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645274430 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.645274430
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1680522142
Short name T181
Test name
Test status
Simulation time 27969775888 ps
CPU time 600.06 seconds
Started Sep 01 06:35:43 PM UTC 24
Finished Sep 01 06:45:51 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680522142 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shado
w_reg_errors_with_csr_rw.1680522142
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.1133025872
Short name T720
Test name
Test status
Simulation time 1390299816 ps
CPU time 24.14 seconds
Started Sep 01 06:36:05 PM UTC 24
Finished Sep 01 06:36:30 PM UTC 24
Peak memory 266848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133025872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1133025872
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1811492049
Short name T725
Test name
Test status
Simulation time 157262627 ps
CPU time 19.46 seconds
Started Sep 01 06:37:41 PM UTC 24
Finished Sep 01 06:38:01 PM UTC 24
Peak memory 264792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811492049 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_
rw_with_rand_reset.1811492049
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.214816933
Short name T723
Test name
Test status
Simulation time 63049757 ps
CPU time 5.73 seconds
Started Sep 01 06:37:30 PM UTC 24
Finished Sep 01 06:37:38 PM UTC 24
Peak memory 252448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214816933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.214816933
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.2292279937
Short name T410
Test name
Test status
Simulation time 8111333 ps
CPU time 2.26 seconds
Started Sep 01 06:37:25 PM UTC 24
Finished Sep 01 06:37:29 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292279937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2292279937
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.361592924
Short name T728
Test name
Test status
Simulation time 353845784 ps
CPU time 40.62 seconds
Started Sep 01 06:37:39 PM UTC 24
Finished Sep 01 06:38:21 PM UTC 24
Peak memory 260768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361592924 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.361592924
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2741424661
Short name T172
Test name
Test status
Simulation time 4246627269 ps
CPU time 312.19 seconds
Started Sep 01 06:37:03 PM UTC 24
Finished Sep 01 06:42:20 PM UTC 24
Peak memory 279532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741424661 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.2741424661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1095684488
Short name T183
Test name
Test status
Simulation time 2106002429 ps
CPU time 295.94 seconds
Started Sep 01 06:37:03 PM UTC 24
Finished Sep 01 06:42:03 PM UTC 24
Peak memory 279324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095684488 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shado
w_reg_errors_with_csr_rw.1095684488
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.2705618193
Short name T724
Test name
Test status
Simulation time 825434159 ps
CPU time 21.43 seconds
Started Sep 01 06:37:17 PM UTC 24
Finished Sep 01 06:37:40 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705618193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2705618193
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.136731731
Short name T730
Test name
Test status
Simulation time 154776015 ps
CPU time 20.21 seconds
Started Sep 01 06:38:23 PM UTC 24
Finished Sep 01 06:38:44 PM UTC 24
Peak memory 264932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136731731 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_r
w_with_rand_reset.136731731
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.169873271
Short name T729
Test name
Test status
Simulation time 20449400 ps
CPU time 5.87 seconds
Started Sep 01 06:38:22 PM UTC 24
Finished Sep 01 06:38:29 PM UTC 24
Peak memory 250400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169873271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.169873271
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.3785725211
Short name T412
Test name
Test status
Simulation time 17065252 ps
CPU time 2.2 seconds
Started Sep 01 06:38:18 PM UTC 24
Finished Sep 01 06:38:21 PM UTC 24
Peak memory 250340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785725211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3785725211
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.308100109
Short name T731
Test name
Test status
Simulation time 1083793625 ps
CPU time 34.27 seconds
Started Sep 01 06:38:22 PM UTC 24
Finished Sep 01 06:38:58 PM UTC 24
Peak memory 260548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308100109 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.308100109
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2458203411
Short name T178
Test name
Test status
Simulation time 5496697142 ps
CPU time 523.51 seconds
Started Sep 01 06:38:02 PM UTC 24
Finished Sep 01 06:46:53 PM UTC 24
Peak memory 279596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458203411 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.2458203411
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3846226368
Short name T198
Test name
Test status
Simulation time 16851128438 ps
CPU time 1402.92 seconds
Started Sep 01 06:37:44 PM UTC 24
Finished Sep 01 07:01:25 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846226368 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado
w_reg_errors_with_csr_rw.3846226368
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.3628094613
Short name T726
Test name
Test status
Simulation time 45318729 ps
CPU time 6.54 seconds
Started Sep 01 06:38:09 PM UTC 24
Finished Sep 01 06:38:17 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628094613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3628094613
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4088167922
Short name T734
Test name
Test status
Simulation time 70488632 ps
CPU time 9.75 seconds
Started Sep 01 06:39:12 PM UTC 24
Finished Sep 01 06:39:22 PM UTC 24
Peak memory 268960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088167922 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_
rw_with_rand_reset.4088167922
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.442110969
Short name T733
Test name
Test status
Simulation time 64210072 ps
CPU time 5.42 seconds
Started Sep 01 06:39:04 PM UTC 24
Finished Sep 01 06:39:11 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442110969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.442110969
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3955348154
Short name T735
Test name
Test status
Simulation time 346767518 ps
CPU time 30.43 seconds
Started Sep 01 06:39:10 PM UTC 24
Finished Sep 01 06:39:42 PM UTC 24
Peak memory 262680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955348154 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.3955348154
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2954348482
Short name T174
Test name
Test status
Simulation time 16724760403 ps
CPU time 407.8 seconds
Started Sep 01 06:38:30 PM UTC 24
Finished Sep 01 06:45:24 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954348482 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.2954348482
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3383384538
Short name T187
Test name
Test status
Simulation time 8810651211 ps
CPU time 839.6 seconds
Started Sep 01 06:38:24 PM UTC 24
Finished Sep 01 06:52:34 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383384538 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shado
w_reg_errors_with_csr_rw.3383384538
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.2813429275
Short name T732
Test name
Test status
Simulation time 321619125 ps
CPU time 22.94 seconds
Started Sep 01 06:38:45 PM UTC 24
Finished Sep 01 06:39:09 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813429275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2813429275
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3748767914
Short name T738
Test name
Test status
Simulation time 480816174 ps
CPU time 17.91 seconds
Started Sep 01 06:39:55 PM UTC 24
Finished Sep 01 06:40:14 PM UTC 24
Peak memory 252500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748767914 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_
rw_with_rand_reset.3748767914
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.2956023416
Short name T736
Test name
Test status
Simulation time 261508456 ps
CPU time 7.58 seconds
Started Sep 01 06:39:52 PM UTC 24
Finished Sep 01 06:40:00 PM UTC 24
Peak memory 250464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956023416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2956023416
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.3589650762
Short name T414
Test name
Test status
Simulation time 19386442 ps
CPU time 2.11 seconds
Started Sep 01 06:39:50 PM UTC 24
Finished Sep 01 06:39:54 PM UTC 24
Peak memory 250332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589650762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3589650762
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1130906010
Short name T745
Test name
Test status
Simulation time 1331613162 ps
CPU time 73.74 seconds
Started Sep 01 06:39:52 PM UTC 24
Finished Sep 01 06:41:07 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130906010 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.1130906010
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2078694831
Short name T177
Test name
Test status
Simulation time 2779644191 ps
CPU time 243.61 seconds
Started Sep 01 06:39:29 PM UTC 24
Finished Sep 01 06:43:37 PM UTC 24
Peak memory 281572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078694831 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.2078694831
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.2584042286
Short name T737
Test name
Test status
Simulation time 1330951942 ps
CPU time 27.08 seconds
Started Sep 01 06:39:44 PM UTC 24
Finished Sep 01 06:40:13 PM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584042286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2584042286
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.339644116
Short name T96
Test name
Test status
Simulation time 3482327535 ps
CPU time 81.07 seconds
Started Sep 01 04:55:29 PM UTC 24
Finished Sep 01 04:56:52 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339644116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.339644116
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.2543935855
Short name T331
Test name
Test status
Simulation time 17156380643 ps
CPU time 1021.88 seconds
Started Sep 01 04:55:38 PM UTC 24
Finished Sep 01 05:12:53 PM UTC 24
Peak memory 282080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543935855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2543935855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.3400638598
Short name T474
Test name
Test status
Simulation time 26804042198 ps
CPU time 1894.26 seconds
Started Sep 01 04:55:42 PM UTC 24
Finished Sep 01 05:27:40 PM UTC 24
Peak memory 288220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400638598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3400638598
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.3315836878
Short name T9
Test name
Test status
Simulation time 2032628802 ps
CPU time 32.9 seconds
Started Sep 01 04:55:28 PM UTC 24
Finished Sep 01 04:56:02 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315836878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3315836878
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.3921320905
Short name T150
Test name
Test status
Simulation time 147180544182 ps
CPU time 1404.46 seconds
Started Sep 01 04:55:45 PM UTC 24
Finished Sep 01 05:19:27 PM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921320905 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.3921320905
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.897158782
Short name T513
Test name
Test status
Simulation time 91920999092 ps
CPU time 2914.38 seconds
Started Sep 01 04:55:58 PM UTC 24
Finished Sep 01 05:45:05 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897158782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.897158782
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.3033966385
Short name T6
Test name
Test status
Simulation time 732025332 ps
CPU time 24.58 seconds
Started Sep 01 04:56:00 PM UTC 24
Finished Sep 01 04:56:26 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033966385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3033966385
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.3003150070
Short name T14
Test name
Test status
Simulation time 351538874 ps
CPU time 15.32 seconds
Started Sep 01 04:55:56 PM UTC 24
Finished Sep 01 04:56:12 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003150070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3003150070
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.2661844265
Short name T30
Test name
Test status
Simulation time 7246357736 ps
CPU time 431.91 seconds
Started Sep 01 04:55:59 PM UTC 24
Finished Sep 01 05:03:17 PM UTC 24
Peak memory 263300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661844265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2661844265
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.3498511336
Short name T11
Test name
Test status
Simulation time 844433960 ps
CPU time 14.38 seconds
Started Sep 01 04:55:56 PM UTC 24
Finished Sep 01 04:56:11 PM UTC 24
Peak memory 263268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498511336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3498511336
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.170719539
Short name T110
Test name
Test status
Simulation time 2647167159 ps
CPU time 47.5 seconds
Started Sep 01 04:55:56 PM UTC 24
Finished Sep 01 04:56:45 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170719539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.170719539
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.1681620764
Short name T75
Test name
Test status
Simulation time 32871793340 ps
CPU time 2278.61 seconds
Started Sep 01 05:01:52 PM UTC 24
Finished Sep 01 05:40:19 PM UTC 24
Peak memory 287228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681620764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1681620764
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.599238828
Short name T428
Test name
Test status
Simulation time 351941061 ps
CPU time 13.71 seconds
Started Sep 01 05:02:30 PM UTC 24
Finished Sep 01 05:02:45 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599238828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.599238828
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.1777078793
Short name T302
Test name
Test status
Simulation time 7950995394 ps
CPU time 54.97 seconds
Started Sep 01 05:01:38 PM UTC 24
Finished Sep 01 05:02:35 PM UTC 24
Peak memory 269176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777078793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1777078793
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.715691057
Short name T104
Test name
Test status
Simulation time 4596613699 ps
CPU time 107.22 seconds
Started Sep 01 05:01:23 PM UTC 24
Finished Sep 01 05:03:12 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715691057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.715691057
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.3930507213
Short name T300
Test name
Test status
Simulation time 18928019002 ps
CPU time 993.17 seconds
Started Sep 01 05:02:06 PM UTC 24
Finished Sep 01 05:18:53 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930507213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3930507213
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.1315005086
Short name T61
Test name
Test status
Simulation time 4525860854 ps
CPU time 99.44 seconds
Started Sep 01 05:01:20 PM UTC 24
Finished Sep 01 05:03:01 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315005086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1315005086
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.2652607397
Short name T93
Test name
Test status
Simulation time 1564211752 ps
CPU time 80.3 seconds
Started Sep 01 05:01:21 PM UTC 24
Finished Sep 01 05:02:43 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652607397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2652607397
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.3181470643
Short name T111
Test name
Test status
Simulation time 389089698 ps
CPU time 43.47 seconds
Started Sep 01 05:01:44 PM UTC 24
Finished Sep 01 05:02:29 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181470643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3181470643
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.2379632527
Short name T427
Test name
Test status
Simulation time 930430334 ps
CPU time 40.74 seconds
Started Sep 01 05:01:19 PM UTC 24
Finished Sep 01 05:02:02 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379632527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2379632527
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.1325061916
Short name T36
Test name
Test status
Simulation time 2620380570 ps
CPU time 203.63 seconds
Started Sep 01 05:02:31 PM UTC 24
Finished Sep 01 05:05:58 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325061916 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.1325061916
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all_with_rand_reset.3613970713
Short name T117
Test name
Test status
Simulation time 5495184767 ps
CPU time 750.82 seconds
Started Sep 01 05:02:42 PM UTC 24
Finished Sep 01 05:15:24 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3613970713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.a
lert_handler_stress_all_with_rand_reset.3613970713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.175810475
Short name T229
Test name
Test status
Simulation time 15413200 ps
CPU time 4.33 seconds
Started Sep 01 05:03:17 PM UTC 24
Finished Sep 01 05:03:22 PM UTC 24
Peak memory 263168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175810475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.175810475
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.3837461562
Short name T389
Test name
Test status
Simulation time 81022038211 ps
CPU time 1194.06 seconds
Started Sep 01 05:03:03 PM UTC 24
Finished Sep 01 05:23:10 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837461562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3837461562
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.1211546732
Short name T261
Test name
Test status
Simulation time 1253166968 ps
CPU time 84.92 seconds
Started Sep 01 05:03:14 PM UTC 24
Finished Sep 01 05:04:41 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211546732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1211546732
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.1617238578
Short name T437
Test name
Test status
Simulation time 1446931630 ps
CPU time 200.66 seconds
Started Sep 01 05:02:47 PM UTC 24
Finished Sep 01 05:06:11 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617238578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1617238578
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.4198764178
Short name T430
Test name
Test status
Simulation time 346501946 ps
CPU time 26.38 seconds
Started Sep 01 05:02:46 PM UTC 24
Finished Sep 01 05:03:13 PM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198764178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.4198764178
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.3662085810
Short name T502
Test name
Test status
Simulation time 115305555672 ps
CPU time 2340.89 seconds
Started Sep 01 05:03:14 PM UTC 24
Finished Sep 01 05:42:43 PM UTC 24
Peak memory 299844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662085810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3662085810
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.2149602027
Short name T267
Test name
Test status
Simulation time 4343763089 ps
CPU time 250.59 seconds
Started Sep 01 05:03:06 PM UTC 24
Finished Sep 01 05:07:20 PM UTC 24
Peak memory 269320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149602027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2149602027
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.4186637623
Short name T431
Test name
Test status
Simulation time 2194104729 ps
CPU time 92.84 seconds
Started Sep 01 05:02:44 PM UTC 24
Finished Sep 01 05:04:19 PM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186637623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4186637623
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.3976900467
Short name T94
Test name
Test status
Simulation time 1598768478 ps
CPU time 70 seconds
Started Sep 01 05:02:44 PM UTC 24
Finished Sep 01 05:03:55 PM UTC 24
Peak memory 269340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976900467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3976900467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.3819042375
Short name T112
Test name
Test status
Simulation time 543425751 ps
CPU time 27.56 seconds
Started Sep 01 05:03:01 PM UTC 24
Finished Sep 01 05:03:30 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819042375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3819042375
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.3748741633
Short name T230
Test name
Test status
Simulation time 6416541388 ps
CPU time 64.67 seconds
Started Sep 01 05:02:44 PM UTC 24
Finished Sep 01 05:03:50 PM UTC 24
Peak memory 263296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748741633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3748741633
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.3617545501
Short name T309
Test name
Test status
Simulation time 897857960442 ps
CPU time 3830.24 seconds
Started Sep 01 05:03:16 PM UTC 24
Finished Sep 01 06:07:49 PM UTC 24
Peak memory 321056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617545501 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.3617545501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all_with_rand_reset.264226719
Short name T64
Test name
Test status
Simulation time 19044709597 ps
CPU time 725.06 seconds
Started Sep 01 05:03:18 PM UTC 24
Finished Sep 01 05:15:33 PM UTC 24
Peak memory 285628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=264226719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.al
ert_handler_stress_all_with_rand_reset.264226719
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.2985181726
Short name T357
Test name
Test status
Simulation time 18462102142 ps
CPU time 1888.99 seconds
Started Sep 01 05:03:52 PM UTC 24
Finished Sep 01 05:35:45 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985181726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2985181726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.1711061689
Short name T262
Test name
Test status
Simulation time 628027651 ps
CPU time 32.07 seconds
Started Sep 01 05:04:20 PM UTC 24
Finished Sep 01 05:04:54 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711061689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1711061689
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.3442416605
Short name T440
Test name
Test status
Simulation time 10661502579 ps
CPU time 200.98 seconds
Started Sep 01 05:03:49 PM UTC 24
Finished Sep 01 05:07:14 PM UTC 24
Peak memory 269104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442416605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3442416605
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.1454884364
Short name T232
Test name
Test status
Simulation time 976158389 ps
CPU time 35.91 seconds
Started Sep 01 05:03:32 PM UTC 24
Finished Sep 01 05:04:09 PM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454884364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1454884364
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.618849170
Short name T404
Test name
Test status
Simulation time 131364069969 ps
CPU time 1514.23 seconds
Started Sep 01 05:04:15 PM UTC 24
Finished Sep 01 05:29:48 PM UTC 24
Peak memory 299848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618849170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.618849170
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.213448678
Short name T38
Test name
Test status
Simulation time 5504211935 ps
CPU time 110.33 seconds
Started Sep 01 05:03:23 PM UTC 24
Finished Sep 01 05:05:16 PM UTC 24
Peak memory 263164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213448678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.213448678
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.739262150
Short name T133
Test name
Test status
Simulation time 2576948350 ps
CPU time 43.7 seconds
Started Sep 01 05:03:29 PM UTC 24
Finished Sep 01 05:04:14 PM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739262150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.739262150
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.1019705223
Short name T231
Test name
Test status
Simulation time 380042649 ps
CPU time 29.36 seconds
Started Sep 01 05:03:20 PM UTC 24
Finished Sep 01 05:03:51 PM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019705223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1019705223
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all_with_rand_reset.3787949726
Short name T31
Test name
Test status
Simulation time 3928250589 ps
CPU time 174.64 seconds
Started Sep 01 05:04:33 PM UTC 24
Finished Sep 01 05:07:31 PM UTC 24
Peak memory 283644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3787949726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.a
lert_handler_stress_all_with_rand_reset.3787949726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.570144069
Short name T253
Test name
Test status
Simulation time 53784513 ps
CPU time 6.53 seconds
Started Sep 01 05:05:30 PM UTC 24
Finished Sep 01 05:05:38 PM UTC 24
Peak memory 263244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570144069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.570144069
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.3490469758
Short name T436
Test name
Test status
Simulation time 407387927 ps
CPU time 31.38 seconds
Started Sep 01 05:05:25 PM UTC 24
Finished Sep 01 05:05:58 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490469758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3490469758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.2090174019
Short name T433
Test name
Test status
Simulation time 505730381 ps
CPU time 27.72 seconds
Started Sep 01 05:04:58 PM UTC 24
Finished Sep 01 05:05:27 PM UTC 24
Peak memory 269368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090174019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2090174019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.233186670
Short name T264
Test name
Test status
Simulation time 200771575 ps
CPU time 13.42 seconds
Started Sep 01 05:04:54 PM UTC 24
Finished Sep 01 05:05:09 PM UTC 24
Peak memory 267000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233186670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.233186670
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.3235076125
Short name T285
Test name
Test status
Simulation time 14648256891 ps
CPU time 343.93 seconds
Started Sep 01 05:05:10 PM UTC 24
Finished Sep 01 05:10:58 PM UTC 24
Peak memory 269512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235076125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3235076125
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.2475557874
Short name T265
Test name
Test status
Simulation time 445503778 ps
CPU time 35.13 seconds
Started Sep 01 05:04:45 PM UTC 24
Finished Sep 01 05:05:21 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475557874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2475557874
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.163195172
Short name T146
Test name
Test status
Simulation time 223878688 ps
CPU time 10.89 seconds
Started Sep 01 05:04:46 PM UTC 24
Finished Sep 01 05:04:58 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163195172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.163195172
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.1805743492
Short name T148
Test name
Test status
Simulation time 259874028 ps
CPU time 28.75 seconds
Started Sep 01 05:04:59 PM UTC 24
Finished Sep 01 05:05:29 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805743492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1805743492
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.3892750955
Short name T432
Test name
Test status
Simulation time 1648039014 ps
CPU time 40.75 seconds
Started Sep 01 05:04:42 PM UTC 24
Finished Sep 01 05:05:25 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892750955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3892750955
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.1482862544
Short name T576
Test name
Test status
Simulation time 58379071057 ps
CPU time 3618.56 seconds
Started Sep 01 05:05:28 PM UTC 24
Finished Sep 01 06:06:28 PM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482862544 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.1482862544
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.3959471911
Short name T254
Test name
Test status
Simulation time 50115380 ps
CPU time 4 seconds
Started Sep 01 05:07:21 PM UTC 24
Finished Sep 01 05:07:26 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959471911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3959471911
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.3490474147
Short name T407
Test name
Test status
Simulation time 41227539036 ps
CPU time 2121.47 seconds
Started Sep 01 05:06:12 PM UTC 24
Finished Sep 01 05:42:02 PM UTC 24
Peak memory 301880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490474147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3490474147
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.4248052723
Short name T435
Test name
Test status
Simulation time 7589531114 ps
CPU time 38.48 seconds
Started Sep 01 05:07:06 PM UTC 24
Finished Sep 01 05:07:46 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248052723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.4248052723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.2614552049
Short name T78
Test name
Test status
Simulation time 5422319558 ps
CPU time 184.31 seconds
Started Sep 01 05:05:59 PM UTC 24
Finished Sep 01 05:09:06 PM UTC 24
Peak memory 269104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614552049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2614552049
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.3219293318
Short name T439
Test name
Test status
Simulation time 134862153 ps
CPU time 12.45 seconds
Started Sep 01 05:05:59 PM UTC 24
Finished Sep 01 05:06:13 PM UTC 24
Peak memory 262920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219293318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3219293318
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.3347982519
Short name T381
Test name
Test status
Simulation time 30206460269 ps
CPU time 2412.9 seconds
Started Sep 01 05:06:14 PM UTC 24
Finished Sep 01 05:46:56 PM UTC 24
Peak memory 299836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347982519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3347982519
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.3491354510
Short name T529
Test name
Test status
Simulation time 55891540606 ps
CPU time 2658.57 seconds
Started Sep 01 05:06:38 PM UTC 24
Finished Sep 01 05:51:25 PM UTC 24
Peak memory 298464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491354510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3491354510
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.129696505
Short name T85
Test name
Test status
Simulation time 4498865689 ps
CPU time 269.14 seconds
Started Sep 01 05:06:12 PM UTC 24
Finished Sep 01 05:10:46 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129696505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.129696505
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.3998550939
Short name T438
Test name
Test status
Simulation time 2652139687 ps
CPU time 18.49 seconds
Started Sep 01 05:05:52 PM UTC 24
Finished Sep 01 05:06:12 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998550939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3998550939
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.1954965294
Short name T147
Test name
Test status
Simulation time 3089125016 ps
CPU time 67.07 seconds
Started Sep 01 05:05:56 PM UTC 24
Finished Sep 01 05:07:05 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954965294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1954965294
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.1447656631
Short name T113
Test name
Test status
Simulation time 1240112682 ps
CPU time 35.97 seconds
Started Sep 01 05:05:59 PM UTC 24
Finished Sep 01 05:06:36 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447656631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1447656631
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.3686407594
Short name T434
Test name
Test status
Simulation time 89166794 ps
CPU time 11.43 seconds
Started Sep 01 05:05:39 PM UTC 24
Finished Sep 01 05:05:51 PM UTC 24
Peak memory 265024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686407594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3686407594
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.4226911297
Short name T317
Test name
Test status
Simulation time 253397607137 ps
CPU time 3163.16 seconds
Started Sep 01 05:07:14 PM UTC 24
Finished Sep 01 06:00:34 PM UTC 24
Peak memory 304672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226911297 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.4226911297
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/14.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.2233046
Short name T80
Test name
Test status
Simulation time 442948352 ps
CPU time 4.74 seconds
Started Sep 01 05:09:08 PM UTC 24
Finished Sep 01 05:09:13 PM UTC 24
Peak memory 263164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_ha
ndler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2233046
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.506196271
Short name T82
Test name
Test status
Simulation time 4548343884 ps
CPU time 68.75 seconds
Started Sep 01 05:08:52 PM UTC 24
Finished Sep 01 05:10:02 PM UTC 24
Peak memory 263296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506196271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.506196271
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.3055843301
Short name T83
Test name
Test status
Simulation time 5503385081 ps
CPU time 163.66 seconds
Started Sep 01 05:07:51 PM UTC 24
Finished Sep 01 05:10:38 PM UTC 24
Peak memory 269432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055843301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3055843301
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.4152354028
Short name T79
Test name
Test status
Simulation time 3220699666 ps
CPU time 80.59 seconds
Started Sep 01 05:07:46 PM UTC 24
Finished Sep 01 05:09:09 PM UTC 24
Peak memory 262996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152354028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.4152354028
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.2023207186
Short name T390
Test name
Test status
Simulation time 185130196607 ps
CPU time 3371.88 seconds
Started Sep 01 05:08:37 PM UTC 24
Finished Sep 01 06:05:27 PM UTC 24
Peak memory 304936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023207186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2023207186
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.2350841308
Short name T292
Test name
Test status
Simulation time 45733870096 ps
CPU time 1394.09 seconds
Started Sep 01 05:08:39 PM UTC 24
Finished Sep 01 05:32:10 PM UTC 24
Peak memory 302152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350841308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2350841308
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.1379063580
Short name T349
Test name
Test status
Simulation time 7728965800 ps
CPU time 521.46 seconds
Started Sep 01 05:08:23 PM UTC 24
Finished Sep 01 05:17:12 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379063580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1379063580
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.1481714308
Short name T441
Test name
Test status
Simulation time 646254061 ps
CPU time 16.53 seconds
Started Sep 01 05:07:33 PM UTC 24
Finished Sep 01 05:07:51 PM UTC 24
Peak memory 269468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481714308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1481714308
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.1928362053
Short name T114
Test name
Test status
Simulation time 1039481872 ps
CPU time 32.96 seconds
Started Sep 01 05:08:01 PM UTC 24
Finished Sep 01 05:08:35 PM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928362053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1928362053
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.4276074205
Short name T442
Test name
Test status
Simulation time 594686737 ps
CPU time 50.87 seconds
Started Sep 01 05:07:30 PM UTC 24
Finished Sep 01 05:08:22 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276074205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.4276074205
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.1139737858
Short name T451
Test name
Test status
Simulation time 16044030845 ps
CPU time 315.62 seconds
Started Sep 01 05:09:05 PM UTC 24
Finished Sep 01 05:14:26 PM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139737858 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.1139737858
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all_with_rand_reset.2782036476
Short name T156
Test name
Test status
Simulation time 2262698025 ps
CPU time 116.12 seconds
Started Sep 01 05:09:10 PM UTC 24
Finished Sep 01 05:11:08 PM UTC 24
Peak memory 279804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2782036476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.a
lert_handler_stress_all_with_rand_reset.2782036476
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.410174158
Short name T255
Test name
Test status
Simulation time 27065823 ps
CPU time 3.55 seconds
Started Sep 01 05:11:15 PM UTC 24
Finished Sep 01 05:11:20 PM UTC 24
Peak memory 263436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410174158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.410174158
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.1212366538
Short name T552
Test name
Test status
Simulation time 40635311457 ps
CPU time 2917.57 seconds
Started Sep 01 05:10:49 PM UTC 24
Finished Sep 01 06:00:01 PM UTC 24
Peak memory 304676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212366538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1212366538
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.4205026283
Short name T445
Test name
Test status
Simulation time 1681566989 ps
CPU time 34.34 seconds
Started Sep 01 05:11:02 PM UTC 24
Finished Sep 01 05:11:38 PM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205026283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.4205026283
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.3714993168
Short name T454
Test name
Test status
Simulation time 16944575169 ps
CPU time 323.96 seconds
Started Sep 01 05:10:45 PM UTC 24
Finished Sep 01 05:16:13 PM UTC 24
Peak memory 269100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714993168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3714993168
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.847784265
Short name T444
Test name
Test status
Simulation time 871620362 ps
CPU time 20.9 seconds
Started Sep 01 05:10:39 PM UTC 24
Finished Sep 01 05:11:01 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847784265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.847784265
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.4257690607
Short name T384
Test name
Test status
Simulation time 67324781158 ps
CPU time 2747.56 seconds
Started Sep 01 05:10:58 PM UTC 24
Finished Sep 01 05:57:19 PM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257690607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4257690607
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.1155437711
Short name T291
Test name
Test status
Simulation time 46048592306 ps
CPU time 818.42 seconds
Started Sep 01 05:10:59 PM UTC 24
Finished Sep 01 05:24:48 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155437711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1155437711
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.146270723
Short name T355
Test name
Test status
Simulation time 36963183828 ps
CPU time 551.35 seconds
Started Sep 01 05:10:49 PM UTC 24
Finished Sep 01 05:20:08 PM UTC 24
Peak memory 269384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146270723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.146270723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.1509366632
Short name T443
Test name
Test status
Simulation time 1016155345 ps
CPU time 44.09 seconds
Started Sep 01 05:10:02 PM UTC 24
Finished Sep 01 05:10:48 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509366632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1509366632
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.610816270
Short name T84
Test name
Test status
Simulation time 812641466 ps
CPU time 39.54 seconds
Started Sep 01 05:10:03 PM UTC 24
Finished Sep 01 05:10:45 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610816270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.610816270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.3373591083
Short name T145
Test name
Test status
Simulation time 282219439 ps
CPU time 25.75 seconds
Started Sep 01 05:10:47 PM UTC 24
Finished Sep 01 05:11:14 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373591083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3373591083
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.3064778535
Short name T81
Test name
Test status
Simulation time 2020334774 ps
CPU time 45.36 seconds
Started Sep 01 05:09:14 PM UTC 24
Finished Sep 01 05:10:01 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064778535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3064778535
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.1214699330
Short name T446
Test name
Test status
Simulation time 2275687684 ps
CPU time 99.48 seconds
Started Sep 01 05:11:09 PM UTC 24
Finished Sep 01 05:12:51 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214699330 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.1214699330
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all_with_rand_reset.2711743422
Short name T116
Test name
Test status
Simulation time 6464796594 ps
CPU time 99.12 seconds
Started Sep 01 05:11:20 PM UTC 24
Finished Sep 01 05:13:02 PM UTC 24
Peak memory 279476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2711743422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.a
lert_handler_stress_all_with_rand_reset.2711743422
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.1797663594
Short name T256
Test name
Test status
Simulation time 107385628 ps
CPU time 4.89 seconds
Started Sep 01 05:14:22 PM UTC 24
Finished Sep 01 05:14:28 PM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797663594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1797663594
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.3969654640
Short name T140
Test name
Test status
Simulation time 22340527228 ps
CPU time 1611.78 seconds
Started Sep 01 05:13:08 PM UTC 24
Finished Sep 01 05:40:19 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969654640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3969654640
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.2988988549
Short name T450
Test name
Test status
Simulation time 689011630 ps
CPU time 14.85 seconds
Started Sep 01 05:14:04 PM UTC 24
Finished Sep 01 05:14:20 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988988549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2988988549
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.2310165088
Short name T449
Test name
Test status
Simulation time 579693085 ps
CPU time 55.42 seconds
Started Sep 01 05:12:54 PM UTC 24
Finished Sep 01 05:13:52 PM UTC 24
Peak memory 269368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310165088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2310165088
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.3631712311
Short name T448
Test name
Test status
Simulation time 262681907 ps
CPU time 23.2 seconds
Started Sep 01 05:12:51 PM UTC 24
Finished Sep 01 05:13:17 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631712311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3631712311
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.1071569559
Short name T139
Test name
Test status
Simulation time 35289278398 ps
CPU time 2349.16 seconds
Started Sep 01 05:13:52 PM UTC 24
Finished Sep 01 05:53:30 PM UTC 24
Peak memory 295816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071569559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1071569559
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.1914831983
Short name T374
Test name
Test status
Simulation time 17364690695 ps
CPU time 283.38 seconds
Started Sep 01 05:13:18 PM UTC 24
Finished Sep 01 05:18:06 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914831983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1914831983
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.2213145417
Short name T277
Test name
Test status
Simulation time 1863831547 ps
CPU time 84.46 seconds
Started Sep 01 05:12:37 PM UTC 24
Finished Sep 01 05:14:04 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213145417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2213145417
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.526797699
Short name T356
Test name
Test status
Simulation time 243637534 ps
CPU time 14.24 seconds
Started Sep 01 05:13:03 PM UTC 24
Finished Sep 01 05:13:18 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526797699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.526797699
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.2461711633
Short name T447
Test name
Test status
Simulation time 3949100422 ps
CPU time 86.29 seconds
Started Sep 01 05:11:38 PM UTC 24
Finished Sep 01 05:13:07 PM UTC 24
Peak memory 269504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461711633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2461711633
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.1322239728
Short name T498
Test name
Test status
Simulation time 368626505769 ps
CPU time 1535.72 seconds
Started Sep 01 05:14:09 PM UTC 24
Finished Sep 01 05:40:03 PM UTC 24
Peak memory 285564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322239728 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.1322239728
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all_with_rand_reset.485834693
Short name T354
Test name
Test status
Simulation time 7572094237 ps
CPU time 275.79 seconds
Started Sep 01 05:14:27 PM UTC 24
Finished Sep 01 05:19:07 PM UTC 24
Peak memory 281860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=485834693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.al
ert_handler_stress_all_with_rand_reset.485834693
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.2815068031
Short name T257
Test name
Test status
Simulation time 79913267 ps
CPU time 5.46 seconds
Started Sep 01 05:17:12 PM UTC 24
Finished Sep 01 05:17:19 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815068031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2815068031
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.214746613
Short name T455
Test name
Test status
Simulation time 238916676 ps
CPU time 11.23 seconds
Started Sep 01 05:16:59 PM UTC 24
Finished Sep 01 05:17:12 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214746613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.214746613
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.4235660176
Short name T159
Test name
Test status
Simulation time 17897448701 ps
CPU time 333.25 seconds
Started Sep 01 05:15:25 PM UTC 24
Finished Sep 01 05:21:03 PM UTC 24
Peak memory 269176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235660176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.4235660176
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.350444591
Short name T118
Test name
Test status
Simulation time 1115287884 ps
CPU time 96.44 seconds
Started Sep 01 05:15:20 PM UTC 24
Finished Sep 01 05:16:58 PM UTC 24
Peak memory 269408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350444591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.350444591
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.547824526
Short name T388
Test name
Test status
Simulation time 20005716258 ps
CPU time 1625.84 seconds
Started Sep 01 05:16:08 PM UTC 24
Finished Sep 01 05:43:34 PM UTC 24
Peak memory 279356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547824526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.547824526
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.3009084340
Short name T597
Test name
Test status
Simulation time 179681227825 ps
CPU time 3278.69 seconds
Started Sep 01 05:16:15 PM UTC 24
Finished Sep 01 06:11:31 PM UTC 24
Peak memory 305004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009084340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3009084340
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.656482381
Short name T350
Test name
Test status
Simulation time 8633046316 ps
CPU time 357.43 seconds
Started Sep 01 05:16:03 PM UTC 24
Finished Sep 01 05:22:05 PM UTC 24
Peak memory 263368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656482381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.656482381
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.3656670160
Short name T452
Test name
Test status
Simulation time 479013384 ps
CPU time 43.08 seconds
Started Sep 01 05:14:33 PM UTC 24
Finished Sep 01 05:15:18 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656670160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3656670160
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.847874269
Short name T453
Test name
Test status
Simulation time 413632009 ps
CPU time 30.41 seconds
Started Sep 01 05:15:04 PM UTC 24
Finished Sep 01 05:15:36 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847874269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.847874269
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.933643044
Short name T34
Test name
Test status
Simulation time 1980348374 ps
CPU time 95.48 seconds
Started Sep 01 05:14:29 PM UTC 24
Finished Sep 01 05:16:07 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933643044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.933643044
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.3837574048
Short name T532
Test name
Test status
Simulation time 110992142124 ps
CPU time 2053.02 seconds
Started Sep 01 05:17:12 PM UTC 24
Finished Sep 01 05:51:49 PM UTC 24
Peak memory 295804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837574048 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.3837574048
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all_with_rand_reset.2656713296
Short name T460
Test name
Test status
Simulation time 7098676087 ps
CPU time 213.1 seconds
Started Sep 01 05:17:20 PM UTC 24
Finished Sep 01 05:20:56 PM UTC 24
Peak memory 279476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2656713296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.a
lert_handler_stress_all_with_rand_reset.2656713296
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.2494447670
Short name T258
Test name
Test status
Simulation time 39090221 ps
CPU time 5.72 seconds
Started Sep 01 05:20:57 PM UTC 24
Finished Sep 01 05:21:04 PM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494447670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2494447670
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.3259011397
Short name T152
Test name
Test status
Simulation time 18282914079 ps
CPU time 1718.69 seconds
Started Sep 01 05:20:06 PM UTC 24
Finished Sep 01 05:49:04 PM UTC 24
Peak memory 302144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259011397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3259011397
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.2299228528
Short name T461
Test name
Test status
Simulation time 1167564818 ps
CPU time 71.63 seconds
Started Sep 01 05:20:54 PM UTC 24
Finished Sep 01 05:22:07 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299228528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2299228528
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.595041090
Short name T457
Test name
Test status
Simulation time 75441500 ps
CPU time 10.05 seconds
Started Sep 01 05:19:30 PM UTC 24
Finished Sep 01 05:19:42 PM UTC 24
Peak memory 265308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595041090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.595041090
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.937766569
Short name T459
Test name
Test status
Simulation time 1487646288 ps
CPU time 78.13 seconds
Started Sep 01 05:19:22 PM UTC 24
Finished Sep 01 05:20:42 PM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937766569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.937766569
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.185543533
Short name T565
Test name
Test status
Simulation time 126794451182 ps
CPU time 2446.35 seconds
Started Sep 01 05:20:43 PM UTC 24
Finished Sep 01 06:01:59 PM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185543533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.185543533
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.1195213549
Short name T375
Test name
Test status
Simulation time 42314422431 ps
CPU time 149.79 seconds
Started Sep 01 05:20:09 PM UTC 24
Finished Sep 01 05:22:41 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195213549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1195213549
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.1362104962
Short name T458
Test name
Test status
Simulation time 1251695629 ps
CPU time 68.13 seconds
Started Sep 01 05:18:55 PM UTC 24
Finished Sep 01 05:20:05 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362104962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1362104962
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.3004615605
Short name T322
Test name
Test status
Simulation time 11316001481 ps
CPU time 103.86 seconds
Started Sep 01 05:19:08 PM UTC 24
Finished Sep 01 05:20:55 PM UTC 24
Peak memory 263324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004615605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3004615605
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.2773380272
Short name T65
Test name
Test status
Simulation time 3553012826 ps
CPU time 46.58 seconds
Started Sep 01 05:19:42 PM UTC 24
Finished Sep 01 05:20:30 PM UTC 24
Peak memory 262964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773380272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2773380272
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.1778103596
Short name T456
Test name
Test status
Simulation time 704334472 ps
CPU time 71.93 seconds
Started Sep 01 05:18:07 PM UTC 24
Finished Sep 01 05:19:21 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778103596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1778103596
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.211995953
Short name T362
Test name
Test status
Simulation time 51659629427 ps
CPU time 1326.28 seconds
Started Sep 01 05:20:56 PM UTC 24
Finished Sep 01 05:43:18 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211995953 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.211995953
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all_with_rand_reset.2905181602
Short name T68
Test name
Test status
Simulation time 4146047219 ps
CPU time 325.18 seconds
Started Sep 01 05:21:04 PM UTC 24
Finished Sep 01 05:26:34 PM UTC 24
Peak memory 279548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2905181602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.a
lert_handler_stress_all_with_rand_reset.2905181602
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.1735518719
Short name T45
Test name
Test status
Simulation time 36322305 ps
CPU time 6.32 seconds
Started Sep 01 04:56:11 PM UTC 24
Finished Sep 01 04:56:19 PM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735518719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1735518719
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.3793415902
Short name T400
Test name
Test status
Simulation time 138717560161 ps
CPU time 2234.53 seconds
Started Sep 01 04:56:06 PM UTC 24
Finished Sep 01 05:33:45 PM UTC 24
Peak memory 288228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793415902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3793415902
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.294816520
Short name T5
Test name
Test status
Simulation time 963795732 ps
CPU time 14.82 seconds
Started Sep 01 04:56:09 PM UTC 24
Finished Sep 01 04:56:25 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294816520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.294816520
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.416970646
Short name T344
Test name
Test status
Simulation time 3722897435 ps
CPU time 303.46 seconds
Started Sep 01 04:56:04 PM UTC 24
Finished Sep 01 05:01:12 PM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416970646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.416970646
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.4192585377
Short name T97
Test name
Test status
Simulation time 929476555 ps
CPU time 67.29 seconds
Started Sep 01 04:56:04 PM UTC 24
Finished Sep 01 04:57:13 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192585377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.4192585377
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.1136338851
Short name T346
Test name
Test status
Simulation time 153129952562 ps
CPU time 1573.47 seconds
Started Sep 01 04:56:08 PM UTC 24
Finished Sep 01 05:22:40 PM UTC 24
Peak memory 304344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136338851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1136338851
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.343533947
Short name T106
Test name
Test status
Simulation time 995605531 ps
CPU time 38.38 seconds
Started Sep 01 04:56:04 PM UTC 24
Finished Sep 01 04:56:44 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343533947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.343533947
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.2821362000
Short name T51
Test name
Test status
Simulation time 518605116 ps
CPU time 36.83 seconds
Started Sep 01 04:56:12 PM UTC 24
Finished Sep 01 04:56:51 PM UTC 24
Peak memory 295404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821362000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2821362000
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.2717764104
Short name T55
Test name
Test status
Simulation time 805370411 ps
CPU time 34.53 seconds
Started Sep 01 04:56:06 PM UTC 24
Finished Sep 01 04:56:41 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717764104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2717764104
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.2551877433
Short name T18
Test name
Test status
Simulation time 27100954 ps
CPU time 5.99 seconds
Started Sep 01 04:56:03 PM UTC 24
Finished Sep 01 04:56:10 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551877433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2551877433
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.586931035
Short name T127
Test name
Test status
Simulation time 22099963536 ps
CPU time 1902.69 seconds
Started Sep 01 04:56:09 PM UTC 24
Finished Sep 01 05:28:15 PM UTC 24
Peak memory 304616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586931035 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.586931035
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.3308769512
Short name T33
Test name
Test status
Simulation time 16467767949 ps
CPU time 504.99 seconds
Started Sep 01 04:56:11 PM UTC 24
Finished Sep 01 05:04:43 PM UTC 24
Peak memory 285884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3308769512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.al
ert_handler_stress_all_with_rand_reset.3308769512
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.2019916807
Short name T164
Test name
Test status
Simulation time 3679337085 ps
CPU time 115.48 seconds
Started Sep 01 05:22:08 PM UTC 24
Finished Sep 01 05:24:06 PM UTC 24
Peak memory 269176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019916807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2019916807
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.798146501
Short name T313
Test name
Test status
Simulation time 414645806 ps
CPU time 39.47 seconds
Started Sep 01 05:22:07 PM UTC 24
Finished Sep 01 05:22:48 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798146501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.798146501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.1144603816
Short name T396
Test name
Test status
Simulation time 28475175309 ps
CPU time 1662.35 seconds
Started Sep 01 05:22:45 PM UTC 24
Finished Sep 01 05:50:47 PM UTC 24
Peak memory 301956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144603816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1144603816
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.4266068737
Short name T508
Test name
Test status
Simulation time 37204434788 ps
CPU time 1259 seconds
Started Sep 01 05:22:45 PM UTC 24
Finished Sep 01 05:44:00 PM UTC 24
Peak memory 295752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266068737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.4266068737
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.2887165728
Short name T380
Test name
Test status
Simulation time 1773232341 ps
CPU time 68.88 seconds
Started Sep 01 05:22:44 PM UTC 24
Finished Sep 01 05:23:55 PM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887165728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2887165728
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.3148054731
Short name T462
Test name
Test status
Simulation time 987989331 ps
CPU time 51.68 seconds
Started Sep 01 05:21:31 PM UTC 24
Finished Sep 01 05:22:25 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148054731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3148054731
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.2128536838
Short name T66
Test name
Test status
Simulation time 2651453538 ps
CPU time 42.64 seconds
Started Sep 01 05:21:52 PM UTC 24
Finished Sep 01 05:22:37 PM UTC 24
Peak memory 263388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128536838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2128536838
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.3969824157
Short name T463
Test name
Test status
Simulation time 1754223464 ps
CPU time 31.15 seconds
Started Sep 01 05:22:25 PM UTC 24
Finished Sep 01 05:22:58 PM UTC 24
Peak memory 263036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969824157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3969824157
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.548679231
Short name T290
Test name
Test status
Simulation time 922013984 ps
CPU time 45.63 seconds
Started Sep 01 05:21:04 PM UTC 24
Finished Sep 01 05:21:52 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548679231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.548679231
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.2771937457
Short name T473
Test name
Test status
Simulation time 4140467168 ps
CPU time 255.16 seconds
Started Sep 01 05:22:57 PM UTC 24
Finished Sep 01 05:27:16 PM UTC 24
Peak memory 279476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2771937457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a
lert_handler_stress_all_with_rand_reset.2771937457
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.1869396297
Short name T155
Test name
Test status
Simulation time 399148318051 ps
CPU time 3384.29 seconds
Started Sep 01 05:23:48 PM UTC 24
Finished Sep 01 06:20:53 PM UTC 24
Peak memory 304996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869396297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1869396297
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.3228347534
Short name T468
Test name
Test status
Simulation time 1313468038 ps
CPU time 55.77 seconds
Started Sep 01 05:23:42 PM UTC 24
Finished Sep 01 05:24:40 PM UTC 24
Peak memory 269368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228347534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3228347534
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.1005774010
Short name T467
Test name
Test status
Simulation time 1258334789 ps
CPU time 41.16 seconds
Started Sep 01 05:23:23 PM UTC 24
Finished Sep 01 05:24:06 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005774010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1005774010
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.1197541391
Short name T581
Test name
Test status
Simulation time 146221443810 ps
CPU time 2584.42 seconds
Started Sep 01 05:24:07 PM UTC 24
Finished Sep 01 06:07:41 PM UTC 24
Peak memory 288228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197541391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1197541391
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.2640495413
Short name T353
Test name
Test status
Simulation time 59698212410 ps
CPU time 628.39 seconds
Started Sep 01 05:23:56 PM UTC 24
Finished Sep 01 05:34:33 PM UTC 24
Peak memory 263176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640495413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2640495413
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.3471885396
Short name T466
Test name
Test status
Simulation time 1836295393 ps
CPU time 42.23 seconds
Started Sep 01 05:23:03 PM UTC 24
Finished Sep 01 05:23:47 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471885396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3471885396
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.3714171784
Short name T465
Test name
Test status
Simulation time 1427639813 ps
CPU time 31.55 seconds
Started Sep 01 05:23:12 PM UTC 24
Finished Sep 01 05:23:45 PM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714171784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3714171784
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.4217344814
Short name T318
Test name
Test status
Simulation time 529594117 ps
CPU time 49.69 seconds
Started Sep 01 05:23:46 PM UTC 24
Finished Sep 01 05:24:38 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217344814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.4217344814
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.3485993293
Short name T464
Test name
Test status
Simulation time 819432470 ps
CPU time 23.39 seconds
Started Sep 01 05:22:58 PM UTC 24
Finished Sep 01 05:23:23 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485993293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3485993293
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.1410623564
Short name T122
Test name
Test status
Simulation time 24751579534 ps
CPU time 2640.23 seconds
Started Sep 01 05:24:39 PM UTC 24
Finished Sep 01 06:09:12 PM UTC 24
Peak memory 320984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410623564 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.1410623564
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/21.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.1005361501
Short name T537
Test name
Test status
Simulation time 27580036660 ps
CPU time 1581.7 seconds
Started Sep 01 05:26:20 PM UTC 24
Finished Sep 01 05:53:00 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005361501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1005361501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.2721105136
Short name T475
Test name
Test status
Simulation time 5004665495 ps
CPU time 142.34 seconds
Started Sep 01 05:26:12 PM UTC 24
Finished Sep 01 05:28:37 PM UTC 24
Peak memory 269100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721105136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2721105136
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.2487594954
Short name T472
Test name
Test status
Simulation time 621924245 ps
CPU time 59.72 seconds
Started Sep 01 05:26:08 PM UTC 24
Finished Sep 01 05:27:09 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487594954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2487594954
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.3663884774
Short name T392
Test name
Test status
Simulation time 36471078360 ps
CPU time 1775.95 seconds
Started Sep 01 05:26:38 PM UTC 24
Finished Sep 01 05:56:37 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663884774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3663884774
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.1329862352
Short name T551
Test name
Test status
Simulation time 15834081800 ps
CPU time 1936.07 seconds
Started Sep 01 05:27:11 PM UTC 24
Finished Sep 01 05:59:51 PM UTC 24
Peak memory 301960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329862352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1329862352
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.746545888
Short name T378
Test name
Test status
Simulation time 34966530636 ps
CPU time 445.46 seconds
Started Sep 01 05:26:35 PM UTC 24
Finished Sep 01 05:34:07 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746545888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.746545888
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.1486391751
Short name T471
Test name
Test status
Simulation time 878917819 ps
CPU time 77.14 seconds
Started Sep 01 05:25:00 PM UTC 24
Finished Sep 01 05:26:19 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486391751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1486391751
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.2243298516
Short name T470
Test name
Test status
Simulation time 151927482 ps
CPU time 6.23 seconds
Started Sep 01 05:26:03 PM UTC 24
Finished Sep 01 05:26:10 PM UTC 24
Peak memory 252764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243298516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2243298516
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.694219613
Short name T469
Test name
Test status
Simulation time 109503519 ps
CPU time 7.87 seconds
Started Sep 01 05:24:50 PM UTC 24
Finished Sep 01 05:24:59 PM UTC 24
Peak memory 264948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694219613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.694219613
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.2044246908
Short name T129
Test name
Test status
Simulation time 7537216603 ps
CPU time 391.29 seconds
Started Sep 01 05:27:18 PM UTC 24
Finished Sep 01 05:33:55 PM UTC 24
Peak memory 265340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044246908 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.2044246908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all_with_rand_reset.834475578
Short name T128
Test name
Test status
Simulation time 3766803576 ps
CPU time 130.61 seconds
Started Sep 01 05:27:42 PM UTC 24
Finished Sep 01 05:29:55 PM UTC 24
Peak memory 279812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=834475578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.al
ert_handler_stress_all_with_rand_reset.834475578
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.2157002302
Short name T619
Test name
Test status
Simulation time 72779123482 ps
CPU time 2793.33 seconds
Started Sep 01 05:29:30 PM UTC 24
Finished Sep 01 06:16:38 PM UTC 24
Peak memory 288216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157002302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2157002302
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.2874524802
Short name T484
Test name
Test status
Simulation time 4411591168 ps
CPU time 322.41 seconds
Started Sep 01 05:29:13 PM UTC 24
Finished Sep 01 05:34:41 PM UTC 24
Peak memory 269100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874524802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2874524802
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.2188861466
Short name T476
Test name
Test status
Simulation time 158341327 ps
CPU time 14.94 seconds
Started Sep 01 05:28:56 PM UTC 24
Finished Sep 01 05:29:12 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188861466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2188861466
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.1758922143
Short name T391
Test name
Test status
Simulation time 45035255941 ps
CPU time 2583.05 seconds
Started Sep 01 05:29:41 PM UTC 24
Finished Sep 01 06:13:14 PM UTC 24
Peak memory 298464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758922143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1758922143
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.736608578
Short name T528
Test name
Test status
Simulation time 12790584141 ps
CPU time 1186.63 seconds
Started Sep 01 05:29:42 PM UTC 24
Finished Sep 01 05:49:44 PM UTC 24
Peak memory 298120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736608578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.736608578
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.347577469
Short name T368
Test name
Test status
Simulation time 25223506889 ps
CPU time 288.19 seconds
Started Sep 01 05:29:34 PM UTC 24
Finished Sep 01 05:34:26 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347577469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.347577469
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.502073943
Short name T286
Test name
Test status
Simulation time 866663137 ps
CPU time 20.7 seconds
Started Sep 01 05:28:33 PM UTC 24
Finished Sep 01 05:28:55 PM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502073943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.502073943
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.3587819833
Short name T477
Test name
Test status
Simulation time 3139510131 ps
CPU time 36.5 seconds
Started Sep 01 05:28:38 PM UTC 24
Finished Sep 01 05:29:15 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587819833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3587819833
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.3528390428
Short name T478
Test name
Test status
Simulation time 109246758 ps
CPU time 11.47 seconds
Started Sep 01 05:29:16 PM UTC 24
Finished Sep 01 05:29:29 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528390428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3528390428
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.302764332
Short name T479
Test name
Test status
Simulation time 943020783 ps
CPU time 80.57 seconds
Started Sep 01 05:28:18 PM UTC 24
Finished Sep 01 05:29:41 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302764332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.302764332
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all_with_rand_reset.4273173091
Short name T142
Test name
Test status
Simulation time 41436556919 ps
CPU time 621.63 seconds
Started Sep 01 05:29:56 PM UTC 24
Finished Sep 01 05:40:27 PM UTC 24
Peak memory 283572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4273173091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.a
lert_handler_stress_all_with_rand_reset.4273173091
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.371892125
Short name T621
Test name
Test status
Simulation time 141090491781 ps
CPU time 2666.78 seconds
Started Sep 01 05:31:55 PM UTC 24
Finished Sep 01 06:16:54 PM UTC 24
Peak memory 304936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371892125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.371892125
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.2442999292
Short name T488
Test name
Test status
Simulation time 2508364881 ps
CPU time 229.64 seconds
Started Sep 01 05:31:37 PM UTC 24
Finished Sep 01 05:35:30 PM UTC 24
Peak memory 269432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442999292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2442999292
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.891319559
Short name T483
Test name
Test status
Simulation time 934965457 ps
CPU time 86.28 seconds
Started Sep 01 05:31:14 PM UTC 24
Finished Sep 01 05:32:42 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891319559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.891319559
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.1937346287
Short name T403
Test name
Test status
Simulation time 131290171816 ps
CPU time 2142.32 seconds
Started Sep 01 05:32:43 PM UTC 24
Finished Sep 01 06:08:49 PM UTC 24
Peak memory 299836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937346287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1937346287
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.3202852993
Short name T536
Test name
Test status
Simulation time 172783352170 ps
CPU time 1175.5 seconds
Started Sep 01 05:33:05 PM UTC 24
Finished Sep 01 05:52:57 PM UTC 24
Peak memory 298184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202852993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3202852993
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.2538582945
Short name T481
Test name
Test status
Simulation time 390977890 ps
CPU time 38.58 seconds
Started Sep 01 05:30:56 PM UTC 24
Finished Sep 01 05:31:36 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538582945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2538582945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.404808568
Short name T482
Test name
Test status
Simulation time 13468437537 ps
CPU time 45.45 seconds
Started Sep 01 05:31:07 PM UTC 24
Finished Sep 01 05:31:54 PM UTC 24
Peak memory 262964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404808568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.404808568
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.3760415151
Short name T324
Test name
Test status
Simulation time 1503889375 ps
CPU time 74.35 seconds
Started Sep 01 05:31:48 PM UTC 24
Finished Sep 01 05:33:04 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760415151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3760415151
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.2487975236
Short name T480
Test name
Test status
Simulation time 206269878 ps
CPU time 16.1 seconds
Started Sep 01 05:30:49 PM UTC 24
Finished Sep 01 05:31:07 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487975236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2487975236
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.3539209347
Short name T588
Test name
Test status
Simulation time 25155834997 ps
CPU time 2116.14 seconds
Started Sep 01 05:33:29 PM UTC 24
Finished Sep 01 06:09:11 PM UTC 24
Peak memory 299828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539209347 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.3539209347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/24.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.51200286
Short name T560
Test name
Test status
Simulation time 23300699401 ps
CPU time 1559.95 seconds
Started Sep 01 05:34:42 PM UTC 24
Finished Sep 01 06:01:01 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51200286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/a
lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.51200286
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.521951059
Short name T487
Test name
Test status
Simulation time 287093500 ps
CPU time 29.5 seconds
Started Sep 01 05:34:34 PM UTC 24
Finished Sep 01 05:35:05 PM UTC 24
Peak memory 269404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521951059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.521951059
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.3983975919
Short name T486
Test name
Test status
Simulation time 689850917 ps
CPU time 31.59 seconds
Started Sep 01 05:34:27 PM UTC 24
Finished Sep 01 05:35:00 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983975919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3983975919
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.1796751256
Short name T398
Test name
Test status
Simulation time 97940938835 ps
CPU time 1686.41 seconds
Started Sep 01 05:34:49 PM UTC 24
Finished Sep 01 06:03:16 PM UTC 24
Peak memory 285892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796751256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1796751256
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.2910859277
Short name T305
Test name
Test status
Simulation time 32500606815 ps
CPU time 2210.11 seconds
Started Sep 01 05:34:51 PM UTC 24
Finished Sep 01 06:12:08 PM UTC 24
Peak memory 295748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910859277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2910859277
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.2841236755
Short name T373
Test name
Test status
Simulation time 3689013294 ps
CPU time 169.47 seconds
Started Sep 01 05:34:44 PM UTC 24
Finished Sep 01 05:37:36 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841236755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2841236755
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.4099457856
Short name T314
Test name
Test status
Simulation time 494053252 ps
CPU time 45.16 seconds
Started Sep 01 05:33:56 PM UTC 24
Finished Sep 01 05:34:43 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099457856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.4099457856
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.2592803029
Short name T72
Test name
Test status
Simulation time 160899371 ps
CPU time 25.72 seconds
Started Sep 01 05:34:08 PM UTC 24
Finished Sep 01 05:34:35 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592803029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2592803029
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.1412105687
Short name T315
Test name
Test status
Simulation time 124449391 ps
CPU time 12.62 seconds
Started Sep 01 05:34:37 PM UTC 24
Finished Sep 01 05:34:51 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412105687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1412105687
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.930568494
Short name T485
Test name
Test status
Simulation time 1292358907 ps
CPU time 59.39 seconds
Started Sep 01 05:33:47 PM UTC 24
Finished Sep 01 05:34:48 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930568494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.930568494
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.3738176103
Short name T557
Test name
Test status
Simulation time 118466353682 ps
CPU time 1531.02 seconds
Started Sep 01 05:34:59 PM UTC 24
Finished Sep 01 06:00:50 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738176103 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.3738176103
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/25.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.2535511892
Short name T584
Test name
Test status
Simulation time 29224030074 ps
CPU time 1938.63 seconds
Started Sep 01 05:36:07 PM UTC 24
Finished Sep 01 06:08:49 PM UTC 24
Peak memory 285492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535511892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2535511892
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.2185716912
Short name T495
Test name
Test status
Simulation time 977100943 ps
CPU time 127.32 seconds
Started Sep 01 05:35:47 PM UTC 24
Finished Sep 01 05:37:58 PM UTC 24
Peak memory 269040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185716912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2185716912
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.3323288476
Short name T490
Test name
Test status
Simulation time 649366547 ps
CPU time 42.15 seconds
Started Sep 01 05:35:33 PM UTC 24
Finished Sep 01 05:36:17 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323288476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3323288476
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.1253446219
Short name T630
Test name
Test status
Simulation time 181141653605 ps
CPU time 2466.69 seconds
Started Sep 01 05:36:23 PM UTC 24
Finished Sep 01 06:17:59 PM UTC 24
Peak memory 302560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253446219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1253446219
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.3224519751
Short name T365
Test name
Test status
Simulation time 26973773273 ps
CPU time 653.62 seconds
Started Sep 01 05:36:09 PM UTC 24
Finished Sep 01 05:47:11 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224519751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3224519751
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.316012622
Short name T73
Test name
Test status
Simulation time 2347754503 ps
CPU time 78.69 seconds
Started Sep 01 05:35:13 PM UTC 24
Finished Sep 01 05:36:33 PM UTC 24
Peak memory 269220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316012622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.316012622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.3037284166
Short name T304
Test name
Test status
Simulation time 2245489223 ps
CPU time 31.01 seconds
Started Sep 01 05:35:33 PM UTC 24
Finished Sep 01 05:36:06 PM UTC 24
Peak memory 262996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037284166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3037284166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.2740219198
Short name T361
Test name
Test status
Simulation time 409306021 ps
CPU time 40.04 seconds
Started Sep 01 05:35:50 PM UTC 24
Finished Sep 01 05:36:31 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740219198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2740219198
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.2604076687
Short name T489
Test name
Test status
Simulation time 710725692 ps
CPU time 61.74 seconds
Started Sep 01 05:35:05 PM UTC 24
Finished Sep 01 05:36:09 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604076687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2604076687
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.2939963450
Short name T511
Test name
Test status
Simulation time 8643198507 ps
CPU time 493 seconds
Started Sep 01 05:36:33 PM UTC 24
Finished Sep 01 05:44:53 PM UTC 24
Peak memory 269244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939963450 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.2939963450
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.352306586
Short name T358
Test name
Test status
Simulation time 9260347137 ps
CPU time 268.88 seconds
Started Sep 01 05:36:34 PM UTC 24
Finished Sep 01 05:41:07 PM UTC 24
Peak memory 279812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=352306586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.al
ert_handler_stress_all_with_rand_reset.352306586
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.1470897460
Short name T299
Test name
Test status
Simulation time 41489674211 ps
CPU time 3100.51 seconds
Started Sep 01 05:37:47 PM UTC 24
Finished Sep 01 06:30:04 PM UTC 24
Peak memory 304676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470897460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1470897460
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.2010303337
Short name T497
Test name
Test status
Simulation time 709579957 ps
CPU time 58.26 seconds
Started Sep 01 05:37:37 PM UTC 24
Finished Sep 01 05:38:37 PM UTC 24
Peak memory 269040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010303337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2010303337
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.1463794681
Short name T494
Test name
Test status
Simulation time 357483299 ps
CPU time 19.26 seconds
Started Sep 01 05:37:25 PM UTC 24
Finished Sep 01 05:37:46 PM UTC 24
Peak memory 262936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463794681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1463794681
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.4263101349
Short name T408
Test name
Test status
Simulation time 72591641314 ps
CPU time 2737.76 seconds
Started Sep 01 05:38:00 PM UTC 24
Finished Sep 01 06:24:11 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263101349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4263101349
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.898707726
Short name T627
Test name
Test status
Simulation time 67207395058 ps
CPU time 2354.65 seconds
Started Sep 01 05:38:00 PM UTC 24
Finished Sep 01 06:17:42 PM UTC 24
Peak memory 286968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898707726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.898707726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.2735502907
Short name T278
Test name
Test status
Simulation time 13325782810 ps
CPU time 460.3 seconds
Started Sep 01 05:37:59 PM UTC 24
Finished Sep 01 05:45:45 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735502907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2735502907
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.709017677
Short name T492
Test name
Test status
Simulation time 118081914 ps
CPU time 7.41 seconds
Started Sep 01 05:36:49 PM UTC 24
Finished Sep 01 05:36:57 PM UTC 24
Peak memory 264984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709017677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.709017677
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.719123800
Short name T74
Test name
Test status
Simulation time 436913002 ps
CPU time 59.53 seconds
Started Sep 01 05:36:58 PM UTC 24
Finished Sep 01 05:37:59 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719123800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.719123800
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.3663255799
Short name T496
Test name
Test status
Simulation time 129591062 ps
CPU time 13.97 seconds
Started Sep 01 05:37:45 PM UTC 24
Finished Sep 01 05:38:00 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663255799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3663255799
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.272250222
Short name T493
Test name
Test status
Simulation time 3556998961 ps
CPU time 63.33 seconds
Started Sep 01 05:36:39 PM UTC 24
Finished Sep 01 05:37:44 PM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272250222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.272250222
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/27.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.1117057987
Short name T637
Test name
Test status
Simulation time 26716403513 ps
CPU time 2223.73 seconds
Started Sep 01 05:41:07 PM UTC 24
Finished Sep 01 06:18:40 PM UTC 24
Peak memory 297860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117057987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1117057987
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.3610487641
Short name T509
Test name
Test status
Simulation time 10123223968 ps
CPU time 230.05 seconds
Started Sep 01 05:40:33 PM UTC 24
Finished Sep 01 05:44:27 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610487641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3610487641
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.967181649
Short name T500
Test name
Test status
Simulation time 915265301 ps
CPU time 46.59 seconds
Started Sep 01 05:40:28 PM UTC 24
Finished Sep 01 05:41:16 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967181649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.967181649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.1628239579
Short name T406
Test name
Test status
Simulation time 31924173676 ps
CPU time 1892.01 seconds
Started Sep 01 05:41:19 PM UTC 24
Finished Sep 01 06:13:12 PM UTC 24
Peak memory 301956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628239579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1628239579
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.2580238873
Short name T640
Test name
Test status
Simulation time 122788105983 ps
CPU time 2255.36 seconds
Started Sep 01 05:41:22 PM UTC 24
Finished Sep 01 06:19:24 PM UTC 24
Peak memory 295744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580238873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2580238873
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.1284710713
Short name T76
Test name
Test status
Simulation time 2748175123 ps
CPU time 68.02 seconds
Started Sep 01 05:40:23 PM UTC 24
Finished Sep 01 05:41:33 PM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284710713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1284710713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.1571832123
Short name T119
Test name
Test status
Simulation time 4233514931 ps
CPU time 78.45 seconds
Started Sep 01 05:40:23 PM UTC 24
Finished Sep 01 05:41:43 PM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571832123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1571832123
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.2274640909
Short name T323
Test name
Test status
Simulation time 408740058 ps
CPU time 35.96 seconds
Started Sep 01 05:40:43 PM UTC 24
Finished Sep 01 05:41:20 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274640909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2274640909
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.2115768803
Short name T499
Test name
Test status
Simulation time 483913668 ps
CPU time 35.32 seconds
Started Sep 01 05:40:06 PM UTC 24
Finished Sep 01 05:40:42 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115768803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2115768803
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all_with_rand_reset.3972226724
Short name T503
Test name
Test status
Simulation time 3500426474 ps
CPU time 79.5 seconds
Started Sep 01 05:41:44 PM UTC 24
Finished Sep 01 05:43:06 PM UTC 24
Peak memory 283900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3972226724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.a
lert_handler_stress_all_with_rand_reset.3972226724
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.2278895333
Short name T514
Test name
Test status
Simulation time 3648122658 ps
CPU time 120.91 seconds
Started Sep 01 05:43:07 PM UTC 24
Finished Sep 01 05:45:11 PM UTC 24
Peak memory 269496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278895333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2278895333
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.48214770
Short name T505
Test name
Test status
Simulation time 292225016 ps
CPU time 40.65 seconds
Started Sep 01 05:42:45 PM UTC 24
Finished Sep 01 05:43:27 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48214770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.48214770
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.430989762
Short name T685
Test name
Test status
Simulation time 253711967257 ps
CPU time 3354.71 seconds
Started Sep 01 05:43:31 PM UTC 24
Finished Sep 01 06:40:07 PM UTC 24
Peak memory 298460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430989762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.430989762
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.4128729732
Short name T575
Test name
Test status
Simulation time 38092255131 ps
CPU time 1271.72 seconds
Started Sep 01 05:43:32 PM UTC 24
Finished Sep 01 06:05:00 PM UTC 24
Peak memory 297796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128729732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.4128729732
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.177099999
Short name T504
Test name
Test status
Simulation time 482270125 ps
CPU time 44.3 seconds
Started Sep 01 05:42:36 PM UTC 24
Finished Sep 01 05:43:22 PM UTC 24
Peak memory 269084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177099999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.177099999
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.4153233282
Short name T507
Test name
Test status
Simulation time 1600226118 ps
CPU time 50.87 seconds
Started Sep 01 05:42:39 PM UTC 24
Finished Sep 01 05:43:31 PM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153233282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.4153233282
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.1167637437
Short name T506
Test name
Test status
Simulation time 123606432 ps
CPU time 7.61 seconds
Started Sep 01 05:43:21 PM UTC 24
Finished Sep 01 05:43:30 PM UTC 24
Peak memory 252660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167637437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1167637437
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.3767225968
Short name T501
Test name
Test status
Simulation time 210900249 ps
CPU time 32.99 seconds
Started Sep 01 05:42:04 PM UTC 24
Finished Sep 01 05:42:38 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767225968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3767225968
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.3112782077
Short name T515
Test name
Test status
Simulation time 4786437593 ps
CPU time 97.92 seconds
Started Sep 01 05:43:36 PM UTC 24
Finished Sep 01 05:45:16 PM UTC 24
Peak memory 262964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112782077 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.3112782077
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all_with_rand_reset.2361262629
Short name T312
Test name
Test status
Simulation time 1989396584 ps
CPU time 222.78 seconds
Started Sep 01 05:43:44 PM UTC 24
Finished Sep 01 05:47:31 PM UTC 24
Peak memory 285628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2361262629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.a
lert_handler_stress_all_with_rand_reset.2361262629
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.174810626
Short name T53
Test name
Test status
Simulation time 15721663 ps
CPU time 4.41 seconds
Started Sep 01 04:56:21 PM UTC 24
Finished Sep 01 04:56:26 PM UTC 24
Peak memory 263176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174810626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.174810626
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.2480625174
Short name T359
Test name
Test status
Simulation time 88369713551 ps
CPU time 2327.47 seconds
Started Sep 01 04:56:16 PM UTC 24
Finished Sep 01 05:35:31 PM UTC 24
Peak memory 304680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480625174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2480625174
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.1970120108
Short name T131
Test name
Test status
Simulation time 5360234200 ps
CPU time 96.71 seconds
Started Sep 01 04:56:15 PM UTC 24
Finished Sep 01 04:57:54 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970120108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1970120108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.19183497
Short name T95
Test name
Test status
Simulation time 676102534 ps
CPU time 33.8 seconds
Started Sep 01 04:56:15 PM UTC 24
Finished Sep 01 04:56:50 PM UTC 24
Peak memory 263324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19183497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.19183497
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.2073075119
Short name T332
Test name
Test status
Simulation time 23139629381 ps
CPU time 1056.2 seconds
Started Sep 01 04:56:17 PM UTC 24
Finished Sep 01 05:14:06 PM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073075119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2073075119
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.1385470248
Short name T491
Test name
Test status
Simulation time 31931173381 ps
CPU time 2390.79 seconds
Started Sep 01 04:56:17 PM UTC 24
Finished Sep 01 05:36:37 PM UTC 24
Peak memory 288220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385470248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1385470248
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.2873167550
Short name T23
Test name
Test status
Simulation time 11358029520 ps
CPU time 193.1 seconds
Started Sep 01 04:56:16 PM UTC 24
Finished Sep 01 04:59:33 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873167550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2873167550
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.682335947
Short name T47
Test name
Test status
Simulation time 162649117 ps
CPU time 10.63 seconds
Started Sep 01 04:56:14 PM UTC 24
Finished Sep 01 04:56:25 PM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682335947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.682335947
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.2756815108
Short name T56
Test name
Test status
Simulation time 426810492 ps
CPU time 33.9 seconds
Started Sep 01 04:56:14 PM UTC 24
Finished Sep 01 04:56:49 PM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756815108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2756815108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.2985722142
Short name T8
Test name
Test status
Simulation time 748846369 ps
CPU time 16.16 seconds
Started Sep 01 04:56:26 PM UTC 24
Finished Sep 01 04:56:45 PM UTC 24
Peak memory 297452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985722142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2985722142
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.1765509852
Short name T46
Test name
Test status
Simulation time 311385070 ps
CPU time 25.83 seconds
Started Sep 01 04:56:15 PM UTC 24
Finished Sep 01 04:56:42 PM UTC 24
Peak memory 269408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765509852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1765509852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.650369292
Short name T54
Test name
Test status
Simulation time 254264791 ps
CPU time 21.54 seconds
Started Sep 01 04:56:12 PM UTC 24
Finished Sep 01 04:56:35 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650369292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.650369292
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.2709559698
Short name T130
Test name
Test status
Simulation time 24229524289 ps
CPU time 2433.28 seconds
Started Sep 01 04:56:19 PM UTC 24
Finished Sep 01 05:37:22 PM UTC 24
Peak memory 314912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709559698 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.2709559698
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/3.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.4199066040
Short name T680
Test name
Test status
Simulation time 36531553375 ps
CPU time 2898.07 seconds
Started Sep 01 05:45:08 PM UTC 24
Finished Sep 01 06:33:59 PM UTC 24
Peak memory 304996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199066040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.4199066040
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.3414802656
Short name T522
Test name
Test status
Simulation time 1805333541 ps
CPU time 123.55 seconds
Started Sep 01 05:44:54 PM UTC 24
Finished Sep 01 05:47:00 PM UTC 24
Peak memory 269040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414802656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3414802656
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.1022004699
Short name T517
Test name
Test status
Simulation time 3116720540 ps
CPU time 54.89 seconds
Started Sep 01 05:44:48 PM UTC 24
Finished Sep 01 05:45:44 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022004699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1022004699
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.3166926849
Short name T394
Test name
Test status
Simulation time 33795093027 ps
CPU time 1858.38 seconds
Started Sep 01 05:45:11 PM UTC 24
Finished Sep 01 06:16:31 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166926849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3166926849
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.3400808514
Short name T631
Test name
Test status
Simulation time 29877191002 ps
CPU time 1941.31 seconds
Started Sep 01 05:45:17 PM UTC 24
Finished Sep 01 06:18:02 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400808514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3400808514
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.456820786
Short name T372
Test name
Test status
Simulation time 51257768407 ps
CPU time 772.08 seconds
Started Sep 01 05:45:09 PM UTC 24
Finished Sep 01 05:58:11 PM UTC 24
Peak memory 269256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456820786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.456820786
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.2771844283
Short name T516
Test name
Test status
Simulation time 1183435301 ps
CPU time 61.18 seconds
Started Sep 01 05:44:28 PM UTC 24
Finished Sep 01 05:45:31 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771844283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2771844283
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.4181423187
Short name T296
Test name
Test status
Simulation time 511626652 ps
CPU time 32.07 seconds
Started Sep 01 05:44:33 PM UTC 24
Finished Sep 01 05:45:07 PM UTC 24
Peak memory 262932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181423187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.4181423187
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.3449749365
Short name T510
Test name
Test status
Simulation time 503775673 ps
CPU time 27.76 seconds
Started Sep 01 05:44:03 PM UTC 24
Finished Sep 01 05:44:32 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449749365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3449749365
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.3266496314
Short name T121
Test name
Test status
Simulation time 14826906318 ps
CPU time 1305.19 seconds
Started Sep 01 05:46:36 PM UTC 24
Finished Sep 01 06:08:37 PM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266496314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3266496314
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.3123337510
Short name T520
Test name
Test status
Simulation time 582271009 ps
CPU time 24.02 seconds
Started Sep 01 05:46:15 PM UTC 24
Finished Sep 01 05:46:40 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123337510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3123337510
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.2742195730
Short name T521
Test name
Test status
Simulation time 1501799683 ps
CPU time 63.76 seconds
Started Sep 01 05:45:53 PM UTC 24
Finished Sep 01 05:46:59 PM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742195730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2742195730
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.3564578949
Short name T367
Test name
Test status
Simulation time 8416799107 ps
CPU time 365.02 seconds
Started Sep 01 05:46:41 PM UTC 24
Finished Sep 01 05:52:51 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564578949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3564578949
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.799845096
Short name T519
Test name
Test status
Simulation time 626016893 ps
CPU time 36.42 seconds
Started Sep 01 05:45:47 PM UTC 24
Finished Sep 01 05:46:25 PM UTC 24
Peak memory 269068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799845096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.799845096
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.779586510
Short name T153
Test name
Test status
Simulation time 1634267130 ps
CPU time 45.44 seconds
Started Sep 01 05:45:48 PM UTC 24
Finished Sep 01 05:46:35 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779586510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.779586510
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.1110240625
Short name T328
Test name
Test status
Simulation time 268671260 ps
CPU time 28.47 seconds
Started Sep 01 05:46:26 PM UTC 24
Finished Sep 01 05:46:56 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110240625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1110240625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.3158021035
Short name T518
Test name
Test status
Simulation time 179098476 ps
CPU time 27.13 seconds
Started Sep 01 05:45:46 PM UTC 24
Finished Sep 01 05:46:14 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158021035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3158021035
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.198873800
Short name T606
Test name
Test status
Simulation time 15503404336 ps
CPU time 1550.25 seconds
Started Sep 01 05:47:54 PM UTC 24
Finished Sep 01 06:14:04 PM UTC 24
Peak memory 279428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198873800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.198873800
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.2098575392
Short name T306
Test name
Test status
Simulation time 2313055825 ps
CPU time 70.79 seconds
Started Sep 01 05:47:38 PM UTC 24
Finished Sep 01 05:48:51 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098575392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2098575392
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.659301152
Short name T524
Test name
Test status
Simulation time 44043701 ps
CPU time 4.49 seconds
Started Sep 01 05:47:32 PM UTC 24
Finished Sep 01 05:47:37 PM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659301152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.659301152
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.422796624
Short name T386
Test name
Test status
Simulation time 33221286248 ps
CPU time 1885.91 seconds
Started Sep 01 05:48:50 PM UTC 24
Finished Sep 01 06:20:37 PM UTC 24
Peak memory 297784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422796624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.422796624
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.269537374
Short name T590
Test name
Test status
Simulation time 58139637400 ps
CPU time 1222.97 seconds
Started Sep 01 05:48:52 PM UTC 24
Finished Sep 01 06:09:30 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269537374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.269537374
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.2378927577
Short name T523
Test name
Test status
Simulation time 112904278 ps
CPU time 6.9 seconds
Started Sep 01 05:47:12 PM UTC 24
Finished Sep 01 05:47:20 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378927577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2378927577
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.1932671804
Short name T525
Test name
Test status
Simulation time 246519671 ps
CPU time 27.01 seconds
Started Sep 01 05:47:22 PM UTC 24
Finished Sep 01 05:47:50 PM UTC 24
Peak memory 262916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932671804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1932671804
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.440753053
Short name T527
Test name
Test status
Simulation time 543758676 ps
CPU time 56.05 seconds
Started Sep 01 05:47:51 PM UTC 24
Finished Sep 01 05:48:49 PM UTC 24
Peak memory 269408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440753053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.440753053
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.2772061049
Short name T526
Test name
Test status
Simulation time 1336808448 ps
CPU time 39.12 seconds
Started Sep 01 05:47:12 PM UTC 24
Finished Sep 01 05:47:53 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772061049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2772061049
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.1383869527
Short name T691
Test name
Test status
Simulation time 53114153189 ps
CPU time 3424 seconds
Started Sep 01 05:49:07 PM UTC 24
Finished Sep 01 06:46:50 PM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383869527 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.1383869527
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all_with_rand_reset.70659211
Short name T77
Test name
Test status
Simulation time 15868411018 ps
CPU time 292.8 seconds
Started Sep 01 05:49:46 PM UTC 24
Finished Sep 01 05:54:45 PM UTC 24
Peak memory 279556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=70659211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.ale
rt_handler_stress_all_with_rand_reset.70659211
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.3528484224
Short name T539
Test name
Test status
Simulation time 1579230299 ps
CPU time 146.27 seconds
Started Sep 01 05:51:52 PM UTC 24
Finished Sep 01 05:54:21 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528484224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3528484224
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.3437665630
Short name T533
Test name
Test status
Simulation time 5749952319 ps
CPU time 42.24 seconds
Started Sep 01 05:51:30 PM UTC 24
Finished Sep 01 05:52:14 PM UTC 24
Peak memory 269216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437665630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3437665630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.3118367715
Short name T632
Test name
Test status
Simulation time 60028698434 ps
CPU time 1506.7 seconds
Started Sep 01 05:52:38 PM UTC 24
Finished Sep 01 06:18:04 PM UTC 24
Peak memory 299836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118367715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3118367715
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.2255111642
Short name T610
Test name
Test status
Simulation time 42677161845 ps
CPU time 1298.15 seconds
Started Sep 01 05:52:52 PM UTC 24
Finished Sep 01 06:14:45 PM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255111642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2255111642
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.3897344573
Short name T377
Test name
Test status
Simulation time 13078080420 ps
CPU time 425.68 seconds
Started Sep 01 05:52:34 PM UTC 24
Finished Sep 01 05:59:46 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897344573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3897344573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.1446222531
Short name T535
Test name
Test status
Simulation time 1202530439 ps
CPU time 101.79 seconds
Started Sep 01 05:50:53 PM UTC 24
Finished Sep 01 05:52:38 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446222531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1446222531
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.2372342220
Short name T154
Test name
Test status
Simulation time 405782595 ps
CPU time 36.69 seconds
Started Sep 01 05:51:27 PM UTC 24
Finished Sep 01 05:52:05 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372342220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2372342220
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.4080421530
Short name T534
Test name
Test status
Simulation time 400900088 ps
CPU time 26.39 seconds
Started Sep 01 05:52:06 PM UTC 24
Finished Sep 01 05:52:33 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080421530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.4080421530
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.435958976
Short name T531
Test name
Test status
Simulation time 1477769550 ps
CPU time 37.56 seconds
Started Sep 01 05:50:50 PM UTC 24
Finished Sep 01 05:51:29 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435958976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.435958976
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all_with_rand_reset.567290009
Short name T310
Test name
Test status
Simulation time 4684344731 ps
CPU time 557.68 seconds
Started Sep 01 05:53:03 PM UTC 24
Finished Sep 01 06:02:27 PM UTC 24
Peak memory 285892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=567290009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.al
ert_handler_stress_all_with_rand_reset.567290009
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.1152803553
Short name T688
Test name
Test status
Simulation time 38992430103 ps
CPU time 3052.46 seconds
Started Sep 01 05:54:22 PM UTC 24
Finished Sep 01 06:45:50 PM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152803553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1152803553
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.639674386
Short name T544
Test name
Test status
Simulation time 4630798806 ps
CPU time 168.12 seconds
Started Sep 01 05:54:12 PM UTC 24
Finished Sep 01 05:57:03 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639674386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.639674386
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.481587220
Short name T540
Test name
Test status
Simulation time 1460595163 ps
CPU time 66.78 seconds
Started Sep 01 05:54:00 PM UTC 24
Finished Sep 01 05:55:09 PM UTC 24
Peak memory 269216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481587220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.481587220
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.462384602
Short name T674
Test name
Test status
Simulation time 100696992253 ps
CPU time 2161.24 seconds
Started Sep 01 05:55:10 PM UTC 24
Finished Sep 01 06:31:37 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462384602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.462384602
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.210761466
Short name T638
Test name
Test status
Simulation time 111613655062 ps
CPU time 1401.6 seconds
Started Sep 01 05:55:17 PM UTC 24
Finished Sep 01 06:18:56 PM UTC 24
Peak memory 295740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210761466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.210761466
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.2480725960
Short name T566
Test name
Test status
Simulation time 34688730564 ps
CPU time 444.77 seconds
Started Sep 01 05:54:46 PM UTC 24
Finished Sep 01 06:02:17 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480725960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2480725960
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.3737044050
Short name T542
Test name
Test status
Simulation time 1496435698 ps
CPU time 97.96 seconds
Started Sep 01 05:53:47 PM UTC 24
Finished Sep 01 05:55:27 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737044050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3737044050
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.3919401619
Short name T307
Test name
Test status
Simulation time 458617528 ps
CPU time 19.96 seconds
Started Sep 01 05:53:50 PM UTC 24
Finished Sep 01 05:54:12 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919401619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3919401619
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.558882634
Short name T541
Test name
Test status
Simulation time 3702999139 ps
CPU time 55 seconds
Started Sep 01 05:54:19 PM UTC 24
Finished Sep 01 05:55:16 PM UTC 24
Peak memory 269144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558882634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.558882634
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.139657610
Short name T538
Test name
Test status
Simulation time 141210890 ps
CPU time 26.2 seconds
Started Sep 01 05:53:31 PM UTC 24
Finished Sep 01 05:53:59 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139657610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.139657610
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.1800918389
Short name T163
Test name
Test status
Simulation time 42896621868 ps
CPU time 3240.2 seconds
Started Sep 01 05:55:28 PM UTC 24
Finished Sep 01 06:50:08 PM UTC 24
Peak memory 302552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800918389 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.1800918389
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all_with_rand_reset.1737435298
Short name T303
Test name
Test status
Simulation time 10720012629 ps
CPU time 483.34 seconds
Started Sep 01 05:56:01 PM UTC 24
Finished Sep 01 06:04:11 PM UTC 24
Peak memory 281788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1737435298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.a
lert_handler_stress_all_with_rand_reset.1737435298
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.2921943309
Short name T548
Test name
Test status
Simulation time 402692961 ps
CPU time 21.55 seconds
Started Sep 01 05:58:03 PM UTC 24
Finished Sep 01 05:58:26 PM UTC 24
Peak memory 267064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921943309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2921943309
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.4012438907
Short name T549
Test name
Test status
Simulation time 1708254629 ps
CPU time 79.25 seconds
Started Sep 01 05:57:22 PM UTC 24
Finished Sep 01 05:58:43 PM UTC 24
Peak memory 262924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012438907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.4012438907
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.1575116665
Short name T399
Test name
Test status
Simulation time 90793624959 ps
CPU time 3172.92 seconds
Started Sep 01 05:58:25 PM UTC 24
Finished Sep 01 06:51:56 PM UTC 24
Peak memory 300584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575116665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1575116665
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.1836349328
Short name T656
Test name
Test status
Simulation time 94909589478 ps
CPU time 1541.83 seconds
Started Sep 01 05:58:26 PM UTC 24
Finished Sep 01 06:24:28 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836349328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1836349328
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.746945069
Short name T553
Test name
Test status
Simulation time 8750756583 ps
CPU time 99.65 seconds
Started Sep 01 05:58:23 PM UTC 24
Finished Sep 01 06:00:05 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746945069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.746945069
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.1697874970
Short name T547
Test name
Test status
Simulation time 3453736122 ps
CPU time 87.53 seconds
Started Sep 01 05:56:54 PM UTC 24
Finished Sep 01 05:58:24 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697874970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1697874970
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.468509708
Short name T545
Test name
Test status
Simulation time 1390737299 ps
CPU time 62.27 seconds
Started Sep 01 05:57:04 PM UTC 24
Finished Sep 01 05:58:09 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468509708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.468509708
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.266716510
Short name T546
Test name
Test status
Simulation time 407882657 ps
CPU time 11.21 seconds
Started Sep 01 05:58:10 PM UTC 24
Finished Sep 01 05:58:22 PM UTC 24
Peak memory 264988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266716510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.266716510
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.1704618062
Short name T543
Test name
Test status
Simulation time 632551679 ps
CPU time 12.73 seconds
Started Sep 01 05:56:39 PM UTC 24
Finished Sep 01 05:56:53 PM UTC 24
Peak memory 264952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704618062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1704618062
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all_with_rand_reset.3452707236
Short name T556
Test name
Test status
Simulation time 3033131793 ps
CPU time 117.09 seconds
Started Sep 01 05:58:44 PM UTC 24
Finished Sep 01 06:00:43 PM UTC 24
Peak memory 279476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3452707236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.a
lert_handler_stress_all_with_rand_reset.3452707236
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.4205250898
Short name T665
Test name
Test status
Simulation time 123710123629 ps
CPU time 1591.52 seconds
Started Sep 01 06:00:38 PM UTC 24
Finished Sep 01 06:27:30 PM UTC 24
Peak memory 295736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205250898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.4205250898
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.1242503021
Short name T563
Test name
Test status
Simulation time 1396522625 ps
CPU time 96.74 seconds
Started Sep 01 06:00:06 PM UTC 24
Finished Sep 01 06:01:44 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242503021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1242503021
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.1144890729
Short name T559
Test name
Test status
Simulation time 1049957053 ps
CPU time 52.67 seconds
Started Sep 01 06:00:03 PM UTC 24
Finished Sep 01 06:00:59 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144890729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1144890729
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.164582726
Short name T679
Test name
Test status
Simulation time 75924048257 ps
CPU time 1966.17 seconds
Started Sep 01 06:00:44 PM UTC 24
Finished Sep 01 06:33:56 PM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164582726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.164582726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.1241832072
Short name T699
Test name
Test status
Simulation time 54623710308 ps
CPU time 3220.49 seconds
Started Sep 01 06:00:52 PM UTC 24
Finished Sep 01 06:55:08 PM UTC 24
Peak memory 304940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241832072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1241832072
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.2795993125
Short name T573
Test name
Test status
Simulation time 104126047392 ps
CPU time 194.51 seconds
Started Sep 01 06:00:41 PM UTC 24
Finished Sep 01 06:03:59 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795993125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2795993125
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.1587598453
Short name T555
Test name
Test status
Simulation time 515190900 ps
CPU time 51.66 seconds
Started Sep 01 05:59:47 PM UTC 24
Finished Sep 01 06:00:40 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587598453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1587598453
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.4292184669
Short name T558
Test name
Test status
Simulation time 871646418 ps
CPU time 61.99 seconds
Started Sep 01 05:59:54 PM UTC 24
Finished Sep 01 06:00:57 PM UTC 24
Peak memory 262920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292184669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.4292184669
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.2211791275
Short name T561
Test name
Test status
Simulation time 210862367 ps
CPU time 32.27 seconds
Started Sep 01 06:00:37 PM UTC 24
Finished Sep 01 06:01:11 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211791275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2211791275
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.3058826307
Short name T554
Test name
Test status
Simulation time 4327524910 ps
CPU time 82.66 seconds
Started Sep 01 05:59:10 PM UTC 24
Finished Sep 01 06:00:35 PM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058826307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3058826307
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/36.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.2843110195
Short name T683
Test name
Test status
Simulation time 66161013878 ps
CPU time 2154.4 seconds
Started Sep 01 06:02:01 PM UTC 24
Finished Sep 01 06:38:20 PM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843110195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2843110195
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.2062164435
Short name T569
Test name
Test status
Simulation time 3671120679 ps
CPU time 85.35 seconds
Started Sep 01 06:01:46 PM UTC 24
Finished Sep 01 06:03:13 PM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062164435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2062164435
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.858941238
Short name T567
Test name
Test status
Simulation time 2372826408 ps
CPU time 55.23 seconds
Started Sep 01 06:01:27 PM UTC 24
Finished Sep 01 06:02:24 PM UTC 24
Peak memory 263296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858941238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.858941238
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.1348762309
Short name T124
Test name
Test status
Simulation time 17446127787 ps
CPU time 1946.78 seconds
Started Sep 01 06:02:25 PM UTC 24
Finished Sep 01 06:35:16 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348762309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1348762309
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.4186848126
Short name T677
Test name
Test status
Simulation time 467001743554 ps
CPU time 1824.83 seconds
Started Sep 01 06:02:29 PM UTC 24
Finished Sep 01 06:33:15 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186848126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4186848126
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.560283186
Short name T564
Test name
Test status
Simulation time 1449159209 ps
CPU time 37.28 seconds
Started Sep 01 06:01:12 PM UTC 24
Finished Sep 01 06:01:51 PM UTC 24
Peak memory 262940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560283186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.560283186
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.8224148
Short name T568
Test name
Test status
Simulation time 2797962635 ps
CPU time 66.61 seconds
Started Sep 01 06:01:23 PM UTC 24
Finished Sep 01 06:02:32 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8224148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_rand
om_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.8224148
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.226309915
Short name T326
Test name
Test status
Simulation time 1491049159 ps
CPU time 69.21 seconds
Started Sep 01 06:01:52 PM UTC 24
Finished Sep 01 06:03:03 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226309915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.226309915
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.3108155431
Short name T562
Test name
Test status
Simulation time 800782638 ps
CPU time 21.09 seconds
Started Sep 01 06:01:03 PM UTC 24
Finished Sep 01 06:01:26 PM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108155431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3108155431
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all_with_rand_reset.1286108807
Short name T614
Test name
Test status
Simulation time 23184606909 ps
CPU time 769.91 seconds
Started Sep 01 06:02:38 PM UTC 24
Finished Sep 01 06:15:38 PM UTC 24
Peak memory 295932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1286108807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.a
lert_handler_stress_all_with_rand_reset.1286108807
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.2353496574
Short name T690
Test name
Test status
Simulation time 175547635011 ps
CPU time 2527.17 seconds
Started Sep 01 06:03:59 PM UTC 24
Finished Sep 01 06:46:38 PM UTC 24
Peak memory 304676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353496574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2353496574
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.1126691164
Short name T598
Test name
Test status
Simulation time 5515401045 ps
CPU time 487.64 seconds
Started Sep 01 06:03:27 PM UTC 24
Finished Sep 01 06:11:42 PM UTC 24
Peak memory 269176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126691164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1126691164
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.804641519
Short name T572
Test name
Test status
Simulation time 138882432 ps
CPU time 21.64 seconds
Started Sep 01 06:03:23 PM UTC 24
Finished Sep 01 06:03:46 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804641519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.804641519
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.462960974
Short name T697
Test name
Test status
Simulation time 648299438544 ps
CPU time 2855.33 seconds
Started Sep 01 06:04:13 PM UTC 24
Finished Sep 01 06:52:22 PM UTC 24
Peak memory 286176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462960974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.462960974
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.3797342886
Short name T681
Test name
Test status
Simulation time 28854990238 ps
CPU time 1895.77 seconds
Started Sep 01 06:05:03 PM UTC 24
Finished Sep 01 06:37:01 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797342886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3797342886
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.2220184266
Short name T594
Test name
Test status
Simulation time 27940296193 ps
CPU time 372.75 seconds
Started Sep 01 06:04:11 PM UTC 24
Finished Sep 01 06:10:30 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220184266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2220184266
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.423883021
Short name T571
Test name
Test status
Simulation time 109357007 ps
CPU time 11.62 seconds
Started Sep 01 06:03:14 PM UTC 24
Finished Sep 01 06:03:26 PM UTC 24
Peak memory 265380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423883021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.423883021
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.1174805502
Short name T574
Test name
Test status
Simulation time 1381050425 ps
CPU time 51.04 seconds
Started Sep 01 06:03:18 PM UTC 24
Finished Sep 01 06:04:10 PM UTC 24
Peak memory 262932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174805502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1174805502
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.3683318000
Short name T570
Test name
Test status
Simulation time 131774479 ps
CPU time 17.04 seconds
Started Sep 01 06:03:04 PM UTC 24
Finished Sep 01 06:03:22 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683318000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3683318000
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.2770516190
Short name T693
Test name
Test status
Simulation time 133768738279 ps
CPU time 2550.99 seconds
Started Sep 01 06:05:04 PM UTC 24
Finished Sep 01 06:48:05 PM UTC 24
Peak memory 301880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770516190 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.2770516190
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all_with_rand_reset.2420566919
Short name T293
Test name
Test status
Simulation time 4753325693 ps
CPU time 442.48 seconds
Started Sep 01 06:05:23 PM UTC 24
Finished Sep 01 06:12:52 PM UTC 24
Peak memory 279804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2420566919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.a
lert_handler_stress_all_with_rand_reset.2420566919
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.2199894012
Short name T670
Test name
Test status
Simulation time 30150749715 ps
CPU time 1374.13 seconds
Started Sep 01 06:06:44 PM UTC 24
Finished Sep 01 06:29:55 PM UTC 24
Peak memory 295808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199894012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2199894012
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.3749225249
Short name T601
Test name
Test status
Simulation time 4242147446 ps
CPU time 327.96 seconds
Started Sep 01 06:06:33 PM UTC 24
Finished Sep 01 06:12:06 PM UTC 24
Peak memory 269368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749225249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3749225249
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.380233167
Short name T579
Test name
Test status
Simulation time 327535653 ps
CPU time 37.47 seconds
Started Sep 01 06:06:30 PM UTC 24
Finished Sep 01 06:07:09 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380233167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.380233167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.1168724483
Short name T650
Test name
Test status
Simulation time 7922350086 ps
CPU time 929.41 seconds
Started Sep 01 06:07:11 PM UTC 24
Finished Sep 01 06:22:52 PM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168724483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1168724483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.3223191573
Short name T612
Test name
Test status
Simulation time 32620518663 ps
CPU time 486.71 seconds
Started Sep 01 06:06:51 PM UTC 24
Finished Sep 01 06:15:05 PM UTC 24
Peak memory 269192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223191573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3223191573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.402830187
Short name T577
Test name
Test status
Simulation time 313624946 ps
CPU time 41.44 seconds
Started Sep 01 06:05:52 PM UTC 24
Finished Sep 01 06:06:35 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402830187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.402830187
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.2071789496
Short name T530
Test name
Test status
Simulation time 3253357935 ps
CPU time 48.57 seconds
Started Sep 01 06:05:53 PM UTC 24
Finished Sep 01 06:06:43 PM UTC 24
Peak memory 262992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071789496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2071789496
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.406245032
Short name T580
Test name
Test status
Simulation time 1387023648 ps
CPU time 32.1 seconds
Started Sep 01 06:06:36 PM UTC 24
Finished Sep 01 06:07:10 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406245032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.406245032
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.326121560
Short name T578
Test name
Test status
Simulation time 861793456 ps
CPU time 79.17 seconds
Started Sep 01 06:05:30 PM UTC 24
Finished Sep 01 06:06:51 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326121560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.326121560
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.862941119
Short name T582
Test name
Test status
Simulation time 495922030 ps
CPU time 23.94 seconds
Started Sep 01 06:07:43 PM UTC 24
Finished Sep 01 06:08:08 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862941119 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.862941119
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.2429809726
Short name T57
Test name
Test status
Simulation time 53704108 ps
CPU time 3.85 seconds
Started Sep 01 04:56:45 PM UTC 24
Finished Sep 01 04:56:50 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429809726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2429809726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.2794039407
Short name T360
Test name
Test status
Simulation time 88467870875 ps
CPU time 1757.79 seconds
Started Sep 01 04:56:36 PM UTC 24
Finished Sep 01 05:26:16 PM UTC 24
Peak memory 288228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794039407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2794039407
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.3706895061
Short name T26
Test name
Test status
Simulation time 15734338372 ps
CPU time 37.71 seconds
Started Sep 01 04:56:43 PM UTC 24
Finished Sep 01 04:57:23 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706895061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3706895061
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.510028602
Short name T284
Test name
Test status
Simulation time 11837310413 ps
CPU time 192.74 seconds
Started Sep 01 04:56:32 PM UTC 24
Finished Sep 01 04:59:48 PM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510028602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.510028602
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.2674824166
Short name T16
Test name
Test status
Simulation time 40174994 ps
CPU time 6.3 seconds
Started Sep 01 04:56:28 PM UTC 24
Finished Sep 01 04:56:35 PM UTC 24
Peak memory 252732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674824166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2674824166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.55893094
Short name T338
Test name
Test status
Simulation time 89540110102 ps
CPU time 1950.92 seconds
Started Sep 01 04:56:38 PM UTC 24
Finished Sep 01 05:29:33 PM UTC 24
Peak memory 288220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55893094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.55893094
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.2731808863
Short name T512
Test name
Test status
Simulation time 39346644180 ps
CPU time 2864.69 seconds
Started Sep 01 04:56:42 PM UTC 24
Finished Sep 01 05:45:02 PM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731808863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2731808863
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.3743093669
Short name T24
Test name
Test status
Simulation time 4695064979 ps
CPU time 220.45 seconds
Started Sep 01 04:56:36 PM UTC 24
Finished Sep 01 05:00:20 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743093669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3743093669
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.703756959
Short name T132
Test name
Test status
Simulation time 4061063202 ps
CPU time 95.14 seconds
Started Sep 01 04:56:26 PM UTC 24
Finished Sep 01 04:58:04 PM UTC 24
Peak memory 269216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703756959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.703756959
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.1726634610
Short name T60
Test name
Test status
Simulation time 387724898 ps
CPU time 44.33 seconds
Started Sep 01 04:56:28 PM UTC 24
Finished Sep 01 04:57:14 PM UTC 24
Peak memory 262916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726634610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1726634610
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.2690497668
Short name T52
Test name
Test status
Simulation time 1873972759 ps
CPU time 68.85 seconds
Started Sep 01 04:56:46 PM UTC 24
Finished Sep 01 04:57:56 PM UTC 24
Peak memory 297292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690497668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2690497668
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.3919857198
Short name T105
Test name
Test status
Simulation time 110048766 ps
CPU time 14.43 seconds
Started Sep 01 04:56:26 PM UTC 24
Finished Sep 01 04:56:43 PM UTC 24
Peak memory 265020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919857198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3919857198
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all_with_rand_reset.721550567
Short name T50
Test name
Test status
Simulation time 5772198770 ps
CPU time 633.19 seconds
Started Sep 01 04:56:46 PM UTC 24
Finished Sep 01 05:07:29 PM UTC 24
Peak memory 283596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=721550567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.ale
rt_handler_stress_all_with_rand_reset.721550567
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.2144086009
Short name T668
Test name
Test status
Simulation time 22069770236 ps
CPU time 1147.35 seconds
Started Sep 01 06:08:52 PM UTC 24
Finished Sep 01 06:28:13 PM UTC 24
Peak memory 299828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144086009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2144086009
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.3516603543
Short name T592
Test name
Test status
Simulation time 2139975394 ps
CPU time 84.09 seconds
Started Sep 01 06:08:40 PM UTC 24
Finished Sep 01 06:10:06 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516603543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3516603543
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.555511347
Short name T593
Test name
Test status
Simulation time 1144992805 ps
CPU time 99.33 seconds
Started Sep 01 06:08:40 PM UTC 24
Finished Sep 01 06:10:21 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555511347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.555511347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.949444223
Short name T402
Test name
Test status
Simulation time 10303363296 ps
CPU time 784.85 seconds
Started Sep 01 06:08:57 PM UTC 24
Finished Sep 01 06:22:11 PM UTC 24
Peak memory 285636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949444223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.949444223
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.1345964562
Short name T684
Test name
Test status
Simulation time 95652945621 ps
CPU time 1815.57 seconds
Started Sep 01 06:09:05 PM UTC 24
Finished Sep 01 06:39:43 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345964562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1345964562
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.3445049357
Short name T371
Test name
Test status
Simulation time 2845312851 ps
CPU time 99.07 seconds
Started Sep 01 06:08:52 PM UTC 24
Finished Sep 01 06:10:33 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445049357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3445049357
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.2963327564
Short name T586
Test name
Test status
Simulation time 374729936 ps
CPU time 50.33 seconds
Started Sep 01 06:08:12 PM UTC 24
Finished Sep 01 06:09:04 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963327564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2963327564
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.3901369450
Short name T585
Test name
Test status
Simulation time 1940022636 ps
CPU time 34.75 seconds
Started Sep 01 06:08:20 PM UTC 24
Finished Sep 01 06:08:56 PM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901369450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3901369450
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.2505541073
Short name T587
Test name
Test status
Simulation time 223746750 ps
CPU time 24.39 seconds
Started Sep 01 06:08:43 PM UTC 24
Finished Sep 01 06:09:09 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505541073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2505541073
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.227860577
Short name T583
Test name
Test status
Simulation time 51086458 ps
CPU time 7.9 seconds
Started Sep 01 06:08:10 PM UTC 24
Finished Sep 01 06:08:19 PM UTC 24
Peak memory 265020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227860577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.227860577
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all_with_rand_reset.2779521853
Short name T629
Test name
Test status
Simulation time 3645701319 ps
CPU time 513.68 seconds
Started Sep 01 06:09:16 PM UTC 24
Finished Sep 01 06:17:57 PM UTC 24
Peak memory 281596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2779521853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.a
lert_handler_stress_all_with_rand_reset.2779521853
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.2934442106
Short name T689
Test name
Test status
Simulation time 125540104663 ps
CPU time 2109.71 seconds
Started Sep 01 06:10:31 PM UTC 24
Finished Sep 01 06:46:04 PM UTC 24
Peak memory 285492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934442106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2934442106
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.1459291981
Short name T607
Test name
Test status
Simulation time 3904551574 ps
CPU time 236.73 seconds
Started Sep 01 06:10:06 PM UTC 24
Finished Sep 01 06:14:07 PM UTC 24
Peak memory 269368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459291981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1459291981
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.3020046836
Short name T596
Test name
Test status
Simulation time 2156119110 ps
CPU time 91.52 seconds
Started Sep 01 06:09:53 PM UTC 24
Finished Sep 01 06:11:27 PM UTC 24
Peak memory 263328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020046836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3020046836
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.1557606115
Short name T702
Test name
Test status
Simulation time 43716142235 ps
CPU time 2705.63 seconds
Started Sep 01 06:10:42 PM UTC 24
Finished Sep 01 06:56:20 PM UTC 24
Peak memory 304680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557606115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1557606115
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.1144326163
Short name T709
Test name
Test status
Simulation time 76297327318 ps
CPU time 3328.26 seconds
Started Sep 01 06:11:09 PM UTC 24
Finished Sep 01 07:07:19 PM UTC 24
Peak memory 304612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144326163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1144326163
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.4145294912
Short name T615
Test name
Test status
Simulation time 6195716127 ps
CPU time 337.1 seconds
Started Sep 01 06:10:34 PM UTC 24
Finished Sep 01 06:16:16 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145294912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.4145294912
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.811707352
Short name T591
Test name
Test status
Simulation time 1749106121 ps
CPU time 24.26 seconds
Started Sep 01 06:09:27 PM UTC 24
Finished Sep 01 06:09:53 PM UTC 24
Peak memory 269036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811707352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.811707352
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.2587331622
Short name T595
Test name
Test status
Simulation time 3423125716 ps
CPU time 67.17 seconds
Started Sep 01 06:09:32 PM UTC 24
Finished Sep 01 06:10:41 PM UTC 24
Peak memory 263068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587331622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2587331622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.518992862
Short name T599
Test name
Test status
Simulation time 2107865736 ps
CPU time 80.53 seconds
Started Sep 01 06:10:23 PM UTC 24
Finished Sep 01 06:11:45 PM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518992862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.518992862
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.1722544050
Short name T589
Test name
Test status
Simulation time 154057156 ps
CPU time 9.6 seconds
Started Sep 01 06:09:16 PM UTC 24
Finished Sep 01 06:09:27 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722544050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1722544050
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/41.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.539642409
Short name T708
Test name
Test status
Simulation time 172758116057 ps
CPU time 3109.22 seconds
Started Sep 01 06:12:26 PM UTC 24
Finished Sep 01 07:04:54 PM UTC 24
Peak memory 305000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539642409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.539642409
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.2308049772
Short name T618
Test name
Test status
Simulation time 15199005072 ps
CPU time 258.63 seconds
Started Sep 01 06:12:11 PM UTC 24
Finished Sep 01 06:16:33 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308049772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2308049772
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.1406311117
Short name T605
Test name
Test status
Simulation time 332911940 ps
CPU time 41.36 seconds
Started Sep 01 06:12:07 PM UTC 24
Finished Sep 01 06:12:50 PM UTC 24
Peak memory 263072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406311117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1406311117
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.2016233550
Short name T401
Test name
Test status
Simulation time 39365975018 ps
CPU time 1293.65 seconds
Started Sep 01 06:12:50 PM UTC 24
Finished Sep 01 06:34:40 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016233550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2016233550
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.3362023250
Short name T686
Test name
Test status
Simulation time 89580241369 ps
CPU time 1781.78 seconds
Started Sep 01 06:12:51 PM UTC 24
Finished Sep 01 06:42:55 PM UTC 24
Peak memory 285896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362023250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3362023250
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.3120606192
Short name T648
Test name
Test status
Simulation time 18220038271 ps
CPU time 575.15 seconds
Started Sep 01 06:12:46 PM UTC 24
Finished Sep 01 06:22:29 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120606192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3120606192
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.3685011638
Short name T602
Test name
Test status
Simulation time 733385787 ps
CPU time 36.36 seconds
Started Sep 01 06:11:47 PM UTC 24
Finished Sep 01 06:12:24 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685011638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3685011638
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.41589203
Short name T604
Test name
Test status
Simulation time 3152315311 ps
CPU time 40.77 seconds
Started Sep 01 06:12:07 PM UTC 24
Finished Sep 01 06:12:49 PM UTC 24
Peak memory 263288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41589203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran
dom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.41589203
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.1660421965
Short name T603
Test name
Test status
Simulation time 1319216536 ps
CPU time 30.48 seconds
Started Sep 01 06:12:13 PM UTC 24
Finished Sep 01 06:12:45 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660421965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1660421965
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.2508482501
Short name T600
Test name
Test status
Simulation time 210786020 ps
CPU time 21.57 seconds
Started Sep 01 06:11:43 PM UTC 24
Finished Sep 01 06:12:05 PM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508482501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2508482501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.3777881135
Short name T321
Test name
Test status
Simulation time 1122752966931 ps
CPU time 3125.78 seconds
Started Sep 01 06:12:53 PM UTC 24
Finished Sep 01 07:05:34 PM UTC 24
Peak memory 304672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777881135 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.3777881135
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/42.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.377685852
Short name T687
Test name
Test status
Simulation time 27807280482 ps
CPU time 1696.37 seconds
Started Sep 01 06:15:05 PM UTC 24
Finished Sep 01 06:43:41 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377685852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.377685852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.2420133089
Short name T616
Test name
Test status
Simulation time 1609621547 ps
CPU time 98.02 seconds
Started Sep 01 06:14:44 PM UTC 24
Finished Sep 01 06:16:24 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420133089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2420133089
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.1018545156
Short name T611
Test name
Test status
Simulation time 2888082821 ps
CPU time 41 seconds
Started Sep 01 06:14:21 PM UTC 24
Finished Sep 01 06:15:04 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018545156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1018545156
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.436725365
Short name T706
Test name
Test status
Simulation time 34596657123 ps
CPU time 2671.25 seconds
Started Sep 01 06:15:40 PM UTC 24
Finished Sep 01 07:00:44 PM UTC 24
Peak memory 297308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436725365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.436725365
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.3420722984
Short name T628
Test name
Test status
Simulation time 5210303028 ps
CPU time 161.05 seconds
Started Sep 01 06:15:06 PM UTC 24
Finished Sep 01 06:17:50 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420722984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3420722984
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.55053189
Short name T609
Test name
Test status
Simulation time 1528864095 ps
CPU time 34.9 seconds
Started Sep 01 06:14:06 PM UTC 24
Finished Sep 01 06:14:43 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55053189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran
dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.55053189
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.4215966546
Short name T613
Test name
Test status
Simulation time 7187277033 ps
CPU time 78.59 seconds
Started Sep 01 06:14:08 PM UTC 24
Finished Sep 01 06:15:29 PM UTC 24
Peak memory 262964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215966546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4215966546
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.1502550567
Short name T617
Test name
Test status
Simulation time 1045445887 ps
CPU time 98.15 seconds
Started Sep 01 06:14:47 PM UTC 24
Finished Sep 01 06:16:27 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502550567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1502550567
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.3304461435
Short name T608
Test name
Test status
Simulation time 6516079490 ps
CPU time 61.64 seconds
Started Sep 01 06:13:17 PM UTC 24
Finished Sep 01 06:14:20 PM UTC 24
Peak memory 263296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304461435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3304461435
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.843283416
Short name T676
Test name
Test status
Simulation time 152809857129 ps
CPU time 955.83 seconds
Started Sep 01 06:16:17 PM UTC 24
Finished Sep 01 06:32:24 PM UTC 24
Peak memory 279420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843283416 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.843283416
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all_with_rand_reset.4023620622
Short name T652
Test name
Test status
Simulation time 6280840058 ps
CPU time 420.03 seconds
Started Sep 01 06:16:25 PM UTC 24
Finished Sep 01 06:23:31 PM UTC 24
Peak memory 281852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4023620622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.a
lert_handler_stress_all_with_rand_reset.4023620622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.2159035290
Short name T704
Test name
Test status
Simulation time 76650792988 ps
CPU time 2553.5 seconds
Started Sep 01 06:17:14 PM UTC 24
Finished Sep 01 07:00:18 PM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159035290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2159035290
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.936799599
Short name T626
Test name
Test status
Simulation time 374707098 ps
CPU time 47.46 seconds
Started Sep 01 06:16:50 PM UTC 24
Finished Sep 01 06:17:39 PM UTC 24
Peak memory 269468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936799599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.936799599
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.884224838
Short name T623
Test name
Test status
Simulation time 2905861101 ps
CPU time 48.01 seconds
Started Sep 01 06:16:39 PM UTC 24
Finished Sep 01 06:17:29 PM UTC 24
Peak memory 263072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884224838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.884224838
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.1540335162
Short name T703
Test name
Test status
Simulation time 106639041996 ps
CPU time 2333.59 seconds
Started Sep 01 06:17:39 PM UTC 24
Finished Sep 01 06:57:01 PM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540335162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1540335162
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.1101442402
Short name T694
Test name
Test status
Simulation time 72773669351 ps
CPU time 1881.45 seconds
Started Sep 01 06:17:39 PM UTC 24
Finished Sep 01 06:49:22 PM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101442402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1101442402
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.2466745684
Short name T383
Test name
Test status
Simulation time 11074188157 ps
CPU time 470.12 seconds
Started Sep 01 06:17:30 PM UTC 24
Finished Sep 01 06:25:26 PM UTC 24
Peak memory 269256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466745684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2466745684
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.3040062346
Short name T624
Test name
Test status
Simulation time 855532347 ps
CPU time 63.78 seconds
Started Sep 01 06:16:33 PM UTC 24
Finished Sep 01 06:17:38 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040062346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3040062346
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.3239611997
Short name T620
Test name
Test status
Simulation time 413783356 ps
CPU time 14.41 seconds
Started Sep 01 06:16:34 PM UTC 24
Finished Sep 01 06:16:49 PM UTC 24
Peak memory 269404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239611997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3239611997
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.2853628068
Short name T622
Test name
Test status
Simulation time 1723501610 ps
CPU time 15.25 seconds
Started Sep 01 06:16:56 PM UTC 24
Finished Sep 01 06:17:13 PM UTC 24
Peak memory 266996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853628068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2853628068
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.2507869312
Short name T625
Test name
Test status
Simulation time 740854313 ps
CPU time 68.08 seconds
Started Sep 01 06:16:28 PM UTC 24
Finished Sep 01 06:17:38 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507869312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2507869312
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.1615913787
Short name T696
Test name
Test status
Simulation time 398453455543 ps
CPU time 2009.3 seconds
Started Sep 01 06:17:40 PM UTC 24
Finished Sep 01 06:51:33 PM UTC 24
Peak memory 296060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615913787 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.1615913787
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all_with_rand_reset.1912134976
Short name T269
Test name
Test status
Simulation time 21514405963 ps
CPU time 441.23 seconds
Started Sep 01 06:17:44 PM UTC 24
Finished Sep 01 06:25:12 PM UTC 24
Peak memory 279548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1912134976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.a
lert_handler_stress_all_with_rand_reset.1912134976
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.1725954715
Short name T294
Test name
Test status
Simulation time 20474266501 ps
CPU time 1679.7 seconds
Started Sep 01 06:18:18 PM UTC 24
Finished Sep 01 06:46:38 PM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725954715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1725954715
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.2600392551
Short name T641
Test name
Test status
Simulation time 2551684003 ps
CPU time 84.99 seconds
Started Sep 01 06:18:06 PM UTC 24
Finished Sep 01 06:19:32 PM UTC 24
Peak memory 263032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600392551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2600392551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.1737381440
Short name T633
Test name
Test status
Simulation time 607493725 ps
CPU time 14.28 seconds
Started Sep 01 06:18:02 PM UTC 24
Finished Sep 01 06:18:17 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737381440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1737381440
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.3973814287
Short name T673
Test name
Test status
Simulation time 7984366305 ps
CPU time 709.57 seconds
Started Sep 01 06:18:26 PM UTC 24
Finished Sep 01 06:30:25 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973814287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3973814287
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.2291594605
Short name T698
Test name
Test status
Simulation time 131152446594 ps
CPU time 2053.25 seconds
Started Sep 01 06:18:27 PM UTC 24
Finished Sep 01 06:53:05 PM UTC 24
Peak memory 295740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291594605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2291594605
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.4079123764
Short name T669
Test name
Test status
Simulation time 117862017696 ps
CPU time 587.27 seconds
Started Sep 01 06:18:19 PM UTC 24
Finished Sep 01 06:28:14 PM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079123764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.4079123764
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.1922458113
Short name T635
Test name
Test status
Simulation time 1636172513 ps
CPU time 34.55 seconds
Started Sep 01 06:17:51 PM UTC 24
Finished Sep 01 06:18:27 PM UTC 24
Peak memory 269244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922458113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1922458113
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.2603412006
Short name T634
Test name
Test status
Simulation time 498861267 ps
CPU time 25.55 seconds
Started Sep 01 06:17:58 PM UTC 24
Finished Sep 01 06:18:25 PM UTC 24
Peak memory 262932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603412006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2603412006
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.1099397160
Short name T636
Test name
Test status
Simulation time 368493311 ps
CPU time 32.01 seconds
Started Sep 01 06:18:06 PM UTC 24
Finished Sep 01 06:18:39 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099397160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1099397160
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.1293518758
Short name T639
Test name
Test status
Simulation time 2997425773 ps
CPU time 68.98 seconds
Started Sep 01 06:17:47 PM UTC 24
Finished Sep 01 06:18:57 PM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293518758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1293518758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.335649920
Short name T329
Test name
Test status
Simulation time 3822666568 ps
CPU time 282.34 seconds
Started Sep 01 06:18:39 PM UTC 24
Finished Sep 01 06:23:26 PM UTC 24
Peak memory 265012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335649920 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.335649920
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.3881430282
Short name T678
Test name
Test status
Simulation time 92338045456 ps
CPU time 837.02 seconds
Started Sep 01 06:19:48 PM UTC 24
Finished Sep 01 06:33:56 PM UTC 24
Peak memory 285492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881430282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3881430282
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.1018899883
Short name T647
Test name
Test status
Simulation time 1830792730 ps
CPU time 166.13 seconds
Started Sep 01 06:19:34 PM UTC 24
Finished Sep 01 06:22:23 PM UTC 24
Peak memory 269368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018899883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1018899883
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.2070248405
Short name T643
Test name
Test status
Simulation time 2072106073 ps
CPU time 32.71 seconds
Started Sep 01 06:19:26 PM UTC 24
Finished Sep 01 06:20:00 PM UTC 24
Peak memory 269060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070248405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2070248405
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.2462699289
Short name T151
Test name
Test status
Simulation time 15419770245 ps
CPU time 1542.56 seconds
Started Sep 01 06:20:04 PM UTC 24
Finished Sep 01 06:46:06 PM UTC 24
Peak memory 301956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462699289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2462699289
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.1979551136
Short name T713
Test name
Test status
Simulation time 49059419817 ps
CPU time 3208.02 seconds
Started Sep 01 06:20:21 PM UTC 24
Finished Sep 01 07:14:27 PM UTC 24
Peak memory 298464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979551136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1979551136
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.3211884731
Short name T659
Test name
Test status
Simulation time 10777324294 ps
CPU time 341.18 seconds
Started Sep 01 06:20:01 PM UTC 24
Finished Sep 01 06:25:47 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211884731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3211884731
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.141062651
Short name T644
Test name
Test status
Simulation time 1043848044 ps
CPU time 61.73 seconds
Started Sep 01 06:19:00 PM UTC 24
Finished Sep 01 06:20:03 PM UTC 24
Peak memory 269156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141062651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.141062651
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.950374209
Short name T645
Test name
Test status
Simulation time 6794147968 ps
CPU time 87.77 seconds
Started Sep 01 06:19:00 PM UTC 24
Finished Sep 01 06:20:30 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950374209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.950374209
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.1799393125
Short name T330
Test name
Test status
Simulation time 1211256305 ps
CPU time 34.31 seconds
Started Sep 01 06:19:44 PM UTC 24
Finished Sep 01 06:20:20 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799393125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1799393125
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.1389491582
Short name T642
Test name
Test status
Simulation time 856098240 ps
CPU time 47.45 seconds
Started Sep 01 06:18:59 PM UTC 24
Finished Sep 01 06:19:48 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389491582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1389491582
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.2845228403
Short name T682
Test name
Test status
Simulation time 9361032528 ps
CPU time 1043.34 seconds
Started Sep 01 06:20:31 PM UTC 24
Finished Sep 01 06:38:07 PM UTC 24
Peak memory 285492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845228403 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.2845228403
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/46.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.3905478341
Short name T700
Test name
Test status
Simulation time 25629909309 ps
CPU time 1940.76 seconds
Started Sep 01 06:22:51 PM UTC 24
Finished Sep 01 06:55:37 PM UTC 24
Peak memory 285568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905478341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3905478341
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.183397386
Short name T654
Test name
Test status
Simulation time 956348516 ps
CPU time 81.86 seconds
Started Sep 01 06:22:30 PM UTC 24
Finished Sep 01 06:23:54 PM UTC 24
Peak memory 269404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183397386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.183397386
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.2510232654
Short name T651
Test name
Test status
Simulation time 702537332 ps
CPU time 63.73 seconds
Started Sep 01 06:22:24 PM UTC 24
Finished Sep 01 06:23:30 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510232654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2510232654
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.797216506
Short name T701
Test name
Test status
Simulation time 159406966445 ps
CPU time 1953.29 seconds
Started Sep 01 06:22:54 PM UTC 24
Finished Sep 01 06:55:51 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797216506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.797216506
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.1482275944
Short name T695
Test name
Test status
Simulation time 86455251588 ps
CPU time 1553.22 seconds
Started Sep 01 06:23:27 PM UTC 24
Finished Sep 01 06:49:40 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482275944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1482275944
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.3770237280
Short name T662
Test name
Test status
Simulation time 13060810856 ps
CPU time 217.53 seconds
Started Sep 01 06:22:54 PM UTC 24
Finished Sep 01 06:26:36 PM UTC 24
Peak memory 267068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770237280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3770237280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.2763250484
Short name T646
Test name
Test status
Simulation time 38678420 ps
CPU time 4.59 seconds
Started Sep 01 06:22:14 PM UTC 24
Finished Sep 01 06:22:19 PM UTC 24
Peak memory 265020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763250484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2763250484
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.3820154696
Short name T41
Test name
Test status
Simulation time 1063080138 ps
CPU time 29.62 seconds
Started Sep 01 06:22:20 PM UTC 24
Finished Sep 01 06:22:51 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820154696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3820154696
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.77723979
Short name T653
Test name
Test status
Simulation time 451045308 ps
CPU time 46.37 seconds
Started Sep 01 06:22:48 PM UTC 24
Finished Sep 01 06:23:37 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77723979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig
_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.77723979
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.2069227449
Short name T649
Test name
Test status
Simulation time 4702843280 ps
CPU time 110.1 seconds
Started Sep 01 06:20:55 PM UTC 24
Finished Sep 01 06:22:48 PM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069227449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2069227449
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/47.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.3519708783
Short name T705
Test name
Test status
Simulation time 24747604854 ps
CPU time 2111.73 seconds
Started Sep 01 06:24:49 PM UTC 24
Finished Sep 01 07:00:27 PM UTC 24
Peak memory 285568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519708783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3519708783
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.3341299912
Short name T666
Test name
Test status
Simulation time 3687641871 ps
CPU time 205.71 seconds
Started Sep 01 06:24:29 PM UTC 24
Finished Sep 01 06:27:59 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341299912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3341299912
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.146558280
Short name T660
Test name
Test status
Simulation time 11103178899 ps
CPU time 100.49 seconds
Started Sep 01 06:24:26 PM UTC 24
Finished Sep 01 06:26:09 PM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146558280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.146558280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.536252111
Short name T707
Test name
Test status
Simulation time 140862716563 ps
CPU time 2242.54 seconds
Started Sep 01 06:25:09 PM UTC 24
Finished Sep 01 07:02:58 PM UTC 24
Peak memory 285896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536252111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.536252111
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.1853895447
Short name T710
Test name
Test status
Simulation time 37162141188 ps
CPU time 2643.23 seconds
Started Sep 01 06:25:13 PM UTC 24
Finished Sep 01 07:09:49 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853895447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1853895447
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.3600073030
Short name T671
Test name
Test status
Simulation time 31313566429 ps
CPU time 309.07 seconds
Started Sep 01 06:24:58 PM UTC 24
Finished Sep 01 06:30:11 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600073030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3600073030
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.3184141343
Short name T658
Test name
Test status
Simulation time 798931844 ps
CPU time 70.45 seconds
Started Sep 01 06:23:55 PM UTC 24
Finished Sep 01 06:25:08 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184141343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3184141343
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.1649740932
Short name T657
Test name
Test status
Simulation time 561412764 ps
CPU time 19.11 seconds
Started Sep 01 06:24:13 PM UTC 24
Finished Sep 01 06:24:34 PM UTC 24
Peak memory 263260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649740932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1649740932
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.2750193832
Short name T287
Test name
Test status
Simulation time 662127930 ps
CPU time 60.14 seconds
Started Sep 01 06:24:34 PM UTC 24
Finished Sep 01 06:25:36 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750193832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2750193832
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.909222639
Short name T655
Test name
Test status
Simulation time 414429085 ps
CPU time 45.59 seconds
Started Sep 01 06:23:38 PM UTC 24
Finished Sep 01 06:24:25 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909222639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.909222639
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.2677919024
Short name T714
Test name
Test status
Simulation time 44502900892 ps
CPU time 3077.83 seconds
Started Sep 01 06:25:26 PM UTC 24
Finished Sep 01 07:17:20 PM UTC 24
Peak memory 321056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677919024 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.2677919024
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all_with_rand_reset.3270419096
Short name T270
Test name
Test status
Simulation time 2119811470 ps
CPU time 188.57 seconds
Started Sep 01 06:25:38 PM UTC 24
Finished Sep 01 06:28:49 PM UTC 24
Peak memory 283580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3270419096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.a
lert_handler_stress_all_with_rand_reset.3270419096
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.1833589346
Short name T711
Test name
Test status
Simulation time 171337474808 ps
CPU time 2557.94 seconds
Started Sep 01 06:27:32 PM UTC 24
Finished Sep 01 07:10:40 PM UTC 24
Peak memory 288556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833589346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1833589346
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.2256463477
Short name T675
Test name
Test status
Simulation time 17990062764 ps
CPU time 307.03 seconds
Started Sep 01 06:26:51 PM UTC 24
Finished Sep 01 06:32:03 PM UTC 24
Peak memory 269176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256463477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2256463477
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.2272219702
Short name T663
Test name
Test status
Simulation time 142823772 ps
CPU time 13.59 seconds
Started Sep 01 06:26:36 PM UTC 24
Finished Sep 01 06:26:51 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272219702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2272219702
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.2005746556
Short name T366
Test name
Test status
Simulation time 32865173946 ps
CPU time 377.74 seconds
Started Sep 01 06:27:40 PM UTC 24
Finished Sep 01 06:34:03 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005746556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2005746556
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.3997640174
Short name T664
Test name
Test status
Simulation time 476202110 ps
CPU time 42.02 seconds
Started Sep 01 06:26:10 PM UTC 24
Finished Sep 01 06:26:54 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997640174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3997640174
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.2696616223
Short name T667
Test name
Test status
Simulation time 1991125567 ps
CPU time 90.38 seconds
Started Sep 01 06:26:28 PM UTC 24
Finished Sep 01 06:28:01 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696616223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2696616223
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.1140055067
Short name T661
Test name
Test status
Simulation time 471105584 ps
CPU time 37.4 seconds
Started Sep 01 06:25:48 PM UTC 24
Finished Sep 01 06:26:27 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140055067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1140055067
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.792473867
Short name T672
Test name
Test status
Simulation time 1512234360 ps
CPU time 120.29 seconds
Started Sep 01 06:28:16 PM UTC 24
Finished Sep 01 06:30:19 PM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792473867 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.792473867
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.2715522095
Short name T271
Test name
Test status
Simulation time 19180567564 ps
CPU time 207.26 seconds
Started Sep 01 06:28:16 PM UTC 24
Finished Sep 01 06:31:47 PM UTC 24
Peak memory 279804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2715522095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.a
lert_handler_stress_all_with_rand_reset.2715522095
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.2550874864
Short name T135
Test name
Test status
Simulation time 225008522 ps
CPU time 5.65 seconds
Started Sep 01 04:57:23 PM UTC 24
Finished Sep 01 04:57:30 PM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550874864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2550874864
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.975824203
Short name T27
Test name
Test status
Simulation time 155631767 ps
CPU time 16.15 seconds
Started Sep 01 04:57:15 PM UTC 24
Finished Sep 01 04:57:32 PM UTC 24
Peak memory 263236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975824203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.975824203
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.210145060
Short name T161
Test name
Test status
Simulation time 8247094157 ps
CPU time 152.98 seconds
Started Sep 01 04:56:53 PM UTC 24
Finished Sep 01 04:59:29 PM UTC 24
Peak memory 269532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210145060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.210145060
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.118377811
Short name T98
Test name
Test status
Simulation time 3293960995 ps
CPU time 74.01 seconds
Started Sep 01 04:56:52 PM UTC 24
Finished Sep 01 04:58:08 PM UTC 24
Peak memory 262960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118377811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.118377811
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.2452842487
Short name T279
Test name
Test status
Simulation time 22741085434 ps
CPU time 1054.15 seconds
Started Sep 01 04:57:15 PM UTC 24
Finished Sep 01 05:15:02 PM UTC 24
Peak memory 285696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452842487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2452842487
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.3217250346
Short name T283
Test name
Test status
Simulation time 33409514054 ps
CPU time 2044.54 seconds
Started Sep 01 04:57:15 PM UTC 24
Finished Sep 01 05:31:45 PM UTC 24
Peak memory 303424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217250346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3217250346
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.1194090171
Short name T134
Test name
Test status
Simulation time 1867860077 ps
CPU time 36.79 seconds
Started Sep 01 04:56:51 PM UTC 24
Finished Sep 01 04:57:29 PM UTC 24
Peak memory 269240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194090171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1194090171
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.2517451623
Short name T58
Test name
Test status
Simulation time 563204702 ps
CPU time 19.88 seconds
Started Sep 01 04:56:51 PM UTC 24
Finished Sep 01 04:57:12 PM UTC 24
Peak memory 267356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517451623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2517451623
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.2590387675
Short name T59
Test name
Test status
Simulation time 262355321 ps
CPU time 12.66 seconds
Started Sep 01 04:56:59 PM UTC 24
Finished Sep 01 04:57:13 PM UTC 24
Peak memory 262936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590387675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2590387675
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.3097027507
Short name T259
Test name
Test status
Simulation time 8468679574 ps
CPU time 104.63 seconds
Started Sep 01 04:56:50 PM UTC 24
Finished Sep 01 04:58:37 PM UTC 24
Peak memory 269104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097027507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3097027507
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/5.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.1495352752
Short name T126
Test name
Test status
Simulation time 47583416 ps
CPU time 4.39 seconds
Started Sep 01 04:58:09 PM UTC 24
Finished Sep 01 04:58:14 PM UTC 24
Peak memory 263168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495352752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1495352752
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.65085296
Short name T28
Test name
Test status
Simulation time 175392402 ps
CPU time 17.61 seconds
Started Sep 01 04:58:05 PM UTC 24
Finished Sep 01 04:58:24 PM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65085296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h
andler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.65085296
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.2302901207
Short name T144
Test name
Test status
Simulation time 2629696761 ps
CPU time 173.66 seconds
Started Sep 01 04:57:36 PM UTC 24
Finished Sep 01 05:00:33 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302901207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2302901207
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.4067180901
Short name T100
Test name
Test status
Simulation time 552581196 ps
CPU time 58.98 seconds
Started Sep 01 04:57:34 PM UTC 24
Finished Sep 01 04:58:35 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067180901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.4067180901
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.683524373
Short name T335
Test name
Test status
Simulation time 39939110419 ps
CPU time 1662.78 seconds
Started Sep 01 04:57:57 PM UTC 24
Finished Sep 01 05:26:00 PM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683524373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.683524373
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.1209441245
Short name T405
Test name
Test status
Simulation time 221911811956 ps
CPU time 2201.4 seconds
Started Sep 01 04:58:04 PM UTC 24
Finished Sep 01 05:35:11 PM UTC 24
Peak memory 288224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209441245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1209441245
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.1703580502
Short name T22
Test name
Test status
Simulation time 1812193512 ps
CPU time 125.7 seconds
Started Sep 01 04:57:55 PM UTC 24
Finished Sep 01 05:00:03 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703580502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1703580502
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.3808757500
Short name T260
Test name
Test status
Simulation time 4679682944 ps
CPU time 75.54 seconds
Started Sep 01 04:57:31 PM UTC 24
Finished Sep 01 04:58:48 PM UTC 24
Peak memory 269100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808757500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3808757500
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.1671521625
Short name T125
Test name
Test status
Simulation time 83749689 ps
CPU time 17.82 seconds
Started Sep 01 04:57:33 PM UTC 24
Finished Sep 01 04:57:52 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671521625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1671521625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.3785170084
Short name T88
Test name
Test status
Simulation time 3425049474 ps
CPU time 57.22 seconds
Started Sep 01 04:57:30 PM UTC 24
Finished Sep 01 04:58:29 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785170084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3785170084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.3364693264
Short name T248
Test name
Test status
Simulation time 148946737 ps
CPU time 5.99 seconds
Started Sep 01 04:59:07 PM UTC 24
Finished Sep 01 04:59:14 PM UTC 24
Peak memory 263168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364693264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3364693264
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.1824489674
Short name T29
Test name
Test status
Simulation time 467339801 ps
CPU time 15.57 seconds
Started Sep 01 04:58:55 PM UTC 24
Finished Sep 01 04:59:12 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824489674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1824489674
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.3442928084
Short name T345
Test name
Test status
Simulation time 2235661753 ps
CPU time 160.74 seconds
Started Sep 01 04:58:31 PM UTC 24
Finished Sep 01 05:01:14 PM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442928084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3442928084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.240270147
Short name T109
Test name
Test status
Simulation time 833453093 ps
CPU time 81.01 seconds
Started Sep 01 04:58:31 PM UTC 24
Finished Sep 01 04:59:54 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240270147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.240270147
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.222464484
Short name T336
Test name
Test status
Simulation time 66890554181 ps
CPU time 1828.85 seconds
Started Sep 01 04:58:48 PM UTC 24
Finished Sep 01 05:29:39 PM UTC 24
Peak memory 295812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222464484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.222464484
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.217638704
Short name T149
Test name
Test status
Simulation time 77277716495 ps
CPU time 1899.91 seconds
Started Sep 01 04:58:49 PM UTC 24
Finished Sep 01 05:30:53 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217638704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.217638704
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.644054237
Short name T348
Test name
Test status
Simulation time 7015640061 ps
CPU time 150.08 seconds
Started Sep 01 04:58:46 PM UTC 24
Finished Sep 01 05:01:19 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644054237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.644054237
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.507233169
Short name T37
Test name
Test status
Simulation time 620853005 ps
CPU time 81.51 seconds
Started Sep 01 04:58:25 PM UTC 24
Finished Sep 01 04:59:49 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507233169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.507233169
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.1034619503
Short name T89
Test name
Test status
Simulation time 145513924 ps
CPU time 14.48 seconds
Started Sep 01 04:58:29 PM UTC 24
Finished Sep 01 04:58:45 PM UTC 24
Peak memory 262932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034619503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1034619503
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.3981865980
Short name T143
Test name
Test status
Simulation time 155649000 ps
CPU time 10.1 seconds
Started Sep 01 04:58:36 PM UTC 24
Finished Sep 01 04:58:47 PM UTC 24
Peak memory 253024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981865980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3981865980
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.569338474
Short name T108
Test name
Test status
Simulation time 846727654 ps
CPU time 46.54 seconds
Started Sep 01 04:58:18 PM UTC 24
Finished Sep 01 04:59:06 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569338474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.569338474
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.428755155
Short name T63
Test name
Test status
Simulation time 39304163143 ps
CPU time 776 seconds
Started Sep 01 04:59:02 PM UTC 24
Finished Sep 01 05:12:08 PM UTC 24
Peak memory 279684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428755155 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.428755155
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all_with_rand_reset.3426045894
Short name T62
Test name
Test status
Simulation time 4813234451 ps
CPU time 582.38 seconds
Started Sep 01 04:59:13 PM UTC 24
Finished Sep 01 05:09:04 PM UTC 24
Peak memory 285948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3426045894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.al
ert_handler_stress_all_with_rand_reset.3426045894
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.109090595
Short name T249
Test name
Test status
Simulation time 44842316 ps
CPU time 6.79 seconds
Started Sep 01 05:00:21 PM UTC 24
Finished Sep 01 05:00:29 PM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109090595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.109090595
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.1712548731
Short name T138
Test name
Test status
Simulation time 184447633368 ps
CPU time 2412.51 seconds
Started Sep 01 04:59:49 PM UTC 24
Finished Sep 01 05:40:30 PM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712548731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1712548731
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.2818822252
Short name T165
Test name
Test status
Simulation time 2093978455 ps
CPU time 71.85 seconds
Started Sep 01 05:00:08 PM UTC 24
Finished Sep 01 05:01:22 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818822252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2818822252
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.2958003940
Short name T343
Test name
Test status
Simulation time 11936143963 ps
CPU time 204.09 seconds
Started Sep 01 04:59:33 PM UTC 24
Finished Sep 01 05:03:01 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958003940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2958003940
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.2362275685
Short name T102
Test name
Test status
Simulation time 3173324240 ps
CPU time 45.65 seconds
Started Sep 01 04:59:30 PM UTC 24
Finished Sep 01 05:00:18 PM UTC 24
Peak memory 263296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362275685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2362275685
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.3502014446
Short name T339
Test name
Test status
Simulation time 13643439896 ps
CPU time 1349.57 seconds
Started Sep 01 04:59:55 PM UTC 24
Finished Sep 01 05:22:40 PM UTC 24
Peak memory 301888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502014446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3502014446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.4038735755
Short name T550
Test name
Test status
Simulation time 204642107627 ps
CPU time 3500.01 seconds
Started Sep 01 05:00:07 PM UTC 24
Finished Sep 01 05:59:08 PM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038735755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.4038735755
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.2438975484
Short name T263
Test name
Test status
Simulation time 24317345502 ps
CPU time 306.89 seconds
Started Sep 01 04:59:52 PM UTC 24
Finished Sep 01 05:05:03 PM UTC 24
Peak memory 269188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438975484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2438975484
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.3605594093
Short name T91
Test name
Test status
Simulation time 2678070031 ps
CPU time 94.45 seconds
Started Sep 01 04:59:15 PM UTC 24
Finished Sep 01 05:00:53 PM UTC 24
Peak memory 269476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605594093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3605594093
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.3159725903
Short name T101
Test name
Test status
Simulation time 727167872 ps
CPU time 25.99 seconds
Started Sep 01 04:59:24 PM UTC 24
Finished Sep 01 04:59:51 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159725903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3159725903
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.156450450
Short name T90
Test name
Test status
Simulation time 3059002463 ps
CPU time 49.76 seconds
Started Sep 01 04:59:49 PM UTC 24
Finished Sep 01 05:00:41 PM UTC 24
Peak memory 269188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156450450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.156450450
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.732072191
Short name T425
Test name
Test status
Simulation time 1078834765 ps
CPU time 104.37 seconds
Started Sep 01 04:59:13 PM UTC 24
Finished Sep 01 05:01:00 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732072191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.732072191
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.2249516476
Short name T342
Test name
Test status
Simulation time 27204825394 ps
CPU time 1340.64 seconds
Started Sep 01 05:00:18 PM UTC 24
Finished Sep 01 05:22:55 PM UTC 24
Peak memory 285884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249516476 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.2249516476
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/8.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.789061915
Short name T250
Test name
Test status
Simulation time 624954784 ps
CPU time 4.07 seconds
Started Sep 01 05:01:15 PM UTC 24
Finished Sep 01 05:01:20 PM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789061915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.789061915
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.2761627251
Short name T364
Test name
Test status
Simulation time 19468116746 ps
CPU time 1492.47 seconds
Started Sep 01 05:00:55 PM UTC 24
Finished Sep 01 05:26:06 PM UTC 24
Peak memory 279352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761627251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2761627251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.1794274232
Short name T166
Test name
Test status
Simulation time 752603852 ps
CPU time 44.32 seconds
Started Sep 01 05:01:14 PM UTC 24
Finished Sep 01 05:02:00 PM UTC 24
Peak memory 263236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794274232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1794274232
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.3617449453
Short name T281
Test name
Test status
Simulation time 4968059298 ps
CPU time 114.94 seconds
Started Sep 01 05:00:45 PM UTC 24
Finished Sep 01 05:02:42 PM UTC 24
Peak memory 269208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617449453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3617449453
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.3610915146
Short name T424
Test name
Test status
Simulation time 146891114 ps
CPU time 9.03 seconds
Started Sep 01 05:00:43 PM UTC 24
Finished Sep 01 05:00:54 PM UTC 24
Peak memory 252660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610915146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3610915146
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.508563862
Short name T337
Test name
Test status
Simulation time 12864903820 ps
CPU time 1205.54 seconds
Started Sep 01 05:01:10 PM UTC 24
Finished Sep 01 05:21:30 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508563862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.508563862
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.1832040291
Short name T123
Test name
Test status
Simulation time 31406626319 ps
CPU time 2047.23 seconds
Started Sep 01 05:01:13 PM UTC 24
Finished Sep 01 05:35:45 PM UTC 24
Peak memory 301956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832040291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1832040291
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.4099898975
Short name T352
Test name
Test status
Simulation time 28610901337 ps
CPU time 292.09 seconds
Started Sep 01 05:01:01 PM UTC 24
Finished Sep 01 05:05:58 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099898975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4099898975
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.558141280
Short name T44
Test name
Test status
Simulation time 453732386 ps
CPU time 40.64 seconds
Started Sep 01 05:00:34 PM UTC 24
Finished Sep 01 05:01:16 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558141280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.558141280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.803877178
Short name T289
Test name
Test status
Simulation time 383986298 ps
CPU time 52.82 seconds
Started Sep 01 05:00:42 PM UTC 24
Finished Sep 01 05:01:37 PM UTC 24
Peak memory 269368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803877178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.803877178
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.3052803460
Short name T103
Test name
Test status
Simulation time 499233231 ps
CPU time 17.44 seconds
Started Sep 01 05:00:54 PM UTC 24
Finished Sep 01 05:01:13 PM UTC 24
Peak memory 267000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052803460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3052803460
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.3030745590
Short name T426
Test name
Test status
Simulation time 283655359 ps
CPU time 46.34 seconds
Started Sep 01 05:00:31 PM UTC 24
Finished Sep 01 05:01:19 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030745590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3030745590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.3205981248
Short name T429
Test name
Test status
Simulation time 1164879147 ps
CPU time 107.63 seconds
Started Sep 01 05:01:15 PM UTC 24
Finished Sep 01 05:03:05 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205981248 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.3205981248
Directory /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/9.alert_handler_stress_all/latest
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