Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52647532	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24893260

1

T1

484

T2

91

T3

1180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12124514	1			T1	393		T2	15		T3	453
values[0x0]	32651166	1			T1	430		T2	151		T3	1537
values[0x1]	32765112	1			T1	430		T2	160		T3	1519

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45852125	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31688667

1

T1

576

T2

123

T3

1448

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	246761	1			T1	6		T2	1		T12	27
valid_sources[0x01]	219734	1			T12	38		T4	1		T11	46
valid_sources[0x02]	219466	1			T1	6		T2	1		T12	43
valid_sources[0x03]	217996	1			T1	8		T2	1		T12	20
valid_sources[0x04]	615840	1			T1	2		T2	2		T12	28
valid_sources[0x05]	217021	1			T1	8		T2	2		T12	26
valid_sources[0x06]	228049	1			T1	9		T2	3		T12	33
valid_sources[0x07]	220141	1			T1	1		T2	1		T12	21
valid_sources[0x08]	218914	1			T2	1		T12	36		T13	4
valid_sources[0x09]	218246	1			T2	1		T12	29		T4	6
valid_sources[0x0a]	221981	1			T1	7		T2	1		T12	34
valid_sources[0x0b]	215569	1			T1	1		T12	33		T4	4
valid_sources[0x0c]	216053	1			T1	1		T2	2		T12	18
valid_sources[0x0d]	216196	1			T1	4		T2	1		T12	27
valid_sources[0x0e]	757772	1			T1	15		T2	2		T12	35
valid_sources[0x0f]	228534	1			T1	10		T2	1		T12	30
valid_sources[0x10]	217414	1			T1	8		T2	2		T12	35
valid_sources[0x11]	690307	1			T1	9		T2	2		T12	33
valid_sources[0x12]	215470	1			T1	2		T2	2		T12	29
valid_sources[0x13]	218672	1			T1	3		T2	1		T12	41
valid_sources[0x14]	821521	1			T1	1		T2	2		T12	30
valid_sources[0x15]	218032	1			T1	10		T2	2		T12	44
valid_sources[0x16]	595573	1			T1	14		T2	1		T12	27
valid_sources[0x17]	214885	1			T1	1		T2	2		T12	22
valid_sources[0x18]	215196	1			T2	1		T12	23		T13	6
valid_sources[0x19]	227062	1			T1	4		T12	33		T4	2
valid_sources[0x1a]	226582	1			T1	5		T2	3		T12	19
valid_sources[0x1b]	218799	1			T1	5		T12	34		T4	6
valid_sources[0x1c]	219096	1			T1	7		T2	3		T12	22
valid_sources[0x1d]	216690	1			T1	1		T2	1		T12	36
valid_sources[0x1e]	218142	1			T1	7		T2	1		T12	45
valid_sources[0x1f]	219198	1			T1	6		T2	1		T12	37
valid_sources[0x20]	509354	1			T1	6		T2	2		T12	48
valid_sources[0x21]	226983	1			T2	2		T12	26		T13	3
valid_sources[0x22]	260633	1			T12	31		T4	6		T11	26
valid_sources[0x23]	738277	1			T1	6		T2	3		T12	36
valid_sources[0x24]	221137	1			T1	3		T2	1		T12	45
valid_sources[0x25]	216488	1			T1	6		T2	1		T12	36
valid_sources[0x26]	584082	1			T1	7		T2	3		T12	35
valid_sources[0x27]	217187	1			T1	3		T12	24		T4	3
valid_sources[0x28]	226105	1			T1	6		T2	1		T12	43
valid_sources[0x29]	218822	1			T12	37		T4	1		T11	23
valid_sources[0x2a]	215352	1			T1	3		T2	2		T12	38
valid_sources[0x2b]	628786	1			T12	42		T11	57		T22	32
valid_sources[0x2c]	218483	1			T1	17		T2	2		T12	41
valid_sources[0x2d]	215159	1			T1	2		T2	1		T12	26
valid_sources[0x2e]	217487	1			T1	6		T12	45		T13	2
valid_sources[0x2f]	230757	1			T1	6		T12	34		T4	1
valid_sources[0x30]	818448	1			T1	11		T12	18		T13	12
valid_sources[0x31]	223160	1			T12	38		T11	40		T22	37
valid_sources[0x32]	219846	1			T1	6		T2	2		T12	38
valid_sources[0x33]	222454	1			T1	7		T2	1		T10	4634
valid_sources[0x34]	230687	1			T1	3		T2	1		T12	19
valid_sources[0x35]	219089	1			T1	3		T2	1		T12	36
valid_sources[0x36]	222338	1			T1	8		T2	1		T12	40
valid_sources[0x37]	218626	1			T1	11		T2	2		T12	38
valid_sources[0x38]	215411	1			T1	14		T12	34		T4	6
valid_sources[0x39]	216105	1			T2	3		T12	43		T4	3
valid_sources[0x3a]	477993	1			T1	5		T2	4		T12	35
valid_sources[0x3b]	219852	1			T12	22		T13	1		T11	36
valid_sources[0x3c]	217777	1			T1	8		T2	4		T12	43
valid_sources[0x3d]	685637	1			T1	2		T12	32		T4	4
valid_sources[0x3e]	218717	1			T2	1		T12	27		T11	60
valid_sources[0x3f]	216239	1			T1	4		T2	1		T12	32
valid_sources[0x40]	220710	1			T1	13		T2	3		T12	29
valid_sources[0x41]	488442	1			T12	57		T4	4		T13	3
valid_sources[0x42]	218040	1			T12	32		T4	2		T13	2
valid_sources[0x43]	223801	1			T1	5		T2	2		T12	42
valid_sources[0x44]	216331	1			T2	2		T12	25		T4	3
valid_sources[0x45]	217256	1			T2	1		T12	26		T4	1
valid_sources[0x46]	218337	1			T2	1		T12	27		T13	6
valid_sources[0x47]	219577	1			T1	7		T2	5		T12	38
valid_sources[0x48]	682497	1			T2	1		T12	50		T11	49
valid_sources[0x49]	214896	1			T1	7		T2	1		T12	27
valid_sources[0x4a]	221357	1			T1	2		T12	16		T11	15
valid_sources[0x4b]	217697	1			T1	8		T12	23		T13	1
valid_sources[0x4c]	658974	1			T1	9		T12	35		T4	1
valid_sources[0x4d]	459116	1			T1	11		T2	1		T12	28
valid_sources[0x4e]	220707	1			T2	3		T12	23		T13	5
valid_sources[0x4f]	222030	1			T12	51		T4	1		T11	70
valid_sources[0x50]	214913	1			T1	13		T2	2		T12	32
valid_sources[0x51]	245900	1			T1	4		T2	2		T12	45
valid_sources[0x52]	218769	1			T1	6		T2	5		T12	28
valid_sources[0x53]	214049	1			T1	3		T12	34		T4	1
valid_sources[0x54]	230317	1			T1	2		T12	22		T4	1
valid_sources[0x55]	222522	1			T1	1		T12	35		T13	1
valid_sources[0x56]	215281	1			T1	6		T2	2		T12	28
valid_sources[0x57]	220492	1			T1	4		T12	28		T4	14
valid_sources[0x58]	220160	1			T1	2		T2	2		T12	42
valid_sources[0x59]	216911	1			T1	1		T12	23		T4	12
valid_sources[0x5a]	227085	1			T1	1		T2	4		T12	31
valid_sources[0x5b]	237360	1			T1	2		T2	1		T12	54
valid_sources[0x5c]	221728	1			T1	13		T2	4		T12	39
valid_sources[0x5d]	926004	1			T1	9		T2	1		T12	42
valid_sources[0x5e]	215162	1			T1	9		T2	1		T12	40
valid_sources[0x5f]	900143	1			T1	5		T2	2		T12	31
valid_sources[0x60]	217729	1			T1	1		T2	2		T12	39
valid_sources[0x61]	216774	1			T1	6		T2	2		T12	27
valid_sources[0x62]	214779	1			T2	1		T12	39		T4	1
valid_sources[0x63]	215839	1			T1	9		T2	2		T12	33
valid_sources[0x64]	229883	1			T1	3		T12	34		T11	20
valid_sources[0x65]	216933	1			T2	1		T12	27		T11	28
valid_sources[0x66]	223336	1			T1	11		T2	3		T12	44
valid_sources[0x67]	217952	1			T1	2		T2	1		T12	43
valid_sources[0x68]	653283	1			T1	1		T2	2		T12	33
valid_sources[0x69]	218507	1			T12	24		T4	1		T11	11
valid_sources[0x6a]	217018	1			T1	12		T2	1		T12	29
valid_sources[0x6b]	216813	1			T1	3		T2	2		T12	46
valid_sources[0x6c]	705871	1			T2	2		T12	45		T4	7
valid_sources[0x6d]	730923	1			T1	2		T2	2		T12	27
valid_sources[0x6e]	217009	1			T1	13		T2	2		T12	53
valid_sources[0x6f]	217832	1			T1	11		T2	1		T12	29
valid_sources[0x70]	214392	1			T1	11		T2	1		T12	20
valid_sources[0x71]	218562	1			T1	6		T2	1		T12	46
valid_sources[0x72]	218331	1			T1	4		T2	2		T12	27
valid_sources[0x73]	214673	1			T1	3		T12	27		T13	7
valid_sources[0x74]	227535	1			T12	38		T11	13		T22	21
valid_sources[0x75]	594469	1			T1	5		T2	1		T12	26
valid_sources[0x76]	219782	1			T1	2		T12	29		T4	1
valid_sources[0x77]	219189	1			T1	8		T12	25		T4	3
valid_sources[0x78]	216368	1			T1	3		T2	1		T12	35
valid_sources[0x79]	571068	1			T1	3		T12	47		T13	3
valid_sources[0x7a]	220253	1			T1	5		T2	2		T12	39
valid_sources[0x7b]	220652	1			T1	11		T12	34		T13	5
valid_sources[0x7c]	216367	1			T1	6		T12	40		T4	1
valid_sources[0x7d]	224660	1			T1	6		T2	1		T12	31
valid_sources[0x7e]	236136	1			T2	1		T12	39		T4	2
valid_sources[0x7f]	217148	1			T1	2		T2	2		T12	28
valid_sources[0x80]	228605	1			T1	5		T2	2		T12	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5828765

1

T1

214

T2

6

T3

226

values[0x0]

all_enables

biggest_size

12174518

1

T1

175

T2

55

T3

605

values[0x1]

all_enables

biggest_size

6889977

1

T1

95

T2

30

T3

349