Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T43
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14511	0	0
DisabledNoTrigBkwd_A	2147483647	647483	0	0
DisabledNoTrigFwd_A	2147483647	1294057528	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14511	0	0
T2	2896	627	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T7	162529	0	0	0
T9	44448	0	0	0
T10	38690	0	0	0
T11	34998	0	0	0
T12	28995	0	0	0
T13	4211	1067	0	0
T14	29912	0	0	0
T17	24442	0	0	0
T22	66970	0	0	0
T26	63833	0	0	0
T43	3346	549	0	0
T44	37625	0	0	0
T45	71982	0	0	0
T46	3520	552	0	0
T63	0	894	0	0
T69	0	1177	0	0
T85	32231	0	0	0
T105	77804	0	0	0
T106	50782	0	0	0
T222	0	937	0	0
T241	0	1076	0	0
T242	0	615	0	0
T243	0	1061	0	0
T244	0	480	0	0
T245	0	581	0	0
T246	0	441	0	0
T247	0	371	0	0
T248	0	568	0	0
T249	0	1238	0	0
T250	0	202	0	0
T251	0	495	0	0
T252	0	720	0	0
T253	0	860	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	647483	0	0
T1	3677	5	0	0
T2	5792	3	0	0
T3	105720	1	0	0
T4	28134	0	0	0
T5	368768	0	0	0
T6	132195	0	0	0
T7	0	2	0	0
T10	116070	5	0	0
T11	139992	119	0	0
T12	86985	0	0	0
T13	16844	0	0	0
T14	119648	0	0	0
T22	200910	80	0	0
T23	90898	113	0	0
T24	53324	3	0	0
T25	8200	9	0	0
T26	0	45	0	0
T27	0	223	0	0
T28	0	5	0	0
T35	1831	69	0	0
T36	0	413	0	0
T43	0	8	0	0
T44	0	9	0	0
T45	0	34	0	0
T46	0	7	0	0
T47	0	181	0	0
T48	0	74	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1294057528	0	0
T1	14708	11272	0	0
T2	11584	8565	0	0
T3	140960	97946	0	0
T4	37512	16328	0	0
T5	368768	14469	0	0
T10	154760	101970	0	0
T11	139992	59355	0	0
T12	115980	111028	0	0
T13	16844	11323	0	0
T14	119648	90320	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T3 T10 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T3,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T63,T222
1	1	Covered	T1,T3,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T11,T22

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	583104694	3821	0	0
DisabledNoTrigBkwd_A	583104694	163585	0	0
DisabledNoTrigFwd_A	583104694	322458124	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	3821	0	0
T7	162529	0	0	0
T9	44448	0	0	0
T17	24442	0	0	0
T26	63833	0	0	0
T43	3346	549	0	0
T44	37625	0	0	0
T45	71982	0	0	0
T63	0	894	0	0
T85	32231	0	0	0
T105	77804	0	0	0
T106	50782	0	0	0
T222	0	937	0	0
T245	0	581	0	0
T253	0	860	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	163585	0	0
T3	35240	1	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	0	0	0
T11	34998	14	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	80	0	0
T23	45449	113	0	0
T24	0	3	0	0
T26	0	25	0	0
T35	0	58	0	0
T43	0	8	0	0
T44	0	9	0	0
T45	0	34	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	322458124	0	0
T1	3677	2011	0	0
T2	2896	2125	0	0
T3	35240	22083	0	0
T4	9378	2338	0	0
T5	92192	3593	0	0
T10	38690	38605	0	0
T11	34998	5910	0	0
T12	28995	27363	0	0
T13	4211	2795	0	0
T14	29912	29861	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T10,T12
1	1	Covered	T2,T10,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T246,T247
1	1	Covered	T2,T10,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	583104694	1934	0	0
DisabledNoTrigBkwd_A	583104694	138750	0	0
DisabledNoTrigFwd_A	583104694	348458931	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	1934	0	0
T2	2896	627	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	0	0	0
T11	34998	0	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T246	0	441	0	0
T247	0	371	0	0
T251	0	495	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	138750	0	0
T2	2896	3	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T7	0	1	0	0
T10	38690	3	0	0
T11	34998	98	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T26	0	18	0	0
T27	0	9	0	0
T28	0	5	0	0
T36	0	413	0	0
T47	0	181	0	0
T48	0	74	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	348458931	0	0
T1	3677	3621	0	0
T2	2896	2137	0	0
T3	35240	5533	0	0
T4	9378	2354	0	0
T5	92192	3609	0	0
T10	38690	18872	0	0
T11	34998	3096	0	0
T12	28995	27363	0	0
T13	4211	2813	0	0
T14	29912	18725	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T3 T10 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T69,T241
1	1	Covered	T1,T10,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	583104694	6506	0	0
DisabledNoTrigBkwd_A	583104694	177421	0	0
DisabledNoTrigFwd_A	583104694	326018416	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	6506	0	0
T18	63022	0	0	0
T27	103757	0	0	0
T28	73493	0	0	0
T40	17396	0	0	0
T46	3520	552	0	0
T63	3143	0	0	0
T69	0	1177	0	0
T76	159372	0	0	0
T86	88860	0	0	0
T140	12929	0	0	0
T141	8388	0	0	0
T241	0	1076	0	0
T243	0	1061	0	0
T244	0	480	0	0
T249	0	1238	0	0
T250	0	202	0	0
T252	0	720	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	177421	0	0
T1	3677	5	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T7	0	1	0	0
T10	38690	2	0	0
T11	34998	7	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T25	0	9	0	0
T26	0	2	0	0
T27	0	214	0	0
T35	0	11	0	0
T46	0	7	0	0
T76	0	68	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	326018416	0	0
T1	3677	2019	0	0
T2	2896	2146	0	0
T3	35240	35165	0	0
T4	9378	9250	0	0
T5	92192	3624	0	0
T10	38690	5888	0	0
T11	34998	23500	0	0
T12	28995	28939	0	0
T13	4211	2842	0	0
T14	29912	29861	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T3 T10 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T4
1	0	Covered	T1,T10,T12
1	1	Covered	T12,T13,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T242,T248
1	1	Covered	T12,T13,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T11,T25

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	583104694	2250	0	0
DisabledNoTrigBkwd_A	583104694	167727	0	0
DisabledNoTrigFwd_A	583104694	297122057	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	2250	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T11	34998	0	0	0
T13	4211	1067	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T25	8200	0	0	0
T35	1831	0	0	0
T242	0	615	0	0
T248	0	568	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	167727	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T7	0	1	0	0
T11	34998	6	0	0
T13	4211	16	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T25	8200	3	0	0
T27	0	25	0	0
T28	0	23	0	0
T35	1831	0	0	0
T47	0	91	0	0
T66	0	9	0	0
T67	0	470	0	0
T76	0	57	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	297122057	0	0
T1	3677	3621	0	0
T2	2896	2157	0	0
T3	35240	35165	0	0
T4	9378	2386	0	0
T5	92192	3643	0	0
T10	38690	38605	0	0
T11	34998	26849	0	0
T12	28995	27363	0	0
T13	4211	2873	0	0
T14	29912	11873	0	0