Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T2 T3 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T2 T3 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T2 T3 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T12 T14 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T12 T14 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T12 T14 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T12 T14 
172        1/1                    state_d    = Phase0St;
           Tests:       T26 T27 T28 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T26 T27 T28 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T26 T27 T28 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T26 T27 T28 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T12 T14 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T12 T14 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T12 T14 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T12 T14 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T2 T3 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T2 T3 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T2 T3 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T2 T3 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
194        1/1                    state_d = IdleSt;
           Tests:       T29 T30 T31 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T30 T31 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T30 T31 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T2 T3 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T2 T3 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T2 T3 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T2 T3 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
211        1/1                    state_d = IdleSt;
           Tests:       T10 T23 T7 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T23 T7 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T23 T7 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T2 T3 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T2 T3 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T2 T3 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T2 T3 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T2 T3 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
229        1/1                    state_d = IdleSt;
           Tests:       T26 T27 T32 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T26 T27 T32 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T26 T27 T32 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T2 T3 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T2 T3 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T2 T3 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T2 T3 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T2 T3 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
245        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T32 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T34 T32 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T34 T32 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T2 T3 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T2 T3 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T2 T3 
260        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
261        1/1                    state_d = IdleSt;
           Tests:       T23 T35 T26 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T10
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T1,T12,T14
1	1	1	Covered	T1,T12,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T14
0	1	Covered	T26,T27,T36
1	0	Covered	T27,T28,T33

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T12,T14
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T27,T28,T33

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T14
1	0	Covered	T37,T38,T39
1	1	Covered	T26,T27,T36

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T10

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T3,T11,T23

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T23,T24

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T3,T10

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T12,T14

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T12,T14
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T29,T30,T31
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T10,T23,T7
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T26,T27,T32
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T33,T34,T32
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T23,T35,T26
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T12,T14
TimeoutSt->Phase0St	172	Covered	T26,T27,T28

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T30,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T23,T7
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T27,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T34,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T23,T35,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1028	0	0
CheckAccumTrig0_A	2147483647	2236	0	0
CheckAccumTrig1_A	2147483647	94	0	0
CheckClr_A	2147483647	993	0	0
CheckEn_A	2147483647	986100051	0	0
CheckPhase0_A	2147483647	2487	0	0
CheckPhase1_A	2147483647	2435	0	0
CheckPhase2_A	2147483647	2381	0	0
CheckPhase3_A	2147483647	2339	0	0
CheckTimeout0_A	2147483647	3332	0	0
CheckTimeoutSt1_A	2147483647	357444	0	0
CheckTimeoutSt2_A	2147483647	3012	0	0
CheckTimeoutStTrig_A	2147483647	214	0	0
ErrorStAllEscAsserted_A	2147483647	5735	0	0
ErrorStIsTerminal_A	2147483647	4655	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1028	0	0
T6	528780	241	0	0
T7	650116	0	0	0
T8	166184	235	0	0
T9	0	261	0	0
T17	97768	0	0	0
T25	32800	0	0	0
T26	255332	0	0	0
T35	7324	0	0	0
T40	0	100	0	0
T41	0	191	0	0
T42	84608	0	0	0
T43	13384	0	0	0
T44	150500	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2236	0	0
T1	3677	1	0	0
T2	5792	1	0	0
T3	105720	1	0	0
T4	28134	0	0	0
T5	368768	0	0	0
T6	132195	0	0	0
T7	0	2	0	0
T10	116070	3	0	0
T11	139992	3	0	0
T12	86985	0	0	0
T13	16844	0	0	0
T14	119648	0	0	0
T22	200910	1	0	0
T23	90898	3	0	0
T24	53324	1	0	0
T25	8200	1	0	0
T26	0	10	0	0
T27	0	3	0	0
T28	0	1	0	0
T35	1831	2	0	0
T36	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	94	0	0
T15	1777446	0	0	0
T19	152158	0	0	0
T27	103757	1	0	0
T28	146986	1	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	258345	2	0	0
T34	0	1	0	0
T36	109325	0	0	0
T38	0	1	0	0
T41	102147	0	0	0
T47	1118241	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	6286	0	0	0
T64	66846	0	0	0
T65	93906	0	0	0
T66	93670	0	0	0
T67	13189	0	0	0
T68	180914	0	0	0
T69	4695	0	0	0
T70	992580	0	0	0
T71	803956	0	0	0
T72	107071	0	0	0
T73	1257	0	0	0
T74	327360	0	0	0
T75	349097	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	993	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T7	162529	2	0	0
T8	41546	0	0	0
T9	44448	0	0	0
T10	38690	1	0	0
T11	34998	0	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T17	24442	0	0	0
T22	66970	0	0	0
T23	90898	2	0	0
T24	106648	0	0	0
T25	8200	0	0	0
T26	127666	9	0	0
T27	0	10	0	0
T28	0	6	0	0
T33	0	2	0	0
T35	1831	1	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	75250	2	0	0
T50	0	5	0	0
T51	0	3	0	0
T54	0	3	0	0
T76	0	4	0	0
T77	0	6	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	4	0	0
T84	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	986100051	0	0
T1	14708	11270	0	0
T2	11584	8565	0	0
T3	140960	77851	0	0
T4	37512	16323	0	0
T5	368768	14465	0	0
T10	154760	93429	0	0
T11	139992	16964	0	0
T12	115980	111024	0	0
T13	16844	11323	0	0
T14	119648	90317	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2487	0	0
T1	3677	1	0	0
T2	5792	1	0	0
T3	105720	1	0	0
T4	28134	0	0	0
T5	368768	0	0	0
T6	132195	0	0	0
T7	0	2	0	0
T10	116070	3	0	0
T11	139992	3	0	0
T12	86985	0	0	0
T13	16844	0	0	0
T14	119648	0	0	0
T22	200910	1	0	0
T23	90898	3	0	0
T24	53324	1	0	0
T25	8200	1	0	0
T26	0	11	0	0
T27	0	6	0	0
T28	0	2	0	0
T35	1831	2	0	0
T36	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2435	0	0
T1	3677	1	0	0
T2	5792	1	0	0
T3	105720	1	0	0
T4	28134	0	0	0
T5	368768	0	0	0
T6	132195	0	0	0
T7	0	1	0	0
T10	116070	2	0	0
T11	139992	3	0	0
T12	86985	0	0	0
T13	16844	0	0	0
T14	119648	0	0	0
T22	200910	1	0	0
T23	90898	2	0	0
T24	53324	1	0	0
T25	8200	1	0	0
T26	0	11	0	0
T27	0	6	0	0
T28	0	2	0	0
T35	1831	2	0	0
T36	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2381	0	0
T1	3677	1	0	0
T2	5792	1	0	0
T3	105720	1	0	0
T4	28134	0	0	0
T5	368768	0	0	0
T6	132195	0	0	0
T7	0	1	0	0
T10	116070	2	0	0
T11	139992	3	0	0
T12	86985	0	0	0
T13	16844	0	0	0
T14	119648	0	0	0
T22	200910	1	0	0
T23	90898	2	0	0
T24	53324	1	0	0
T25	8200	1	0	0
T26	0	9	0	0
T27	0	5	0	0
T28	0	2	0	0
T35	1831	2	0	0
T36	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2339	0	0
T1	3677	1	0	0
T2	5792	1	0	0
T3	105720	1	0	0
T4	28134	0	0	0
T5	368768	0	0	0
T6	132195	0	0	0
T7	0	1	0	0
T10	116070	2	0	0
T11	139992	3	0	0
T12	86985	0	0	0
T13	16844	0	0	0
T14	119648	0	0	0
T22	200910	1	0	0
T23	90898	2	0	0
T24	53324	1	0	0
T25	8200	1	0	0
T26	0	9	0	0
T27	0	5	0	0
T28	0	2	0	0
T35	1831	2	0	0
T36	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3332	0	0
T1	3677	1	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	28134	0	0	0
T5	276576	0	0	0
T6	396585	0	0	0
T8	41546	0	0	0
T10	38690	0	0	0
T11	139992	2	0	0
T12	86985	2	0	0
T13	12633	0	0	0
T14	89736	11	0	0
T22	200910	0	0	0
T23	136347	0	0	0
T24	159972	0	0	0
T25	8200	1	0	0
T26	0	2	0	0
T27	0	10	0	0
T28	0	3	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	1831	0	0	0
T36	0	2	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T49	0	3	0	0
T50	0	14	0	0
T64	0	8	0	0
T79	0	1	0	0
T80	0	5	0	0
T85	0	18	0	0
T86	0	4	0	0
T87	0	11	0	0
T88	0	21	0	0
T89	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	357444	0	0
T1	3677	46	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	28134	0	0	0
T5	276576	0	0	0
T6	396585	0	0	0
T8	41546	0	0	0
T10	38690	0	0	0
T11	139992	104	0	0
T12	86985	86	0	0
T13	12633	0	0	0
T14	89736	757	0	0
T22	200910	0	0	0
T23	136347	0	0	0
T24	159972	0	0	0
T25	8200	55	0	0
T26	0	161	0	0
T27	0	1378	0	0
T28	0	277	0	0
T33	0	8	0	0
T34	0	141	0	0
T35	1831	0	0	0
T36	0	500	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T49	0	306	0	0
T50	0	2308	0	0
T64	0	777	0	0
T79	0	118	0	0
T80	0	289	0	0
T85	0	1957	0	0
T86	0	690	0	0
T87	0	1908	0	0
T88	0	1213	0	0
T89	0	25	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3012	0	0
T1	3677	1	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	28134	0	0	0
T5	276576	0	0	0
T6	396585	0	0	0
T8	41546	0	0	0
T10	38690	0	0	0
T11	139992	2	0	0
T12	86985	2	0	0
T13	12633	0	0	0
T14	89736	11	0	0
T22	200910	0	0	0
T23	136347	0	0	0
T24	159972	0	0	0
T25	8200	1	0	0
T26	0	1	0	0
T27	0	6	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	6	0	0
T35	1831	0	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T50	0	8	0	0
T64	0	8	0	0
T79	0	1	0	0
T80	0	5	0	0
T85	0	18	0	0
T86	0	3	0	0
T87	0	9	0	0
T88	0	21	0	0
T90	0	1	0	0
T91	0	11	0	0
T92	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	214	0	0
T7	162529	0	0	0
T9	44448	0	0	0
T17	24442	0	0	0
T20	89797	0	0	0
T26	63833	1	0	0
T27	103757	2	0	0
T36	109325	2	0	0
T44	37625	0	0	0
T45	71982	0	0	0
T46	3520	0	0	0
T48	119217	0	0	0
T49	16715	0	0	0
T50	0	6	0	0
T53	0	2	0	0
T54	0	4	0	0
T68	180914	0	0	0
T69	4695	0	0	0
T77	22495	0	0	0
T80	0	2	0	0
T85	32231	0	0	0
T87	65100	2	0	0
T89	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	5	0	0
T104	0	4	0	0
T105	77804	0	0	0
T106	50782	0	0	0
T107	90602	0	0	0
T108	1626	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5735	0	0
T6	528780	1247	0	0
T7	650116	0	0	0
T8	166184	1311	0	0
T9	0	1280	0	0
T17	97768	0	0	0
T25	32800	0	0	0
T26	255332	0	0	0
T35	7324	0	0	0
T40	0	675	0	0
T41	0	1222	0	0
T42	84608	0	0	0
T43	13384	0	0	0
T44	150500	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4655	0	0
T6	528780	1007	0	0
T7	650116	0	0	0
T8	166184	1071	0	0
T9	0	1040	0	0
T17	97768	0	0	0
T25	32800	0	0	0
T26	255332	0	0	0
T35	7324	0	0	0
T40	0	555	0	0
T41	0	982	0	0
T42	84608	0	0	0
T43	13384	0	0	0
T44	150500	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14708	14484	0	0
T2	11584	11364	0	0
T3	140960	140660	0	0
T4	37512	37000	0	0
T5	368768	368216	0	0
T10	154760	154420	0	0
T11	139992	139704	0	0
T12	115980	115756	0	0
T13	16844	16596	0	0
T14	119648	119444	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14708	14484	0	0
T2	11584	11364	0	0
T3	140960	140660	0	0
T4	37512	37000	0	0
T5	368768	368216	0	0
T10	154760	154420	0	0
T11	139992	139704	0	0
T12	115980	115756	0	0
T13	16844	16596	0	0
T14	119648	119444	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T10 T4 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T10 T4 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T10 T4 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T11 
159        1/1                    state_d = TimeoutSt;
           Tests:       T12 T14 T11 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T12 T14 T11 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T12 T14 T11 
172        1/1                    state_d    = Phase0St;
           Tests:       T26 T28 T49 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T26 T28 T49 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T26 T28 T49 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T26 T28 T49 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T12 T14 T11 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T11 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T12 T14 T11 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T14 T11 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T10 T11 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T10 T11 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T10 T11 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T10 T11 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T10 T11 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T10 T11 
194        1/1                    state_d = IdleSt;
           Tests:       T57 T109 T110 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T57 T109 T110 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T57 T109 T110 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T10 T11 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T10 T11 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T11 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T10 T11 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T10 T11 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T10 T11 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T10 T11 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T10 T11 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T10 T11 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T10 T11 
211        1/1                    state_d = IdleSt;
           Tests:       T10 T7 T111 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T7 T111 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T7 T111 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T10 T11 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T10 T11 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T11 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T10 T11 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T10 T11 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T10 T11 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T10 T11 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T10 T11 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T10 T11 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T10 T11 
229        1/1                    state_d = IdleSt;
           Tests:       T26 T54 T30 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T26 T54 T30 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T26 T54 T30 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T10 T11 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T10 T11 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T11 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T10 T11 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T10 T11 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T10 T11 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T10 T11 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T10 T11 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T10 T11 
245        1/1                    state_d = IdleSt;
           Tests:       T84 T112 T113 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T84 T112 T113 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T84 T112 T113 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T10 T11 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T10 T11 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T11 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T10 T11 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T10 T11 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T10 T11 
260        1/1                  if (clr_i) begin
           Tests:       T2 T10 T11 
261        1/1                    state_d = IdleSt;
           Tests:       T26 T28 T50 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T10,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T10,T12
1	0	1	Covered	T2,T7,T76
1	1	0	Covered	T1,T12,T14
1	1	1	Covered	T12,T14,T11

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T11
0	1	Covered	T26,T50,T80
1	0	Covered	T28,T49,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T14,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T49,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T11
1	0	Not Covered
1	1	Covered	T26,T50,T80

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T11,T26
1	Covered	T2,T26,T27

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T11
1	Covered	T7,T28,T50

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T26
1	Covered	T11,T26,T50

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T26
1	Covered	T10,T48,T49

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T10,T26

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T10,T26

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T10,T11
Phase1St	198	Covered	T2,T10,T11
Phase2St	215	Covered	T2,T10,T11
Phase3St	233	Covered	T2,T10,T11
TerminalSt	249	Covered	T2,T10,T11
TimeoutSt	159	Covered	T12,T14,T11

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T2,T10,T11
IdleSt->TimeoutSt	159	Covered	T12,T14,T11
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T57,T114
Phase0St->Phase1St	198	Covered	T2,T10,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T10,T7,T30
Phase1St->Phase2St	215	Covered	T2,T10,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T54,T30
Phase2St->Phase3St	233	Covered	T2,T10,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T84,T112,T113
Phase3St->TerminalSt	249	Covered	T2,T10,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T26,T28,T50
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T12,T14,T11
TimeoutSt->Phase0St	172	Covered	T26,T28,T49

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T28,T49
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T57,T109,T110
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T10,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T11,T26
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T7,T111
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T10,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T11,T26
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T54,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T10,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T11,T26
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T84,T112,T113
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T10,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T11,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T26,T28,T50
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T10,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	583104694	273	0	0
CheckAccumTrig0_A	583104694	466	0	0
CheckAccumTrig1_A	583104694	20	0	0
CheckClr_A	583104694	189	0	0
CheckEn_A	582837594	263556189	0	0
CheckPhase0_A	583104694	526	0	0
CheckPhase1_A	583104694	514	0	0
CheckPhase2_A	583104694	504	0	0
CheckPhase3_A	583104694	494	0	0
CheckTimeout0_A	583104694	461	0	0
CheckTimeoutSt1_A	583104694	57919	0	0
CheckTimeoutSt2_A	583104694	390	0	0
CheckTimeoutStTrig_A	583104694	48	0	0
ErrorStAllEscAsserted_A	583104694	1404	0	0
ErrorStIsTerminal_A	583104694	1134	0	0
EscStateOut_A	582835848	582766975	0	0
u_state_regs_A	583104694	582920888	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	273	0	0
T6	132195	49	0	0
T7	162529	0	0	0
T8	41546	49	0	0
T9	0	79	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	29	0	0
T41	0	67	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	466	0	0
T2	2896	1	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T7	0	1	0	0
T10	38690	2	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T26	0	4	0	0
T27	0	1	0	0
T28	0	1	0	0
T36	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	20	0	0
T15	592482	0	0	0
T19	76079	0	0	0
T28	73493	1	0	0
T33	86115	0	0	0
T41	34049	0	0	0
T47	372747	0	0	0
T49	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	3143	0	0	0
T64	33423	0	0	0
T65	31302	0	0	0
T66	46835	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	189	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T7	0	1	0	0
T10	38690	1	0	0
T11	34998	0	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T26	0	4	0	0
T28	0	2	0	0
T50	0	2	0	0
T54	0	3	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	4	0	0
T84	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582837594	263556189	0	0
T1	3677	3620	0	0
T2	2896	2137	0	0
T3	35240	5533	0	0
T4	9378	2353	0	0
T5	92192	3608	0	0
T10	38690	10333	0	0
T11	34998	3096	0	0
T12	28995	27362	0	0
T13	4211	2813	0	0
T14	29912	18724	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	526	0	0
T2	2896	1	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T7	0	1	0	0
T10	38690	2	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T26	0	5	0	0
T27	0	1	0	0
T28	0	2	0	0
T36	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	514	0	0
T2	2896	1	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	1	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T26	0	5	0	0
T27	0	1	0	0
T28	0	2	0	0
T36	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	504	0	0
T2	2896	1	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	1	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T26	0	4	0	0
T27	0	1	0	0
T28	0	2	0	0
T36	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	494	0	0
T2	2896	1	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	1	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T26	0	4	0	0
T27	0	1	0	0
T28	0	2	0	0
T36	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	461	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T11	34998	1	0	0
T12	28995	1	0	0
T13	4211	0	0	0
T14	29912	3	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T26	0	2	0	0
T28	0	3	0	0
T49	0	1	0	0
T50	0	8	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	57919	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T11	34998	52	0	0
T12	28995	43	0	0
T13	4211	0	0	0
T14	29912	240	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T26	0	161	0	0
T28	0	277	0	0
T49	0	2	0	0
T50	0	1489	0	0
T86	0	336	0	0
T87	0	137	0	0
T88	0	467	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	390	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T11	34998	1	0	0
T12	28995	1	0	0
T13	4211	0	0	0
T14	29912	3	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T26	0	1	0	0
T28	0	2	0	0
T34	0	2	0	0
T50	0	3	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	48	0	0
T7	162529	0	0	0
T9	44448	0	0	0
T17	24442	0	0	0
T26	63833	1	0	0
T44	37625	0	0	0
T45	71982	0	0	0
T46	3520	0	0	0
T50	0	4	0	0
T53	0	1	0	0
T54	0	2	0	0
T80	0	2	0	0
T85	32231	0	0	0
T97	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T103	0	5	0	0
T104	0	3	0	0
T105	77804	0	0	0
T106	50782	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	1404	0	0
T6	132195	298	0	0
T7	162529	0	0	0
T8	41546	312	0	0
T9	0	317	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	175	0	0
T41	0	302	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	1134	0	0
T6	132195	238	0	0
T7	162529	0	0	0
T8	41546	252	0	0
T9	0	257	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	145	0	0
T41	0	242	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582835848	582766975	0	0
T1	3677	3621	0	0
T2	2896	2841	0	0
T3	35240	35165	0	0
T4	9378	9250	0	0
T5	92192	92054	0	0
T10	38690	38605	0	0
T11	34998	34926	0	0
T12	28995	28939	0	0
T13	4211	4149	0	0
T14	29912	29861	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	582920888	0	0
T1	3677	3621	0	0
T2	2896	2841	0	0
T3	35240	35165	0	0
T4	9378	9250	0	0
T5	92192	92054	0	0
T10	38690	38605	0	0
T11	34998	34926	0	0
T12	28995	28939	0	0
T13	4211	4149	0	0
T14	29912	29861	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T13 T11 T25 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T13 T11 T25 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T13 T11 T25 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T85 
159        1/1                    state_d = TimeoutSt;
           Tests:       T12 T14 T85 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T12 T14 T85 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T12 T14 T85 
172        1/1                    state_d    = Phase0St;
           Tests:       T86 T27 T49 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T86 T27 T49 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T86 T27 T49 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T86 T27 T49 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T12 T14 T85 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T85 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T12 T14 T85 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T14 T85 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T11 T25 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T13 T11 T25 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T13 T11 T25 
190        1/1                  esc_state_o = Phase0;
           Tests:       T13 T11 T25 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T13 T11 T25 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T13 T11 T25 
194        1/1                    state_d = IdleSt;
           Tests:       T115 T116 T117 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T115 T116 T117 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T115 T116 T117 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T11 T25 
198        1/1                    state_d = Phase1St;
           Tests:       T13 T11 T25 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T11 T25 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T11 T25 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T11 T25 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T13 T11 T25 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T13 T11 T25 
207        1/1                  esc_state_o = Phase1;
           Tests:       T13 T11 T25 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T13 T11 T25 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T13 T11 T25 
211        1/1                    state_d = IdleSt;
           Tests:       T118 T119 T70 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T118 T119 T70 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T118 T119 T70 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T11 T25 
215        1/1                    state_d = Phase2St;
           Tests:       T13 T11 T25 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T11 T25 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T11 T25 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T11 T25 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T13 T11 T25 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T13 T11 T25 
224        1/1                  esc_state_o = Phase2;
           Tests:       T13 T11 T25 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T13 T11 T25 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T13 T11 T25 
229        1/1                    state_d = IdleSt;
           Tests:       T34 T99 T120 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T99 T120 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T99 T120 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T11 T25 
233        1/1                    state_d = Phase3St;
           Tests:       T13 T11 T25 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T11 T25 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T11 T25 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T13 T11 T25 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T13 T11 T25 
241        1/1                  esc_state_o = Phase3;
           Tests:       T13 T11 T25 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T13 T11 T25 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T13 T11 T25 
245        1/1                    state_d = IdleSt;
           Tests:       T121 T122 T123 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T121 T122 T123 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T121 T122 T123 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T11 T25 
249        1/1                    state_d = TerminalSt;
           Tests:       T13 T11 T25 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T11 T25 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T11 T25 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T13 T11 T25 
259        1/1                  esc_state_o = Terminal;
           Tests:       T13 T11 T25 
260        1/1                  if (clr_i) begin
           Tests:       T13 T11 T25 
261        1/1                    state_d = IdleSt;
           Tests:       T25 T76 T27 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T12,T13,T14
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T14

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T12,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T13,T11,T25

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T14,T11
1	0	1	Covered	T13,T35,T26
1	1	0	Covered	T1,T12,T14
1	1	1	Covered	T12,T14,T85

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T85
0	1	Covered	T86,T27,T49
1	0	Covered	T70,T124,T125

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T14,T85
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T70,T124,T125

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T85
1	0	Not Covered
1	1	Covered	T86,T27,T49

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T25,T7
1	Covered	T13,T27,T47

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T11,T25
1	Covered	T7,T76,T50

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T7,T86
1	Covered	T11,T25,T28

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T11,T25
1	Covered	T86,T27,T67

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T13,T11,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T13,T11,T25

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T13,T11,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T13,T25,T86

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T13,T11,T25
Phase1St	198	Covered	T13,T11,T25
Phase2St	215	Covered	T13,T11,T25
Phase3St	233	Covered	T13,T11,T25
TerminalSt	249	Covered	T13,T11,T25
TimeoutSt	159	Covered	T12,T14,T85

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T13,T11,T25
IdleSt->TimeoutSt	159	Covered	T12,T14,T85
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T50,T115,T114
Phase0St->Phase1St	198	Covered	T13,T11,T25
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T118,T119,T70
Phase1St->Phase2St	215	Covered	T13,T11,T25
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T34,T99,T120
Phase2St->Phase3St	233	Covered	T13,T11,T25
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T121,T122,T123
Phase3St->TerminalSt	249	Covered	T13,T11,T25
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T25,T76,T27
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T12,T14,T85
TimeoutSt->Phase0St	172	Covered	T86,T27,T49

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T11,T25
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T85
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T86,T27,T49
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T85
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T85
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T115,T116,T117
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T13,T11,T25
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T11,T25,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T118,T119,T70
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T13,T11,T25
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T11,T25,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T99,T120
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T13,T11,T25
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T11,T25,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T121,T122,T123
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T13,T11,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T11,T25,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T25,T76,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T13,T11,T25
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	583104694	256	0	0
CheckAccumTrig0_A	583104694	517	0	0
CheckAccumTrig1_A	583104694	21	0	0
CheckClr_A	583104694	251	0	0
CheckEn_A	582837594	227734722	0	0
CheckPhase0_A	583104694	581	0	0
CheckPhase1_A	583104694	565	0	0
CheckPhase2_A	583104694	553	0	0
CheckPhase3_A	583104694	546	0	0
CheckTimeout0_A	583104694	1078	0	0
CheckTimeoutSt1_A	583104694	114990	0	0
CheckTimeoutSt2_A	583104694	1000	0	0
CheckTimeoutStTrig_A	583104694	55	0	0
ErrorStAllEscAsserted_A	583104694	1477	0	0
ErrorStIsTerminal_A	583104694	1207	0	0
EscStateOut_A	582835848	582766975	0	0
u_state_regs_A	583104694	582920888	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	256	0	0
T6	132195	63	0	0
T7	162529	0	0	0
T8	41546	52	0	0
T9	0	57	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	33	0	0
T41	0	51	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	517	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T7	0	1	0	0
T11	34998	1	0	0
T13	4211	1	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T25	8200	2	0	0
T27	0	1	0	0
T28	0	1	0	0
T35	1831	0	0	0
T47	0	1	0	0
T66	0	1	0	0
T67	0	2	0	0
T76	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	21	0	0
T70	992580	6	0	0
T71	803956	0	0	0
T72	107071	0	0	0
T73	1257	0	0	0
T74	327360	0	0	0
T75	349097	0	0	0
T104	327762	0	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	4	0	0
T132	0	2	0	0
T133	246635	0	0	0
T134	21226	0	0	0
T135	340370	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	251	0	0
T7	162529	0	0	0
T8	41546	0	0	0
T9	44448	0	0	0
T17	24442	0	0	0
T25	8200	1	0	0
T26	63833	0	0	0
T27	0	1	0	0
T34	0	2	0	0
T35	1831	0	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0
T49	0	1	0	0
T50	0	3	0	0
T67	0	2	0	0
T76	0	1	0	0
T83	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582837594	227734722	0	0
T1	3677	3620	0	0
T2	2896	2157	0	0
T3	35240	35164	0	0
T4	9378	2385	0	0
T5	92192	3642	0	0
T10	38690	38604	0	0
T11	34998	3104	0	0
T12	28995	27362	0	0
T13	4211	2873	0	0
T14	29912	11873	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	581	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T7	0	1	0	0
T11	34998	1	0	0
T13	4211	1	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T25	8200	2	0	0
T27	0	2	0	0
T28	0	1	0	0
T35	1831	0	0	0
T47	0	1	0	0
T66	0	1	0	0
T76	0	2	0	0
T86	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	565	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T7	0	1	0	0
T11	34998	1	0	0
T13	4211	1	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T25	8200	2	0	0
T27	0	2	0	0
T28	0	1	0	0
T35	1831	0	0	0
T47	0	1	0	0
T66	0	1	0	0
T76	0	2	0	0
T86	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	553	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T7	0	1	0	0
T11	34998	1	0	0
T13	4211	1	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T25	8200	2	0	0
T27	0	2	0	0
T28	0	1	0	0
T35	1831	0	0	0
T47	0	1	0	0
T66	0	1	0	0
T76	0	2	0	0
T86	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	546	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T7	0	1	0	0
T11	34998	1	0	0
T13	4211	1	0	0
T14	29912	0	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T25	8200	2	0	0
T27	0	2	0	0
T28	0	1	0	0
T35	1831	0	0	0
T47	0	1	0	0
T66	0	1	0	0
T76	0	2	0	0
T86	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	1078	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T11	34998	0	0	0
T12	28995	1	0	0
T13	4211	0	0	0
T14	29912	8	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T27	0	1	0	0
T49	0	2	0	0
T64	0	8	0	0
T77	0	6	0	0
T85	0	5	0	0
T86	0	2	0	0
T87	0	7	0	0
T88	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	114990	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T11	34998	0	0	0
T12	28995	43	0	0
T13	4211	0	0	0
T14	29912	517	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T27	0	300	0	0
T49	0	304	0	0
T64	0	777	0	0
T77	0	292	0	0
T85	0	624	0	0
T86	0	354	0	0
T87	0	1445	0	0
T88	0	223	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	1000	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T6	132195	0	0	0
T11	34998	0	0	0
T12	28995	1	0	0
T13	4211	0	0	0
T14	29912	8	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T64	0	8	0	0
T77	0	6	0	0
T85	0	5	0	0
T86	0	1	0	0
T87	0	7	0	0
T88	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	55	0	0
T18	63022	0	0	0
T27	103757	1	0	0
T28	73493	0	0	0
T40	17396	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T57	0	1	0	0
T63	3143	0	0	0
T64	33423	0	0	0
T76	159372	0	0	0
T86	88860	1	0	0
T99	0	1	0	0
T101	0	1	0	0
T136	0	3	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	12929	0	0	0
T141	8388	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	1477	0	0
T6	132195	312	0	0
T7	162529	0	0	0
T8	41546	352	0	0
T9	0	340	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	172	0	0
T41	0	301	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	1207	0	0
T6	132195	252	0	0
T7	162529	0	0	0
T8	41546	292	0	0
T9	0	280	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	142	0	0
T41	0	241	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582835848	582766975	0	0
T1	3677	3621	0	0
T2	2896	2841	0	0
T3	35240	35165	0	0
T4	9378	9250	0	0
T5	92192	92054	0	0
T10	38690	38605	0	0
T11	34998	34926	0	0
T12	28995	28939	0	0
T13	4211	4149	0	0
T14	29912	29861	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	582920888	0	0
T1	3677	3621	0	0
T2	2896	2841	0	0
T3	35240	35165	0	0
T4	9378	9250	0	0
T5	92192	92054	0	0
T10	38690	38605	0	0
T11	34998	34926	0	0
T12	28995	28939	0	0
T13	4211	4149	0	0
T14	29912	29861	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T11 T22 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T11 T22 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T11 T22 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T25 T85 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T25 T85 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T25 T85 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T25 T85 
172        1/1                    state_d    = Phase0St;
           Tests:       T33 T36 T87 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T33 T36 T87 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T33 T36 T87 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T33 T36 T87 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T25 T85 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T25 T85 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T25 T85 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T25 T85 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T11 T22 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T3 T11 T22 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T3 T11 T22 
190        1/1                  esc_state_o = Phase0;
           Tests:       T3 T11 T22 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T3 T11 T22 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T3 T11 T22 
194        1/1                    state_d = IdleSt;
           Tests:       T30 T31 T114 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T30 T31 T114 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T30 T31 T114 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T11 T22 
198        1/1                    state_d = Phase1St;
           Tests:       T3 T11 T22 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T11 T22 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T11 T22 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T11 T22 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T3 T11 T22 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T3 T11 T22 
207        1/1                  esc_state_o = Phase1;
           Tests:       T3 T11 T22 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T3 T11 T22 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T3 T11 T22 
211        1/1                    state_d = IdleSt;
           Tests:       T23 T51 T142 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T23 T51 T142 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T23 T51 T142 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T11 T22 
215        1/1                    state_d = Phase2St;
           Tests:       T3 T11 T22 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T11 T22 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T11 T22 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T11 T22 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T3 T11 T22 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T3 T11 T22 
224        1/1                  esc_state_o = Phase2;
           Tests:       T3 T11 T22 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T3 T11 T22 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T3 T11 T22 
229        1/1                    state_d = IdleSt;
           Tests:       T26 T32 T54 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T26 T32 T54 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T26 T32 T54 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T11 T22 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T11 T22 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T11 T22 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T11 T22 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T11 T22 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T11 T22 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T11 T22 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T11 T22 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T11 T22 
245        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T32 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T34 T32 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T34 T32 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T11 T22 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T11 T22 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T11 T22 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T11 T22 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T11 T22 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T11 T22 
260        1/1                  if (clr_i) begin
           Tests:       T3 T11 T22 
261        1/1                    state_d = IdleSt;
           Tests:       T23 T35 T26 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T22

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T12
1	0	1	Covered	T3,T23,T43
1	1	0	Covered	T1,T12,T14
1	1	1	Covered	T1,T25,T85

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T25,T85
0	1	Covered	T36,T87,T50
1	0	Covered	T33,T50,T34

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T25,T85
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T33,T50,T34

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T85
1	0	Covered	T37,T38
1	1	Covered	T36,T87,T50

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T11,T22
1	Covered	T35,T43,T105

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T3,T11,T23

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T11,T22
1	Covered	T23,T24,T44

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T11,T23
1	Covered	T22,T26,T28

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T11,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T23,T35

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T11,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T11,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T11,T22
Phase1St	198	Covered	T3,T11,T22
Phase2St	215	Covered	T3,T11,T22
Phase3St	233	Covered	T3,T11,T22
TerminalSt	249	Covered	T3,T11,T22
TimeoutSt	159	Covered	T1,T25,T85

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T3,T11,T22
IdleSt->TimeoutSt	159	Covered	T1,T25,T85
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T31,T114
Phase0St->Phase1St	198	Covered	T3,T11,T22
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T23,T51,T142
Phase1St->Phase2St	215	Covered	T3,T11,T22
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T32,T54
Phase2St->Phase3St	233	Covered	T3,T11,T22
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T33,T34,T32
Phase3St->TerminalSt	249	Covered	T3,T11,T22
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T23,T35,T26
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T25,T85
TimeoutSt->Phase0St	172	Covered	T33,T36,T87

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T22
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T85
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T33,T36,T87
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T85
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T85
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T31,T114
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T11,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T11,T22
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T51,T142
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T11,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T11,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T32,T54
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T11,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T11,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T34,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T11,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T11,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T23,T35,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T11,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	583104694	238	0	0
CheckAccumTrig0_A	583104694	804	0	0
CheckAccumTrig1_A	583104694	37	0	0
CheckClr_A	583104694	376	0	0
CheckEn_A	582837594	244224896	0	0
CheckPhase0_A	583104694	872	0	0
CheckPhase1_A	583104694	855	0	0
CheckPhase2_A	583104694	834	0	0
CheckPhase3_A	583104694	814	0	0
CheckTimeout0_A	583104694	888	0	0
CheckTimeoutSt1_A	583104694	89090	0	0
CheckTimeoutSt2_A	583104694	797	0	0
CheckTimeoutStTrig_A	583104694	51	0	0
ErrorStAllEscAsserted_A	583104694	1386	0	0
ErrorStIsTerminal_A	583104694	1116	0	0
EscStateOut_A	582835848	582766975	0	0
u_state_regs_A	583104694	582920888	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	238	0	0
T6	132195	55	0	0
T7	162529	0	0	0
T8	41546	74	0	0
T9	0	59	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	17	0	0
T41	0	33	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	804	0	0
T3	35240	1	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	0	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	1	0	0
T23	45449	3	0	0
T24	0	1	0	0
T26	0	5	0	0
T35	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	37	0	0
T15	592482	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	86115	2	0	0
T34	0	1	0	0
T36	109325	0	0	0
T41	34049	0	0	0
T47	372747	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T65	31302	0	0	0
T66	46835	0	0	0
T67	13189	0	0	0
T68	180914	0	0	0
T69	4695	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	376	0	0
T6	132195	0	0	0
T8	41546	0	0	0
T23	45449	2	0	0
T24	53324	0	0	0
T25	8200	0	0	0
T26	63833	4	0	0
T27	0	5	0	0
T28	0	3	0	0
T33	0	2	0	0
T35	1831	1	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	2	0	0
T77	0	6	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582837594	244224896	0	0
T1	3677	2011	0	0
T2	2896	2125	0	0
T3	35240	1990	0	0
T4	9378	2337	0	0
T5	92192	3592	0	0
T10	38690	38604	0	0
T11	34998	5910	0	0
T12	28995	27362	0	0
T13	4211	2795	0	0
T14	29912	29860	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	872	0	0
T3	35240	1	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	0	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	1	0	0
T23	45449	3	0	0
T24	0	1	0	0
T26	0	5	0	0
T35	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	855	0	0
T3	35240	1	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	0	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	1	0	0
T23	45449	2	0	0
T24	0	1	0	0
T26	0	5	0	0
T35	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	834	0	0
T3	35240	1	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	0	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	1	0	0
T23	45449	2	0	0
T24	0	1	0	0
T26	0	4	0	0
T35	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	814	0	0
T3	35240	1	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	0	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T22	66970	1	0	0
T23	45449	2	0	0
T24	0	1	0	0
T26	0	4	0	0
T35	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	888	0	0
T1	3677	1	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	0	0	0
T11	34998	0	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T25	0	1	0	0
T27	0	2	0	0
T33	0	2	0	0
T36	0	1	0	0
T50	0	5	0	0
T79	0	1	0	0
T80	0	4	0	0
T85	0	6	0	0
T87	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	89090	0	0
T1	3677	46	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	0	0	0
T11	34998	0	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T25	0	55	0	0
T27	0	146	0	0
T33	0	8	0	0
T36	0	138	0	0
T50	0	636	0	0
T79	0	118	0	0
T80	0	246	0	0
T85	0	632	0	0
T87	0	60	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	797	0	0
T1	3677	1	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T10	38690	0	0	0
T11	34998	0	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T25	0	1	0	0
T27	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T50	0	2	0	0
T79	0	1	0	0
T80	0	4	0	0
T85	0	6	0	0
T90	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	51	0	0
T20	89797	0	0	0
T36	109325	1	0	0
T48	119217	0	0	0
T49	16715	0	0	0
T50	0	2	0	0
T54	0	1	0	0
T68	180914	0	0	0
T69	4695	0	0	0
T77	22495	0	0	0
T87	65100	1	0	0
T89	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T98	0	1	0	0
T107	90602	0	0	0
T108	1626	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	1386	0	0
T6	132195	292	0	0
T7	162529	0	0	0
T8	41546	334	0	0
T9	0	285	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	156	0	0
T41	0	319	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	1116	0	0
T6	132195	232	0	0
T7	162529	0	0	0
T8	41546	274	0	0
T9	0	225	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	126	0	0
T41	0	259	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582835848	582766975	0	0
T1	3677	3621	0	0
T2	2896	2841	0	0
T3	35240	35165	0	0
T4	9378	9250	0	0
T5	92192	92054	0	0
T10	38690	38605	0	0
T11	34998	34926	0	0
T12	28995	28939	0	0
T13	4211	4149	0	0
T14	29912	29861	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	582920888	0	0
T1	3677	3621	0	0
T2	2896	2841	0	0
T3	35240	35165	0	0
T4	9378	9250	0	0
T5	92192	92054	0	0
T10	38690	38605	0	0
T11	34998	34926	0	0
T12	28995	28939	0	0
T13	4211	4149	0	0
T14	29912	29861	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T10 T11 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T10 T11 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T10 T11 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T85 T27 
159        1/1                    state_d = TimeoutSt;
           Tests:       T11 T85 T27 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T11 T85 T27 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T11 T85 T27 
172        1/1                    state_d    = Phase0St;
           Tests:       T27 T36 T87 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T27 T36 T87 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T27 T36 T87 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T27 T36 T87 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T11 T85 T27 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T85 T27 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T11 T85 T27 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T85 T27 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T10 T11 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T10 T11 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T10 T11 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T10 T11 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T10 T11 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T10 T11 
194        1/1                    state_d = IdleSt;
           Tests:       T29 T133 T114 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T133 T114 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T133 T114 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T10 T11 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T10 T11 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T10 T11 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T10 T11 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T10 T11 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T10 T11 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T10 T11 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T10 T11 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T10 T11 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T10 T11 
211        1/1                    state_d = IdleSt;
           Tests:       T143 T144 T145 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T143 T144 T145 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T143 T144 T145 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T10 T11 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T10 T11 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T10 T11 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T10 T11 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T10 T11 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T10 T11 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T10 T11 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T10 T11 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T10 T11 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T10 T11 
229        1/1                    state_d = IdleSt;
           Tests:       T27 T114 T121 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T27 T114 T121 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T27 T114 T121 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T10 T11 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T10 T11 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T10 T11 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T10 T11 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T10 T11 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T10 T11 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T10 T11 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T10 T11 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T10 T11 
245        1/1                    state_d = IdleSt;
           Tests:       T146 T133 T147 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T146 T133 T147 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T146 T133 T147 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T10 T11 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T10 T11 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T10 T11 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T10 T11 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T10 T11 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T10 T11 
260        1/1                  if (clr_i) begin
           Tests:       T1 T10 T11 
261        1/1                    state_d = IdleSt;
           Tests:       T26 T7 T76 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T23
1	0	1	Covered	T10,T46,T28
1	1	0	Covered	T1,T12,T14
1	1	1	Covered	T11,T85,T27

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T85,T27
0	1	Covered	T27,T36,T87
1	0	Covered	T27,T38,T147

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T11,T85,T27
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T27,T38,T147

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T85,T27
1	0	Covered	T39
1	1	Covered	T27,T36,T87

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T25,T35
1	Covered	T1,T10,T46

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T11
1	Covered	T26,T7,T27

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T11
1	Covered	T35,T76,T28

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T35
1	Covered	T11,T25,T66

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T1,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T10,T11,T35

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T10,T25,T26

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T25,T35,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T10,T11
Phase1St	198	Covered	T1,T10,T11
Phase2St	215	Covered	T1,T10,T11
Phase3St	233	Covered	T1,T10,T11
TerminalSt	249	Covered	T1,T10,T11
TimeoutSt	159	Covered	T11,T85,T27

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T1,T10,T11
IdleSt->TimeoutSt	159	Covered	T11,T85,T27
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T133,T114
Phase0St->Phase1St	198	Covered	T1,T10,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T143,T144,T145
Phase1St->Phase2St	215	Covered	T1,T10,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T114,T121
Phase2St->Phase3St	233	Covered	T1,T10,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T146,T133,T147
Phase3St->TerminalSt	249	Covered	T1,T10,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T26,T7,T76
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T11,T85,T27
TimeoutSt->Phase0St	172	Covered	T27,T36,T87

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T85,T27
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T27,T36,T87
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T85,T27
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T85,T27
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T133,T114
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T10,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T10,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T143,T144,T145
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T10,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T10,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T114,T121
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T10,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T10,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T146,T133,T147
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T10,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T10,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T26,T7,T76
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T10,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	583104694	261	0	0
CheckAccumTrig0_A	583104694	449	0	0
CheckAccumTrig1_A	583104694	16	0	0
CheckClr_A	583104694	177	0	0
CheckEn_A	582837594	250584244	0	0
CheckPhase0_A	583104694	508	0	0
CheckPhase1_A	583104694	501	0	0
CheckPhase2_A	583104694	490	0	0
CheckPhase3_A	583104694	485	0	0
CheckTimeout0_A	583104694	905	0	0
CheckTimeoutSt1_A	583104694	95445	0	0
CheckTimeoutSt2_A	583104694	825	0	0
CheckTimeoutStTrig_A	583104694	60	0	0
ErrorStAllEscAsserted_A	583104694	1468	0	0
ErrorStIsTerminal_A	583104694	1198	0	0
EscStateOut_A	582835848	582766975	0	0
u_state_regs_A	583104694	582920888	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	261	0	0
T6	132195	74	0	0
T7	162529	0	0	0
T8	41546	60	0	0
T9	0	66	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	21	0	0
T41	0	40	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	449	0	0
T1	3677	1	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T7	0	1	0	0
T10	38690	1	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	2	0	0
T35	0	1	0	0
T46	0	1	0	0
T76	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	16	0	0
T15	592482	0	0	0
T19	76079	0	0	0
T27	103757	1	0	0
T28	73493	0	0	0
T33	86115	0	0	0
T38	0	1	0	0
T41	34049	0	0	0
T47	372747	0	0	0
T63	3143	0	0	0
T64	33423	0	0	0
T65	31302	0	0	0
T145	0	1	0	0
T147	0	1	0	0
T148	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	177	0	0
T7	162529	1	0	0
T9	44448	0	0	0
T17	24442	0	0	0
T26	63833	1	0	0
T27	0	5	0	0
T28	0	1	0	0
T44	37625	0	0	0
T45	71982	0	0	0
T46	3520	0	0	0
T50	0	3	0	0
T51	0	3	0	0
T53	0	1	0	0
T76	0	4	0	0
T82	0	1	0	0
T85	32231	0	0	0
T105	77804	0	0	0
T106	50782	0	0	0
T154	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582837594	250584244	0	0
T1	3677	2019	0	0
T2	2896	2146	0	0
T3	35240	35164	0	0
T4	9378	9248	0	0
T5	92192	3623	0	0
T10	38690	5888	0	0
T11	34998	4854	0	0
T12	28995	28938	0	0
T13	4211	2842	0	0
T14	29912	29860	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	508	0	0
T1	3677	1	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T7	0	1	0	0
T10	38690	1	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	5	0	0
T35	0	1	0	0
T46	0	1	0	0
T76	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	501	0	0
T1	3677	1	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T7	0	1	0	0
T10	38690	1	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	5	0	0
T35	0	1	0	0
T46	0	1	0	0
T76	0	5	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	490	0	0
T1	3677	1	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T7	0	1	0	0
T10	38690	1	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	4	0	0
T35	0	1	0	0
T46	0	1	0	0
T76	0	5	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	485	0	0
T1	3677	1	0	0
T2	2896	0	0	0
T3	35240	0	0	0
T4	9378	0	0	0
T5	92192	0	0	0
T7	0	1	0	0
T10	38690	1	0	0
T11	34998	1	0	0
T12	28995	0	0	0
T13	4211	0	0	0
T14	29912	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	4	0	0
T35	0	1	0	0
T46	0	1	0	0
T76	0	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	905	0	0
T6	132195	0	0	0
T8	41546	0	0	0
T11	34998	1	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T25	8200	0	0	0
T27	0	7	0	0
T34	0	2	0	0
T35	1831	0	0	0
T36	0	1	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T50	0	1	0	0
T80	0	1	0	0
T85	0	7	0	0
T87	0	2	0	0
T88	0	9	0	0
T89	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	95445	0	0
T6	132195	0	0	0
T8	41546	0	0	0
T11	34998	52	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T25	8200	0	0	0
T27	0	932	0	0
T34	0	141	0	0
T35	1831	0	0	0
T36	0	362	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T50	0	183	0	0
T80	0	43	0	0
T85	0	701	0	0
T87	0	266	0	0
T88	0	523	0	0
T89	0	25	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	825	0	0
T6	132195	0	0	0
T8	41546	0	0	0
T11	34998	1	0	0
T22	66970	0	0	0
T23	45449	0	0	0
T24	53324	0	0	0
T25	8200	0	0	0
T27	0	4	0	0
T34	0	2	0	0
T35	1831	0	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T50	0	1	0	0
T80	0	1	0	0
T85	0	7	0	0
T87	0	1	0	0
T88	0	9	0	0
T91	0	11	0	0
T92	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	60	0	0
T15	592482	0	0	0
T19	76079	0	0	0
T27	103757	2	0	0
T28	73493	0	0	0
T33	86115	0	0	0
T36	0	1	0	0
T41	34049	0	0	0
T47	372747	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T57	0	2	0	0
T63	3143	0	0	0
T64	33423	0	0	0
T65	31302	0	0	0
T87	0	1	0	0
T89	0	1	0	0
T99	0	1	0	0
T102	0	1	0	0
T104	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	1468	0	0
T6	132195	345	0	0
T7	162529	0	0	0
T8	41546	313	0	0
T9	0	338	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	172	0	0
T41	0	300	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	1198	0	0
T6	132195	285	0	0
T7	162529	0	0	0
T8	41546	253	0	0
T9	0	278	0	0
T17	24442	0	0	0
T25	8200	0	0	0
T26	63833	0	0	0
T35	1831	0	0	0
T40	0	142	0	0
T41	0	240	0	0
T42	21152	0	0	0
T43	3346	0	0	0
T44	37625	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582835848	582766975	0	0
T1	3677	3621	0	0
T2	2896	2841	0	0
T3	35240	35165	0	0
T4	9378	9250	0	0
T5	92192	92054	0	0
T10	38690	38605	0	0
T11	34998	34926	0	0
T12	28995	28939	0	0
T13	4211	4149	0	0
T14	29912	29861	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583104694	582920888	0	0
T1	3677	3621	0	0
T2	2896	2841	0	0
T3	35240	35165	0	0
T4	9378	9250	0	0
T5	92192	92054	0	0
T10	38690	38605	0	0
T11	34998	34926	0	0
T12	28995	28939	0	0
T13	4211	4149	0	0
T14	29912	29861	0	0