Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	51535	1			T30	577		T25	5		T119	162
class_i[0x1]	30907	1			T10	2		T15	12		T30	410
class_i[0x2]	57144	1			T15	88		T53	8		T18	1
class_i[0x3]	38053	1			T30	4		T53	3		T36	47

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	43040	1			T15	20		T30	2		T53	2
alert[0x1]	44815	1			T10	1		T15	35		T30	982
alert[0x2]	45917	1			T15	30		T87	1		T53	6
alert[0x3]	43867	1			T10	1		T15	15		T30	7

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

177391

1

T10

2

T15

100

T30

991

esc_ping_fail

248

1

T18

1

T19

1

T20

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	42967	1			T15	20		T30	2		T53	2
esc_integrity_fail	alert[0x1]	44755	1			T10	1		T15	35		T30	982
esc_integrity_fail	alert[0x2]	45856	1			T15	30		T87	1		T53	6
esc_integrity_fail	alert[0x3]	43813	1			T10	1		T15	15		T30	7
esc_ping_fail	alert[0x0]	73	1			T20	1		T167	2		T38	2
esc_ping_fail	alert[0x1]	60	1			T20	1		T132	1		T38	2
esc_ping_fail	alert[0x2]	61	1			T18	1		T19	1		T20	1
esc_ping_fail	alert[0x3]	54	1			T132	2		T167	1		T38	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	51489	1			T30	577		T25	5		T119	162
esc_integrity_fail	class_i[0x1]	30826	1			T10	2		T15	12		T30	410
esc_integrity_fail	class_i[0x2]	57079	1			T15	88		T53	8		T19	7
esc_integrity_fail	class_i[0x3]	37997	1			T30	4		T53	3		T36	47
esc_ping_fail	class_i[0x0]	46	1			T38	7		T127	1		T129	1
esc_ping_fail	class_i[0x1]	81	1			T19	1		T20	2		T132	5
esc_ping_fail	class_i[0x2]	65	1			T18	1		T20	1		T116	4
esc_ping_fail	class_i[0x3]	56	1			T337	1		T360	1		T305	5