Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	544499054	0	0	630
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	544499054	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	544499054	544311867	0	0
tb.dut.CheckAccuCntDw	0	0	630	630	0	0
tb.dut.CheckEscCntDw	0	0	630	630	0	0
tb.dut.CheckNAlerts	0	0	630	630	0	0
tb.dut.CheckNClasses	0	0	630	630	0	0
tb.dut.CheckNEscSev	0	0	630	630	0	0
tb.dut.CrashdumpKnownO_A	0	0	544499054	544311867	0	0
tb.dut.EdnKnownO_A	0	0	544499054	544311867	0	0
tb.dut.EscPKnownO_A	0	0	544499054	544311867	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	544499054	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	544499054	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	544499054	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	544499054	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	544499054	90	0	0
tb.dut.IrqAKnownO_A	0	0	544499054	544311867	0	0
tb.dut.IrqBKnownO_A	0	0	544499054	544311867	0	0
tb.dut.IrqCKnownO_A	0	0	544499054	544311867	0	0
tb.dut.IrqDKnownO_A	0	0	544499054	544311867	0	0
tb.dut.TlAReadyKnownO_A	0	0	544499054	544311867	0	0
tb.dut.TlDValidKnownO_A	0	0	544499054	544311867	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	569248140	215447	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	569248140	17531	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	569248140	17636	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	569248140	17120	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	569248140	17415	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	569248140	17630	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	569248140	17168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	569248140	17191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	569248140	17609	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	569248140	17427	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	569248140	17533	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	569248140	17279	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	569248140	17332	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	569248140	17263	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	569248140	17228	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	569248140	17095	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	569248140	17269	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	569248140	17212	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	569248140	17230	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	569248140	17262	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	569248140	17523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	569248140	17353	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	569248140	16968	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	569248140	17066	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	569248140	17121	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	569248140	17711	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	569248140	17091	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	569248140	17368	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	569248140	17342	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	569248140	17174	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	569248140	17282	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	569248140	17433	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	569248140	17445	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	569248140	17342	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	569248140	17554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	569248140	17721	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	569248140	17449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	569248140	16937	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	569248140	17485	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	569248140	17176	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	569248140	17491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	569248140	17463	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	569248140	17175	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	569248140	17285	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	569248140	17120	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	569248140	17108	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	569248140	17348	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	569248140	17269	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	569248140	17552	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	569248140	17067	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	569248140	17194	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	569248140	17378	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	569248140	16971	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	569248140	17245	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	569248140	16953	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	569248140	17204	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	569248140	17185	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	569248140	17236	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	569248140	17360	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	569248140	17363	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	569248140	17392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	569248140	17375	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	569248140	17415	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	569248140	17245	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	569248140	17424	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	569248140	17220	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	569248140	17139	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	569248140	17356	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	569248140	17373	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	569248140	17351	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	569248140	31142	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	569248140	17221	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	569248140	17321	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	569248140	17447	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	569248140	17764	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	569248140	17386	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	569248140	17217	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	569248140	17302	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	569248140	17435	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	544499054	4682	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	544499054	184076	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	544499054	256715693	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	544499054	254	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	544499054	893	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	544499054	45	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	544499054	454	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	544261746	194169146	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	544499054	987	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	544499054	963	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	544499054	946	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	544499054	921	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	544499054	451	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	544499054	53818	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	544499054	326	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	544499054	78	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	544499054	1429	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	544499054	1159	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	544257248	544184274	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	630	630	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	544499054	544311867	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	544499054	4151	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	544499054	173188	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	544499054	299834195	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	544499054	230	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	544499054	442	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	544499054	28	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	544499054	178	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	544261746	218962791	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	544499054	512	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	544499054	500	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	544499054	494	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	544499054	488	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	544499054	501	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	544499054	77070	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	544499054	415	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	544499054	55	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	544499054	1452	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	544499054	1182	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	544257248	544184274	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	630	630	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	544499054	544311867	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	544499054	2969	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	544499054	192090	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	544499054	277883919	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	544499054	270	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	544499054	469	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	544499054	23	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	544499054	195	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	544261746	216113014	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	544499054	547	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	544499054	537	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	544499054	533	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	544499054	526	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	544499054	728	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	544499054	88774	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	544499054	641	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	544499054	61	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	544499054	1397	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	544499054	1127	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	544257248	544184274	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	630	630	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	544499054	544311867	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	544499054	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	544499054	3745	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	544499054	155209	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	544499054	315612935	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	544499054	282	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	544499054	488	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	544499054	19	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	544499054	203	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	544261746	231329921	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	544499054	545	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	544499054	534	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	544499054	528	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	544499054	521	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	544499054	605	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	544499054	72265	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	544499054	529	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	544499054	53	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	544499054	1457	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	544499054	1187	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	544257248	544184274	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	630	630	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	544499054	544311867	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	569248140	86153412	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	569248140	568483716	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	569248140	568483716	0	0
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