Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	78	1			T31	5		T44	1		T36	2
class_index[0x1]	55	1			T15	1		T90	1		T91	1
class_index[0x2]	61	1			T30	1		T87	1		T53	1
class_index[0x3]	53	1			T30	1		T25	1		T83	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	106	1			T31	5		T53	1		T44	1
intr_timeout_cnt[1]	53	1			T30	1		T90	1		T134	1
intr_timeout_cnt[2]	18	1			T25	1		T58	1		T264	1
intr_timeout_cnt[3]	17	1			T32	1		T36	1		T103	1
intr_timeout_cnt[4]	15	1			T15	1		T83	1		T98	1
intr_timeout_cnt[5]	6	1			T265	1		T266	1		T267	1
intr_timeout_cnt[6]	5	1			T62	1		T268	1		T121	1
intr_timeout_cnt[7]	9	1			T36	2		T104	1		T269	1
intr_timeout_cnt[8]	7	1			T87	1		T270	1		T271	1
intr_timeout_cnt[9]	11	1			T30	1		T99	2		T272	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	41	1			T31	5		T44	1		T36	2
class_index[0x0]	intr_timeout_cnt[1]	17	1			T100	2		T68	1		T69	1
class_index[0x0]	intr_timeout_cnt[2]	4	1			T273	1		T266	1		T274	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T121	1		T42	1		T267	1
class_index[0x0]	intr_timeout_cnt[4]	6	1			T98	1		T275	1		T276	3
class_index[0x0]	intr_timeout_cnt[6]	2	1			T268	1		T276	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T121	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T271	1		T277	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T272	1		T270	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	17	1			T91	1		T102	2		T105	1
class_index[0x1]	intr_timeout_cnt[1]	6	1			T90	1		T109	1		T278	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T264	1		T166	1		T161	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T36	1		T103	1		T121	1
class_index[0x1]	intr_timeout_cnt[4]	4	1			T15	1		T42	2		T279	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T265	1		T280	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T62	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	7	1			T36	2		T104	1		T264	1
class_index[0x1]	intr_timeout_cnt[8]	2	1			T115	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	6	1			T99	2		T121	2		T281	2
class_index[0x2]	intr_timeout_cnt[0]	23	1			T53	1		T36	3		T133	1
class_index[0x2]	intr_timeout_cnt[1]	17	1			T30	1		T134	1		T107	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T58	1		T72	1		T257	1
class_index[0x2]	intr_timeout_cnt[3]	6	1			T32	1		T282	3		T283	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T284	1		T267	1		T285	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T266	1		T276	1		T286	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T285	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T87	1		T270	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T271	1		T279	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	25	1			T36	1		T157	1		T117	3
class_index[0x3]	intr_timeout_cnt[1]	13	1			T68	5		T264	1		T287	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T25	1		T121	1		T109	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T71	1		T279	2		-	-
class_index[0x3]	intr_timeout_cnt[4]	1	1			T83	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T267	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T121	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T269	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T288	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T30	1		-	-		-	-