Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	301973	1			T1	3		T10	9		T11	9
all_values[1]	301973	1			T1	3		T10	9		T11	9
all_values[2]	301973	1			T1	3		T10	9		T11	9
all_values[3]	301973	1			T1	3		T10	9		T11	9

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

599754

1

T1

6

T10

22

T11

15

auto[1]

608138

1

T1

6

T10

14

T11

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

718696

1

T1

9

T10

22

T11

36

auto[1]

489196

1

T1

3

T10

14

T12

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	86837	1			T1	2		T10	6		T11	2
all_values[0]	auto[0]	auto[1]	63169	1			T1	1		T10	3		T12	1
all_values[0]	auto[1]	auto[0]	88270	1			T11	7		T12	6		T17	10
all_values[0]	auto[1]	auto[1]	63697	1			T12	5		T17	5		T13	1
all_values[1]	auto[0]	auto[0]	90713	1			T10	2		T11	5		T12	6
all_values[1]	auto[0]	auto[1]	59006	1			T10	2		T13	4		T16	4
all_values[1]	auto[1]	auto[0]	92724	1			T1	3		T10	3		T11	4
all_values[1]	auto[1]	auto[1]	59530	1			T10	2		T13	4		T16	16
all_values[2]	auto[0]	auto[0]	88075	1			T1	2		T10	1		T11	4
all_values[2]	auto[0]	auto[1]	61802	1			T1	1		T10	1		T13	6
all_values[2]	auto[1]	auto[0]	89836	1			T10	4		T11	5		T17	12
all_values[2]	auto[1]	auto[1]	62260	1			T10	3		T13	3		T16	10
all_values[3]	auto[0]	auto[0]	90604	1			T10	5		T11	4		T12	11
all_values[3]	auto[0]	auto[1]	59548	1			T10	2		T13	7		T16	7
all_values[3]	auto[1]	auto[0]	91637	1			T1	2		T10	1		T11	5
all_values[3]	auto[1]	auto[1]	60184	1			T1	1		T10	1		T13	2