Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	301973	1			T1	3		T10	9		T11	9
all_pins[1]	301973	1			T1	3		T10	9		T11	9
all_pins[2]	301973	1			T1	3		T10	9		T11	9
all_pins[3]	301973	1			T1	3		T10	9		T11	9

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	962221	1			T1	11		T10	30		T11	36
values[0x1]	245671	1			T1	1		T10	6		T12	5
transitions[0x0=>0x1]	162890	1			T1	1		T10	3		T12	5
transitions[0x1=>0x0]	163147	1			T1	1		T10	3		T12	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	238276	1			T1	3		T10	9		T11	9
all_pins[0]	values[0x1]	63697	1			T12	5		T17	5		T13	1
all_pins[0]	transitions[0x0=>0x1]	63121	1			T12	5		T17	5		T16	7
all_pins[0]	transitions[0x1=>0x0]	59865	1			T1	1		T10	1		T13	2
all_pins[1]	values[0x0]	242443	1			T1	3		T10	7		T11	9
all_pins[1]	values[0x1]	59530	1			T10	2		T13	4		T16	16
all_pins[1]	transitions[0x0=>0x1]	32348	1			T10	2		T13	4		T16	10
all_pins[1]	transitions[0x1=>0x0]	36515	1			T12	5		T17	5		T13	1
all_pins[2]	values[0x0]	239713	1			T1	3		T10	6		T11	9
all_pins[2]	values[0x1]	62260	1			T10	3		T13	3		T16	10
all_pins[2]	transitions[0x0=>0x1]	34764	1			T10	1		T13	3		T16	1
all_pins[2]	transitions[0x1=>0x0]	32034	1			T13	4		T16	7		T26	3
all_pins[3]	values[0x0]	241789	1			T1	2		T10	8		T11	9
all_pins[3]	values[0x1]	60184	1			T1	1		T10	1		T13	2
all_pins[3]	transitions[0x0=>0x1]	32657	1			T1	1		T13	1		T16	7
all_pins[3]	transitions[0x1=>0x0]	34733	1			T10	2		T13	2		T16	4