Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	92526	1			T331	112		T332	702		T333	471
accum_cnt_1000	206665	1			T15	10		T74	68		T56	10
accum_cnt_100	23629	1			T16	5		T15	8		T52	15
accum_cnt_50	63096	1			T10	2		T16	47		T15	29
accum_cnt_10	159304	1			T1	4		T10	8		T12	10
accum_cnt_0	309911	1			T1	4		T10	6		T11	32

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	223293	1			T1	2		T10	4		T11	8
class_index[0x1]	223293	1			T1	2		T10	4		T11	8
class_index[0x2]	223293	1			T1	2		T10	4		T11	8
class_index[0x3]	223293	1			T1	2		T10	4		T11	8

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22967	1			T331	20		T33	627		T334	209
class_index[0x0]	accum_cnt_1000	62524	1			T74	68		T255	1		T45	100
class_index[0x0]	accum_cnt_100	7064	1			T92	11		T74	13		T44	2
class_index[0x0]	accum_cnt_50	16263	1			T10	2		T16	14		T49	26
class_index[0x0]	accum_cnt_10	37446	1			T1	2		T12	10		T17	11
class_index[0x0]	accum_cnt_0	67769	1			T10	2		T11	8		T17	6
class_index[0x1]	accum_cnt_2000	21008	1			T331	34		T312	22		T292	205
class_index[0x1]	accum_cnt_1000	46052	1			T149	40		T82	51		T252	18
class_index[0x1]	accum_cnt_100	6188	1			T56	15		T149	14		T82	20
class_index[0x1]	accum_cnt_50	12755	1			T16	10		T15	25		T29	8
class_index[0x1]	accum_cnt_10	38614	1			T10	1		T13	13		T16	6
class_index[0x1]	accum_cnt_0	88107	1			T1	2		T10	3		T11	8
class_index[0x2]	accum_cnt_2000	25916	1			T332	444		T333	251		T292	495
class_index[0x2]	accum_cnt_1000	52904	1			T147	47		T252	2		T290	33
class_index[0x2]	accum_cnt_100	4755	1			T16	2		T52	7		T45	7
class_index[0x2]	accum_cnt_50	13811	1			T16	12		T29	2		T31	4
class_index[0x2]	accum_cnt_10	40491	1			T1	2		T10	4		T13	6
class_index[0x2]	accum_cnt_0	74669	1			T11	8		T12	10		T17	17
class_index[0x3]	accum_cnt_2000	22635	1			T331	58		T332	258		T333	220
class_index[0x3]	accum_cnt_1000	45185	1			T15	10		T56	10		T149	31
class_index[0x3]	accum_cnt_100	5622	1			T16	3		T15	8		T52	8
class_index[0x3]	accum_cnt_50	20267	1			T16	11		T15	4		T31	16
class_index[0x3]	accum_cnt_10	42753	1			T10	3		T13	15		T16	4
class_index[0x3]	accum_cnt_0	79366	1			T1	2		T10	1		T11	8