Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5439	1			T87	7		T119	3		T58	2
alert[0x1]	2211	1			T119	4		T36	1		T38	2
alert[0x2]	12491	1			T15	5		T312	121		T117	57
alert[0x3]	4351	1			T15	16		T18	1		T252	2
alert[0x4]	11978	1			T25	8		T255	1		T60	2
alert[0x5]	4708	1			T53	1		T25	5		T119	8
alert[0x6]	3760	1			T132	1		T38	1		T58	12
alert[0x7]	1669	1			T45	23		T252	5		T38	1
alert[0x8]	3530	1			T30	8		T44	9		T132	1
alert[0x9]	5416	1			T38	1		T58	2		T312	70
alert[0xa]	12606	1			T119	1		T132	1		T77	1
alert[0xb]	7558	1			T53	1		T44	41		T45	37
alert[0xc]	6466	1			T252	12		T58	17		T59	12
alert[0xd]	2401	1			T15	5		T19	1		T36	1
alert[0xe]	8014	1			T25	2		T77	23		T45	40
alert[0xf]	4521	1			T19	1		T167	1		T58	1
alert[0x10]	4990	1			T10	2		T23	1		T132	1
alert[0x11]	4676	1			T23	7		T25	24		T18	1
alert[0x12]	6496	1			T15	67		T23	2		T38	2
alert[0x13]	4072	1			T23	3		T77	4		T32	7
alert[0x14]	3842	1			T25	4		T77	4		T252	3
alert[0x15]	7545	1			T19	1		T38	1		T59	113
alert[0x16]	4753	1			T53	2		T44	6		T25	1
alert[0x17]	13786	1			T119	2		T132	1		T58	1
alert[0x18]	5369	1			T252	3		T58	11		T96	24
alert[0x19]	7081	1			T30	1		T53	5		T25	1
alert[0x1a]	8783	1			T58	62		T129	1		T254	5
alert[0x1b]	1667	1			T15	1		T87	5		T36	1
alert[0x1c]	6574	1			T25	1		T45	1		T129	2
alert[0x1d]	1979	1			T10	9		T255	1		T125	1
alert[0x1e]	5263	1			T53	17		T255	11		T59	2091
alert[0x1f]	11319	1			T15	1		T53	9		T25	1
alert[0x20]	5248	1			T15	2		T32	1		T59	15
alert[0x21]	8529	1			T119	1		T77	1		T45	14
alert[0x22]	8836	1			T125	1		T58	20		T138	1
alert[0x23]	3350	1			T255	1		T20	1		T32	3
alert[0x24]	3674	1			T119	1		T77	19		T45	31
alert[0x25]	3755	1			T25	23		T18	1		T32	9
alert[0x26]	3463	1			T15	9		T25	16		T167	1
alert[0x27]	5780	1			T32	3		T252	15		T38	1
alert[0x28]	4070	1			T59	39		T96	13		T335	22
alert[0x29]	6782	1			T132	1		T58	2		T254	1
alert[0x2a]	5263	1			T15	4		T44	3		T255	6
alert[0x2b]	4078	1			T53	11		T84	9		T25	5
alert[0x2c]	3945	1			T23	2		T25	21		T19	1
alert[0x2d]	6368	1			T25	4		T77	3		T167	1
alert[0x2e]	2848	1			T23	1		T18	1		T77	2
alert[0x2f]	4704	1			T25	1		T19	1		T36	2
alert[0x30]	3573	1			T23	1		T25	5		T19	1
alert[0x31]	5655	1			T25	3		T167	1		T36	5
alert[0x32]	6216	1			T15	3		T25	3		T19	1
alert[0x33]	2717	1			T44	1		T45	17		T125	1
alert[0x34]	3011	1			T53	1		T44	2		T36	3
alert[0x35]	3168	1			T30	4		T20	1		T59	4
alert[0x36]	8521	1			T23	2		T45	30		T252	38
alert[0x37]	1040	1			T15	69		T19	1		T45	2
alert[0x38]	8138	1			T119	1		T167	1		T36	3
alert[0x39]	5081	1			T38	1		T58	2		T129	1
alert[0x3a]	2553	1			T18	1		T20	1		T36	46
alert[0x3b]	3427	1			T119	1		T77	1		T129	1
alert[0x3c]	1468	1			T15	1		T45	1		T36	2
alert[0x3d]	3658	1			T20	1		T167	1		T58	4
alert[0x3e]	11626	1			T20	1		T132	2		T77	1
alert[0x3f]	6344	1			T30	1		T25	1		T58	2
alert[0x40]	4319	1			T132	1		T252	1		T36	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	99193	1			T10	9		T23	9		T44	62
class_i[0x1]	99033	1			T30	1		T53	26		T18	1
class_i[0x2]	59646	1			T10	2		T87	12		T53	2
class_i[0x3]	98650	1			T15	183		T30	13		T53	19

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

355901

1

T10

11

T15

183

T30

14

alert_ping_fail

621

1

T18

5

T19

8

T20

6

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5430	1			T87	7		T119	3		T58	2
alert_integrity_fail	alert[0x1]	2200	1			T119	4		T36	1		T58	2
alert_integrity_fail	alert[0x2]	12486	1			T15	5		T312	121		T117	57
alert_integrity_fail	alert[0x3]	4344	1			T15	16		T252	2		T58	1
alert_integrity_fail	alert[0x4]	11973	1			T25	8		T255	1		T60	2
alert_integrity_fail	alert[0x5]	4696	1			T53	1		T25	5		T119	8
alert_integrity_fail	alert[0x6]	3749	1			T58	12		T59	19		T312	11
alert_integrity_fail	alert[0x7]	1662	1			T45	23		T252	5		T96	11
alert_integrity_fail	alert[0x8]	3521	1			T30	8		T44	9		T45	5
alert_integrity_fail	alert[0x9]	5405	1			T58	2		T312	70		T34	23
alert_integrity_fail	alert[0xa]	12595	1			T119	1		T77	1		T59	342
alert_integrity_fail	alert[0xb]	7546	1			T53	1		T44	41		T45	37
alert_integrity_fail	alert[0xc]	6461	1			T252	12		T58	17		T59	12
alert_integrity_fail	alert[0xd]	2392	1			T15	5		T36	1		T96	21
alert_integrity_fail	alert[0xe]	8006	1			T25	2		T77	23		T45	40
alert_integrity_fail	alert[0xf]	4513	1			T58	1		T60	1		T312	10
alert_integrity_fail	alert[0x10]	4987	1			T10	2		T23	1		T252	1
alert_integrity_fail	alert[0x11]	4665	1			T23	7		T25	24		T252	1
alert_integrity_fail	alert[0x12]	6485	1			T15	67		T23	2		T312	314
alert_integrity_fail	alert[0x13]	4060	1			T23	3		T77	4		T32	7
alert_integrity_fail	alert[0x14]	3837	1			T25	4		T77	4		T252	3
alert_integrity_fail	alert[0x15]	7529	1			T59	113		T96	1		T62	31
alert_integrity_fail	alert[0x16]	4736	1			T53	2		T44	6		T25	1
alert_integrity_fail	alert[0x17]	13777	1			T119	2		T58	1		T335	26
alert_integrity_fail	alert[0x18]	5363	1			T252	3		T58	11		T96	24
alert_integrity_fail	alert[0x19]	7073	1			T30	1		T53	5		T25	1
alert_integrity_fail	alert[0x1a]	8771	1			T58	62		T254	5		T159	29
alert_integrity_fail	alert[0x1b]	1658	1			T15	1		T87	5		T36	1
alert_integrity_fail	alert[0x1c]	6561	1			T25	1		T45	1		T312	22
alert_integrity_fail	alert[0x1d]	1970	1			T10	9		T255	1		T335	28
alert_integrity_fail	alert[0x1e]	5260	1			T53	17		T255	11		T59	2091
alert_integrity_fail	alert[0x1f]	11305	1			T15	1		T53	9		T25	1
alert_integrity_fail	alert[0x20]	5239	1			T15	2		T32	1		T59	15
alert_integrity_fail	alert[0x21]	8518	1			T119	1		T77	1		T45	14
alert_integrity_fail	alert[0x22]	8819	1			T58	20		T314	6		T34	299
alert_integrity_fail	alert[0x23]	3335	1			T255	1		T32	3		T45	2
alert_integrity_fail	alert[0x24]	3665	1			T119	1		T77	19		T45	31
alert_integrity_fail	alert[0x25]	3745	1			T25	23		T32	9		T59	47
alert_integrity_fail	alert[0x26]	3457	1			T15	9		T25	16		T59	100
alert_integrity_fail	alert[0x27]	5772	1			T32	3		T252	15		T59	420
alert_integrity_fail	alert[0x28]	4065	1			T59	39		T96	13		T335	22
alert_integrity_fail	alert[0x29]	6770	1			T58	2		T254	1		T335	378
alert_integrity_fail	alert[0x2a]	5256	1			T15	4		T44	3		T255	6
alert_integrity_fail	alert[0x2b]	4068	1			T53	11		T84	9		T25	5
alert_integrity_fail	alert[0x2c]	3932	1			T23	2		T25	21		T77	1
alert_integrity_fail	alert[0x2d]	6359	1			T25	4		T77	3		T59	144
alert_integrity_fail	alert[0x2e]	2836	1			T23	1		T77	2		T117	37
alert_integrity_fail	alert[0x2f]	4688	1			T25	1		T36	2		T58	1
alert_integrity_fail	alert[0x30]	3565	1			T23	1		T25	5		T45	5
alert_integrity_fail	alert[0x31]	5640	1			T25	3		T36	5		T59	55
alert_integrity_fail	alert[0x32]	6209	1			T15	3		T25	3		T45	2
alert_integrity_fail	alert[0x33]	2707	1			T44	1		T45	17		T59	32
alert_integrity_fail	alert[0x34]	3003	1			T53	1		T44	2		T36	3
alert_integrity_fail	alert[0x35]	3157	1			T30	4		T59	4		T60	3
alert_integrity_fail	alert[0x36]	8512	1			T23	2		T45	30		T252	38
alert_integrity_fail	alert[0x37]	1027	1			T15	69		T45	2		T117	85
alert_integrity_fail	alert[0x38]	8127	1			T119	1		T36	3		T58	2
alert_integrity_fail	alert[0x39]	5074	1			T58	2		T59	608		T139	116
alert_integrity_fail	alert[0x3a]	2542	1			T36	46		T312	112		T117	816
alert_integrity_fail	alert[0x3b]	3421	1			T119	1		T77	1		T59	17
alert_integrity_fail	alert[0x3c]	1457	1			T15	1		T45	1		T36	2
alert_integrity_fail	alert[0x3d]	3648	1			T58	4		T60	2		T336	3
alert_integrity_fail	alert[0x3e]	11615	1			T77	1		T58	5		T312	603
alert_integrity_fail	alert[0x3f]	6341	1			T30	1		T25	1		T58	2
alert_integrity_fail	alert[0x40]	4316	1			T252	1		T36	1		T58	3
alert_ping_fail	alert[0x0]	9	1			T129	1		T337	1		T140	2
alert_ping_fail	alert[0x1]	11	1			T38	2		T138	1		T338	1
alert_ping_fail	alert[0x2]	5	1			T337	1		T140	1		T339	1
alert_ping_fail	alert[0x3]	7	1			T18	1		T340	1		T305	1
alert_ping_fail	alert[0x4]	5	1			T341	1		T342	2		T343	1
alert_ping_fail	alert[0x5]	12	1			T125	1		T129	1		T344	1
alert_ping_fail	alert[0x6]	11	1			T132	1		T38	1		T127	1
alert_ping_fail	alert[0x7]	7	1			T38	1		T345	1		T305	1
alert_ping_fail	alert[0x8]	9	1			T132	1		T38	1		T330	1
alert_ping_fail	alert[0x9]	11	1			T38	1		T341	2		T343	1
alert_ping_fail	alert[0xa]	11	1			T132	1		T167	1		T328	1
alert_ping_fail	alert[0xb]	12	1			T125	1		T346	1		T347	1
alert_ping_fail	alert[0xc]	5	1			T348	1		T339	1		T349	1
alert_ping_fail	alert[0xd]	9	1			T19	1		T340	1		T350	1
alert_ping_fail	alert[0xe]	8	1			T337	1		T345	1		T339	1
alert_ping_fail	alert[0xf]	8	1			T19	1		T167	1		T338	1
alert_ping_fail	alert[0x10]	3	1			T132	1		T351	1		T352	1
alert_ping_fail	alert[0x11]	11	1			T18	1		T167	1		T125	1
alert_ping_fail	alert[0x12]	11	1			T38	2		T129	1		T116	1
alert_ping_fail	alert[0x13]	12	1			T323	1		T353	1		T339	2
alert_ping_fail	alert[0x14]	5	1			T346	1		T354	1		T349	1
alert_ping_fail	alert[0x15]	16	1			T19	1		T38	1		T345	1
alert_ping_fail	alert[0x16]	17	1			T20	1		T167	2		T293	2
alert_ping_fail	alert[0x17]	9	1			T132	1		T116	1		T340	1
alert_ping_fail	alert[0x18]	6	1			T305	1		T339	1		T354	1
alert_ping_fail	alert[0x19]	8	1			T167	1		T354	1		T350	1
alert_ping_fail	alert[0x1a]	12	1			T129	1		T355	1		T345	1
alert_ping_fail	alert[0x1b]	9	1			T345	1		T351	1		T350	1
alert_ping_fail	alert[0x1c]	13	1			T129	2		T355	1		T340	1
alert_ping_fail	alert[0x1d]	9	1			T125	1		T338	1		T351	1
alert_ping_fail	alert[0x1e]	3	1			T337	1		T339	1		T356	1
alert_ping_fail	alert[0x1f]	14	1			T167	1		T129	1		T357	2
alert_ping_fail	alert[0x20]	9	1			T340	1		T358	1		T338	1
alert_ping_fail	alert[0x21]	11	1			T167	1		T116	1		T359	1
alert_ping_fail	alert[0x22]	17	1			T125	1		T138	1		T359	1
alert_ping_fail	alert[0x23]	15	1			T20	1		T129	1		T340	1
alert_ping_fail	alert[0x24]	9	1			T129	1		T116	1		T353	1
alert_ping_fail	alert[0x25]	10	1			T18	1		T125	1		T116	1
alert_ping_fail	alert[0x26]	6	1			T167	1		T353	1		T347	1
alert_ping_fail	alert[0x27]	8	1			T38	1		T345	1		T305	1
alert_ping_fail	alert[0x28]	5	1			T345	1		T327	1		T328	1
alert_ping_fail	alert[0x29]	12	1			T132	1		T345	1		T347	1
alert_ping_fail	alert[0x2a]	7	1			T353	1		T140	2		T341	2
alert_ping_fail	alert[0x2b]	10	1			T132	1		T340	2		T350	1
alert_ping_fail	alert[0x2c]	13	1			T19	1		T38	1		T355	1
alert_ping_fail	alert[0x2d]	9	1			T167	1		T125	1		T129	1
alert_ping_fail	alert[0x2e]	12	1			T18	1		T167	1		T38	1
alert_ping_fail	alert[0x2f]	16	1			T19	1		T38	2		T129	1
alert_ping_fail	alert[0x30]	8	1			T19	1		T340	1		T350	1
alert_ping_fail	alert[0x31]	15	1			T167	1		T38	1		T127	1
alert_ping_fail	alert[0x32]	7	1			T19	1		T132	1		T140	2
alert_ping_fail	alert[0x33]	10	1			T125	1		T116	2		T350	1
alert_ping_fail	alert[0x34]	8	1			T127	2		T293	1		T348	2
alert_ping_fail	alert[0x35]	11	1			T20	1		T116	2		T337	1
alert_ping_fail	alert[0x36]	9	1			T38	1		T125	1		T345	2
alert_ping_fail	alert[0x37]	13	1			T19	1		T167	2		T125	1
alert_ping_fail	alert[0x38]	11	1			T167	1		T38	1		T129	1
alert_ping_fail	alert[0x39]	7	1			T38	1		T129	1		T340	1
alert_ping_fail	alert[0x3a]	11	1			T18	1		T20	1		T337	1
alert_ping_fail	alert[0x3b]	6	1			T129	1		T305	1		T338	1
alert_ping_fail	alert[0x3c]	11	1			T129	1		T116	2		T340	1
alert_ping_fail	alert[0x3d]	10	1			T20	1		T167	1		T293	1
alert_ping_fail	alert[0x3e]	11	1			T20	1		T132	2		T129	1
alert_ping_fail	alert[0x3f]	3	1			T345	1		T360	1		T361	1
alert_ping_fail	alert[0x40]	3	1			T132	1		T38	1		T342	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	99033	1			T10	9		T23	9		T44	62
alert_integrity_fail	class_i[0x1]	98837	1			T30	1		T53	26		T32	23
alert_integrity_fail	class_i[0x2]	59558	1			T10	2		T87	12		T53	2
alert_integrity_fail	class_i[0x3]	98473	1			T15	183		T30	13		T53	19
alert_ping_fail	class_i[0x0]	160	1			T18	3		T19	6		T20	1
alert_ping_fail	class_i[0x1]	196	1			T18	1		T20	2		T132	10
alert_ping_fail	class_i[0x2]	88	1			T18	1		T132	1		T38	1
alert_ping_fail	class_i[0x3]	177	1			T19	2		T20	3		T167	1