| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.26 | 99.99 | 98.72 | 97.09 | 100.00 | 100.00 | 99.38 | 99.64 |
| T793 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4264267151 | Sep 09 05:23:46 PM UTC 24 | Sep 09 05:24:04 PM UTC 24 | 297517086 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4125005529 | Sep 09 05:23:58 PM UTC 24 | Sep 09 05:24:06 PM UTC 24 | 68218864 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.3287467257 | Sep 09 05:23:54 PM UTC 24 | Sep 09 05:24:07 PM UTC 24 | 242501347 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.3899422030 | Sep 09 05:24:07 PM UTC 24 | Sep 09 05:24:10 PM UTC 24 | 12985355 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1517319378 | Sep 09 05:21:58 PM UTC 24 | Sep 09 05:24:10 PM UTC 24 | 2606610373 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2767023883 | Sep 09 05:24:08 PM UTC 24 | Sep 09 05:24:11 PM UTC 24 | 10834095 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2042359128 | Sep 09 05:22:37 PM UTC 24 | Sep 09 05:24:14 PM UTC 24 | 4060318037 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.4258748621 | Sep 09 05:24:11 PM UTC 24 | Sep 09 05:24:14 PM UTC 24 | 12482875 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.468002777 | Sep 09 05:24:11 PM UTC 24 | Sep 09 05:24:14 PM UTC 24 | 8136363 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3626788816 | Sep 09 05:24:06 PM UTC 24 | Sep 09 05:24:15 PM UTC 24 | 290290830 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2635902652 | Sep 09 05:24:12 PM UTC 24 | Sep 09 05:24:16 PM UTC 24 | 20052109 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.1240038303 | Sep 09 05:24:01 PM UTC 24 | Sep 09 05:24:16 PM UTC 24 | 137244101 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.2676328895 | Sep 09 05:24:14 PM UTC 24 | Sep 09 05:24:18 PM UTC 24 | 10702366 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.2927604314 | Sep 09 05:24:16 PM UTC 24 | Sep 09 05:24:19 PM UTC 24 | 11728583 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.3655514518 | Sep 09 05:24:15 PM UTC 24 | Sep 09 05:24:19 PM UTC 24 | 8909390 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.3332173249 | Sep 09 05:24:16 PM UTC 24 | Sep 09 05:24:19 PM UTC 24 | 11075011 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.1266775333 | Sep 09 05:24:17 PM UTC 24 | Sep 09 05:24:20 PM UTC 24 | 6688511 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2076023704 | Sep 09 05:24:17 PM UTC 24 | Sep 09 05:24:20 PM UTC 24 | 11382151 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1601763552 | Sep 09 05:24:19 PM UTC 24 | Sep 09 05:24:22 PM UTC 24 | 8568290 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.487323021 | Sep 09 05:24:19 PM UTC 24 | Sep 09 05:24:22 PM UTC 24 | 9841818 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3690558551 | Sep 09 05:24:20 PM UTC 24 | Sep 09 05:24:23 PM UTC 24 | 14210666 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.848451204 | Sep 09 05:24:20 PM UTC 24 | Sep 09 05:24:23 PM UTC 24 | 10990152 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.642931416 | Sep 09 05:24:21 PM UTC 24 | Sep 09 05:24:24 PM UTC 24 | 7612818 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.2026878776 | Sep 09 05:24:21 PM UTC 24 | Sep 09 05:24:25 PM UTC 24 | 9274050 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.623386185 | Sep 09 05:23:37 PM UTC 24 | Sep 09 05:24:26 PM UTC 24 | 353897009 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.4279095078 | Sep 09 05:24:24 PM UTC 24 | Sep 09 05:24:26 PM UTC 24 | 24873361 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.2160606181 | Sep 09 05:24:24 PM UTC 24 | Sep 09 05:24:27 PM UTC 24 | 10716062 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.3296677445 | Sep 09 05:24:24 PM UTC 24 | Sep 09 05:24:27 PM UTC 24 | 11303783 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.907925646 | Sep 09 05:24:24 PM UTC 24 | Sep 09 05:24:27 PM UTC 24 | 17826894 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.3135759741 | Sep 09 05:24:25 PM UTC 24 | Sep 09 05:24:28 PM UTC 24 | 7162420 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2868875695 | Sep 09 05:22:20 PM UTC 24 | Sep 09 05:24:29 PM UTC 24 | 7692116291 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.293239176 | Sep 09 05:24:26 PM UTC 24 | Sep 09 05:24:29 PM UTC 24 | 8835779 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.2834510238 | Sep 09 05:24:27 PM UTC 24 | Sep 09 05:24:30 PM UTC 24 | 13291750 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2268204747 | Sep 09 05:24:27 PM UTC 24 | Sep 09 05:24:30 PM UTC 24 | 8903303 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.576965765 | Sep 09 05:24:27 PM UTC 24 | Sep 09 05:24:31 PM UTC 24 | 20552296 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.2702577845 | Sep 09 05:24:27 PM UTC 24 | Sep 09 05:24:31 PM UTC 24 | 11328103 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.789692974 | Sep 09 05:24:29 PM UTC 24 | Sep 09 05:24:32 PM UTC 24 | 20210144 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.2966981760 | Sep 09 05:24:29 PM UTC 24 | Sep 09 05:24:32 PM UTC 24 | 14749994 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.491371264 | Sep 09 05:21:11 PM UTC 24 | Sep 09 05:24:32 PM UTC 24 | 1571027313 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.3906576536 | Sep 09 05:24:30 PM UTC 24 | Sep 09 05:24:33 PM UTC 24 | 8582015 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.65363989 | Sep 09 05:24:04 PM UTC 24 | Sep 09 05:24:37 PM UTC 24 | 203735838 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1915446957 | Sep 09 05:23:44 PM UTC 24 | Sep 09 05:24:39 PM UTC 24 | 538691101 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1748330080 | Sep 09 05:21:12 PM UTC 24 | Sep 09 05:24:39 PM UTC 24 | 3720711153 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.21779187 | Sep 09 05:21:28 PM UTC 24 | Sep 09 05:24:45 PM UTC 24 | 3015997982 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2049980373 | Sep 09 05:21:13 PM UTC 24 | Sep 09 05:24:49 PM UTC 24 | 9413722748 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4247143657 | Sep 09 05:21:11 PM UTC 24 | Sep 09 05:24:53 PM UTC 24 | 13868398017 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2514811132 | Sep 09 05:21:57 PM UTC 24 | Sep 09 05:24:55 PM UTC 24 | 8057699682 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1849271784 | Sep 09 05:21:06 PM UTC 24 | Sep 09 05:24:56 PM UTC 24 | 6754968952 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.87173507 | Sep 09 05:21:40 PM UTC 24 | Sep 09 05:24:57 PM UTC 24 | 4175928805 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.724670379 | Sep 09 05:21:14 PM UTC 24 | Sep 09 05:25:05 PM UTC 24 | 11879767799 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2538740768 | Sep 09 05:21:17 PM UTC 24 | Sep 09 05:25:47 PM UTC 24 | 13729411065 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.138433425 | Sep 09 05:21:14 PM UTC 24 | Sep 09 05:26:00 PM UTC 24 | 18405175059 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4161602535 | Sep 09 05:21:21 PM UTC 24 | Sep 09 05:26:08 PM UTC 24 | 11868671098 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3159553105 | Sep 09 05:21:35 PM UTC 24 | Sep 09 05:26:13 PM UTC 24 | 89731422653 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3557531735 | Sep 09 05:21:21 PM UTC 24 | Sep 09 05:26:23 PM UTC 24 | 2311804803 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.592365493 | Sep 09 05:21:47 PM UTC 24 | Sep 09 05:26:31 PM UTC 24 | 4458005911 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.940423373 | Sep 09 05:21:13 PM UTC 24 | Sep 09 05:26:51 PM UTC 24 | 18982437188 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4076230779 | Sep 09 05:22:03 PM UTC 24 | Sep 09 05:27:02 PM UTC 24 | 8696342401 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.860448203 | Sep 09 05:22:33 PM UTC 24 | Sep 09 05:27:22 PM UTC 24 | 9044409230 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.266844421 | Sep 09 05:22:30 PM UTC 24 | Sep 09 05:27:28 PM UTC 24 | 2184276272 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1892587442 | Sep 09 05:22:18 PM UTC 24 | Sep 09 05:27:36 PM UTC 24 | 8367149588 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3458112143 | Sep 09 05:21:34 PM UTC 24 | Sep 09 05:27:39 PM UTC 24 | 9148846948 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3306850849 | Sep 09 05:21:08 PM UTC 24 | Sep 09 05:27:48 PM UTC 24 | 28179651629 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3061022637 | Sep 09 05:22:03 PM UTC 24 | Sep 09 05:27:57 PM UTC 24 | 9177133287 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2515043510 | Sep 09 05:22:59 PM UTC 24 | Sep 09 05:28:33 PM UTC 24 | 17280346559 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2101170408 | Sep 09 05:23:15 PM UTC 24 | Sep 09 05:28:36 PM UTC 24 | 7848233409 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3449744542 | Sep 09 05:21:07 PM UTC 24 | Sep 09 05:28:36 PM UTC 24 | 6656302726 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3734781324 | Sep 09 05:21:18 PM UTC 24 | Sep 09 05:28:53 PM UTC 24 | 20245201217 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2762991520 | Sep 09 05:22:48 PM UTC 24 | Sep 09 05:29:00 PM UTC 24 | 19912547398 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2863180077 | Sep 09 05:22:59 PM UTC 24 | Sep 09 05:29:10 PM UTC 24 | 39556785156 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.359287116 | Sep 09 05:23:53 PM UTC 24 | Sep 09 05:29:11 PM UTC 24 | 16826634219 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2975453490 | Sep 09 05:23:15 PM UTC 24 | Sep 09 05:29:19 PM UTC 24 | 37333420111 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3396732697 | Sep 09 05:21:40 PM UTC 24 | Sep 09 05:30:10 PM UTC 24 | 7552881196 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3078212007 | Sep 09 05:23:30 PM UTC 24 | Sep 09 05:30:41 PM UTC 24 | 42224843967 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.626703420 | Sep 09 05:21:14 PM UTC 24 | Sep 09 05:31:08 PM UTC 24 | 4657982679 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.47379806 | Sep 09 05:21:17 PM UTC 24 | Sep 09 05:31:27 PM UTC 24 | 9399112292 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1463664728 | Sep 09 05:21:45 PM UTC 24 | Sep 09 05:31:32 PM UTC 24 | 24436102948 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3560572111 | Sep 09 05:21:27 PM UTC 24 | Sep 09 05:31:35 PM UTC 24 | 18154932158 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.854369851 | Sep 09 05:21:11 PM UTC 24 | Sep 09 05:32:09 PM UTC 24 | 28679026706 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1433237423 | Sep 09 05:21:13 PM UTC 24 | Sep 09 05:32:44 PM UTC 24 | 13765336378 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.635365611 | Sep 09 05:20:52 PM UTC 24 | Sep 09 05:34:43 PM UTC 24 | 48389189535 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.19287302 | Sep 09 05:21:54 PM UTC 24 | Sep 09 05:38:59 PM UTC 24 | 17710398353 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2122605738 | Sep 09 05:22:41 PM UTC 24 | Sep 09 05:41:29 PM UTC 24 | 34197731310 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2417218164 | Sep 09 05:23:51 PM UTC 24 | Sep 09 05:42:20 PM UTC 24 | 18068694844 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3611189188 | Sep 09 05:23:29 PM UTC 24 | Sep 09 05:44:53 PM UTC 24 | 51275371048 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.610571416 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1161904687 ps |
| CPU time | 27.82 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:46:44 AM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610571416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.610571416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.2593104678 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1600767605 ps |
| CPU time | 31.17 seconds |
| Started | Sep 09 11:46:18 AM UTC 24 |
| Finished | Sep 09 11:46:50 AM UTC 24 |
| Peak memory | 295468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593104678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2593104678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all_with_rand_reset.4234635856 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5121421058 ps |
| CPU time | 288.49 seconds |
| Started | Sep 09 11:51:09 AM UTC 24 |
| Finished | Sep 09 11:56:01 AM UTC 24 |
| Peak memory | 279804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4234635856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.al ert_handler_stress_all_with_rand_reset.4234635856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.2095232846 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2394129840 ps |
| CPU time | 14.72 seconds |
| Started | Sep 09 11:46:16 AM UTC 24 |
| Finished | Sep 09 11:46:32 AM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095232846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2095232846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.2423650665 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 535784867 ps |
| CPU time | 52.09 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:47:09 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423650665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2423650665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2698478883 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 183595536 ps |
| CPU time | 21.64 seconds |
| Started | Sep 09 05:21:15 PM UTC 24 |
| Finished | Sep 09 05:21:38 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698478883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2698478883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.3662823677 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 895643372 ps |
| CPU time | 23.26 seconds |
| Started | Sep 09 11:46:23 AM UTC 24 |
| Finished | Sep 09 11:46:48 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662823677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3662823677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.2636721232 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 20369807195 ps |
| CPU time | 354.81 seconds |
| Started | Sep 09 11:46:45 AM UTC 24 |
| Finished | Sep 09 11:52:44 AM UTC 24 |
| Peak memory | 283968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2636721232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.al ert_handler_stress_all_with_rand_reset.2636721232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3306850849 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 28179651629 ps |
| CPU time | 394.18 seconds |
| Started | Sep 09 05:21:08 PM UTC 24 |
| Finished | Sep 09 05:27:48 PM UTC 24 |
| Peak memory | 279184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306850849 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.3306850849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.4258267021 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 31085138386 ps |
| CPU time | 2308.01 seconds |
| Started | Sep 09 11:47:43 AM UTC 24 |
| Finished | Sep 09 12:26:38 PM UTC 24 |
| Peak memory | 302556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258267021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.4258267021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.1264350357 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 126449793533 ps |
| CPU time | 1796.05 seconds |
| Started | Sep 09 11:46:14 AM UTC 24 |
| Finished | Sep 09 12:16:30 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264350357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1264350357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.3181496930 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 853364385 ps |
| CPU time | 9.33 seconds |
| Started | Sep 09 05:21:10 PM UTC 24 |
| Finished | Sep 09 05:21:20 PM UTC 24 |
| Peak memory | 250472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181496930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3181496930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4161602535 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 11868671098 ps |
| CPU time | 282.54 seconds |
| Started | Sep 09 05:21:21 PM UTC 24 |
| Finished | Sep 09 05:26:08 PM UTC 24 |
| Peak memory | 279536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161602535 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.4161602535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.946352504 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13981656651 ps |
| CPU time | 545.37 seconds |
| Started | Sep 09 11:46:55 AM UTC 24 |
| Finished | Sep 09 11:56:06 AM UTC 24 |
| Peak memory | 263044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946352504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.946352504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.2588142041 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 52247517179 ps |
| CPU time | 1364.05 seconds |
| Started | Sep 09 01:39:50 PM UTC 24 |
| Finished | Sep 09 02:02:50 PM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588142041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2588142041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.1241239494 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 7575711522 ps |
| CPU time | 676.17 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:57:39 AM UTC 24 |
| Peak memory | 279352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241239494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1241239494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all_with_rand_reset.4208408735 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2126441122 ps |
| CPU time | 114.07 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:48:11 AM UTC 24 |
| Peak memory | 279484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4208408735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.al ert_handler_stress_all_with_rand_reset.4208408735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.3926389024 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 62974601599 ps |
| CPU time | 1888.52 seconds |
| Started | Sep 09 11:48:22 AM UTC 24 |
| Finished | Sep 09 12:20:11 PM UTC 24 |
| Peak memory | 299832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926389024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3926389024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1463664728 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 24436102948 ps |
| CPU time | 578.97 seconds |
| Started | Sep 09 05:21:45 PM UTC 24 |
| Finished | Sep 09 05:31:32 PM UTC 24 |
| Peak memory | 285604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463664728 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad ow_reg_errors_with_csr_rw.1463664728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3159553105 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 89731422653 ps |
| CPU time | 274.62 seconds |
| Started | Sep 09 05:21:35 PM UTC 24 |
| Finished | Sep 09 05:26:13 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159553105 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.3159553105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.2458903469 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 51689017361 ps |
| CPU time | 3140.04 seconds |
| Started | Sep 09 12:12:13 PM UTC 24 |
| Finished | Sep 09 01:05:12 PM UTC 24 |
| Peak memory | 304680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458903469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2458903469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.1777526675 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 12450251 ps |
| CPU time | 2.02 seconds |
| Started | Sep 09 05:21:15 PM UTC 24 |
| Finished | Sep 09 05:21:18 PM UTC 24 |
| Peak memory | 250416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777526675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1777526675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.1846079395 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 531176274 ps |
| CPU time | 31.26 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:46:48 AM UTC 24 |
| Peak memory | 263264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846079395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1846079395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2122605738 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 34197731310 ps |
| CPU time | 1114.38 seconds |
| Started | Sep 09 05:22:41 PM UTC 24 |
| Finished | Sep 09 05:41:29 PM UTC 24 |
| Peak memory | 282112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122605738 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shad ow_reg_errors_with_csr_rw.2122605738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.2712318558 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 245589808544 ps |
| CPU time | 1156.79 seconds |
| Started | Sep 09 11:47:05 AM UTC 24 |
| Finished | Sep 09 12:06:35 PM UTC 24 |
| Peak memory | 301956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712318558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2712318558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.1873936792 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 57218604394 ps |
| CPU time | 1769.28 seconds |
| Started | Sep 09 12:16:52 PM UTC 24 |
| Finished | Sep 09 12:46:41 PM UTC 24 |
| Peak memory | 299248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873936792 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.1873936792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.4074585314 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 29313287318 ps |
| CPU time | 1683.61 seconds |
| Started | Sep 09 11:46:14 AM UTC 24 |
| Finished | Sep 09 12:14:36 PM UTC 24 |
| Peak memory | 288616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074585314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.4074585314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.4144898141 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 20598904 ps |
| CPU time | 3.95 seconds |
| Started | Sep 09 05:21:12 PM UTC 24 |
| Finished | Sep 09 05:21:18 PM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144898141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4144898141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.491371264 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1571027313 ps |
| CPU time | 196.93 seconds |
| Started | Sep 09 05:21:11 PM UTC 24 |
| Finished | Sep 09 05:24:32 PM UTC 24 |
| Peak memory | 279472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491371264 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.491371264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.3932344181 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 13116120654 ps |
| CPU time | 387.63 seconds |
| Started | Sep 09 11:50:15 AM UTC 24 |
| Finished | Sep 09 11:56:48 AM UTC 24 |
| Peak memory | 263300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932344181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3932344181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.489774875 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 59710109741 ps |
| CPU time | 1466.84 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 12:10:59 PM UTC 24 |
| Peak memory | 301888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489774875 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.489774875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.115746202 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 55781060670 ps |
| CPU time | 605.79 seconds |
| Started | Sep 09 12:57:34 PM UTC 24 |
| Finished | Sep 09 01:07:46 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115746202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.115746202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.635365611 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 48389189535 ps |
| CPU time | 820.55 seconds |
| Started | Sep 09 05:20:52 PM UTC 24 |
| Finished | Sep 09 05:34:43 PM UTC 24 |
| Peak memory | 288396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635365611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow _reg_errors_with_csr_rw.635365611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.3642279257 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 37430721240 ps |
| CPU time | 2345.11 seconds |
| Started | Sep 09 11:47:47 AM UTC 24 |
| Finished | Sep 09 12:27:18 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642279257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3642279257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.1093200018 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 751144773 ps |
| CPU time | 38.31 seconds |
| Started | Sep 09 11:46:24 AM UTC 24 |
| Finished | Sep 09 11:47:04 AM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093200018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1093200018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.2210132628 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 158875279196 ps |
| CPU time | 982.93 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 12:02:49 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210132628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2210132628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.3480982738 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 140770710478 ps |
| CPU time | 2305.44 seconds |
| Started | Sep 09 11:55:14 AM UTC 24 |
| Finished | Sep 09 12:34:07 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480982738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3480982738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4076230779 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 8696342401 ps |
| CPU time | 294.63 seconds |
| Started | Sep 09 05:22:03 PM UTC 24 |
| Finished | Sep 09 05:27:02 PM UTC 24 |
| Peak memory | 279536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076230779 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.4076230779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all_with_rand_reset.209338490 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1909598091 ps |
| CPU time | 153.32 seconds |
| Started | Sep 09 11:46:18 AM UTC 24 |
| Finished | Sep 09 11:48:54 AM UTC 24 |
| Peak memory | 285956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=209338490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ale rt_handler_stress_all_with_rand_reset.209338490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.4207235782 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 23211267111 ps |
| CPU time | 465.59 seconds |
| Started | Sep 09 11:46:14 AM UTC 24 |
| Finished | Sep 09 11:54:05 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207235782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.4207235782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.1426800825 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1287756211 ps |
| CPU time | 55.96 seconds |
| Started | Sep 09 01:05:15 PM UTC 24 |
| Finished | Sep 09 01:06:12 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426800825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1426800825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2610858136 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 942584535 ps |
| CPU time | 47.98 seconds |
| Started | Sep 09 05:21:13 PM UTC 24 |
| Finished | Sep 09 05:22:03 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610858136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2610858136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.122652237 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 82824794743 ps |
| CPU time | 639.07 seconds |
| Started | Sep 09 01:09:57 PM UTC 24 |
| Finished | Sep 09 01:20:44 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122652237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.122652237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.2569062906 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1172662577146 ps |
| CPU time | 3425.55 seconds |
| Started | Sep 09 11:53:05 AM UTC 24 |
| Finished | Sep 09 12:50:49 PM UTC 24 |
| Peak memory | 320992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569062906 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.2569062906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.650938518 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 70448615376 ps |
| CPU time | 3880.08 seconds |
| Started | Sep 09 11:47:58 AM UTC 24 |
| Finished | Sep 09 12:53:18 PM UTC 24 |
| Peak memory | 321320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650938518 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.650938518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3611189188 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 51275371048 ps |
| CPU time | 1268.04 seconds |
| Started | Sep 09 05:23:29 PM UTC 24 |
| Finished | Sep 09 05:44:53 PM UTC 24 |
| Peak memory | 282108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611189188 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shad ow_reg_errors_with_csr_rw.3611189188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.536688782 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 9493697 ps |
| CPU time | 2.38 seconds |
| Started | Sep 09 05:21:24 PM UTC 24 |
| Finished | Sep 09 05:21:28 PM UTC 24 |
| Peak memory | 250420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536688782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.536688782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.1322863527 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 192729499776 ps |
| CPU time | 2814.75 seconds |
| Started | Sep 09 01:46:27 PM UTC 24 |
| Finished | Sep 09 02:33:51 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322863527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1322863527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3458112143 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 9148846948 ps |
| CPU time | 360.07 seconds |
| Started | Sep 09 05:21:34 PM UTC 24 |
| Finished | Sep 09 05:27:39 PM UTC 24 |
| Peak memory | 279600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458112143 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shado w_reg_errors_with_csr_rw.3458112143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.1237361898 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 22776756229 ps |
| CPU time | 118.94 seconds |
| Started | Sep 09 12:11:45 PM UTC 24 |
| Finished | Sep 09 12:13:46 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237361898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1237361898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.1313058044 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 51852882922 ps |
| CPU time | 3237.31 seconds |
| Started | Sep 09 12:42:38 PM UTC 24 |
| Finished | Sep 09 01:37:10 PM UTC 24 |
| Peak memory | 304928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313058044 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.1313058044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.3242116746 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1780666771 ps |
| CPU time | 43.31 seconds |
| Started | Sep 09 01:17:32 PM UTC 24 |
| Finished | Sep 09 01:18:16 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242116746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3242116746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.2717856588 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 22727541853 ps |
| CPU time | 385.89 seconds |
| Started | Sep 09 11:47:09 AM UTC 24 |
| Finished | Sep 09 11:53:40 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717856588 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.2717856588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.2413318056 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 5266624836 ps |
| CPU time | 59.13 seconds |
| Started | Sep 09 11:46:50 AM UTC 24 |
| Finished | Sep 09 11:47:51 AM UTC 24 |
| Peak memory | 269472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413318056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2413318056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.479428905 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 234103070908 ps |
| CPU time | 3583.11 seconds |
| Started | Sep 09 12:33:33 PM UTC 24 |
| Finished | Sep 09 01:33:55 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479428905 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.479428905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.2895771518 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 222144708569 ps |
| CPU time | 1698.29 seconds |
| Started | Sep 09 01:10:54 PM UTC 24 |
| Finished | Sep 09 01:39:32 PM UTC 24 |
| Peak memory | 316540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895771518 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.2895771518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3020069208 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 191088096 ps |
| CPU time | 4.53 seconds |
| Started | Sep 09 05:23:23 PM UTC 24 |
| Finished | Sep 09 05:23:28 PM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020069208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3020069208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.47379806 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 9399112292 ps |
| CPU time | 601.75 seconds |
| Started | Sep 09 05:21:17 PM UTC 24 |
| Finished | Sep 09 05:31:27 PM UTC 24 |
| Peak memory | 279468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47379806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_ reg_errors_with_csr_rw.47379806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.985279531 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 175565555 ps |
| CPU time | 3.05 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:46:19 AM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985279531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.985279531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.842002567 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 39792613 ps |
| CPU time | 3.23 seconds |
| Started | Sep 09 11:46:18 AM UTC 24 |
| Finished | Sep 09 11:46:22 AM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842002567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.842002567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.2113192410 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 253430212 ps |
| CPU time | 6.16 seconds |
| Started | Sep 09 11:57:41 AM UTC 24 |
| Finished | Sep 09 11:57:48 AM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113192410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2113192410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.4218229455 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 33130962 ps |
| CPU time | 5.08 seconds |
| Started | Sep 09 12:03:09 PM UTC 24 |
| Finished | Sep 09 12:03:15 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218229455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.4218229455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.2706094838 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 34556041165 ps |
| CPU time | 293.52 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:51:13 AM UTC 24 |
| Peak memory | 263300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706094838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2706094838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.3422682603 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 25940508448 ps |
| CPU time | 1897.99 seconds |
| Started | Sep 09 11:56:55 AM UTC 24 |
| Finished | Sep 09 12:28:55 PM UTC 24 |
| Peak memory | 285824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422682603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3422682603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.563423781 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 12916671040 ps |
| CPU time | 1740.57 seconds |
| Started | Sep 09 12:24:19 PM UTC 24 |
| Finished | Sep 09 12:53:41 PM UTC 24 |
| Peak memory | 304672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563423781 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.563423781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.844396391 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 368143511780 ps |
| CPU time | 2843.61 seconds |
| Started | Sep 09 12:41:58 PM UTC 24 |
| Finished | Sep 09 01:29:55 PM UTC 24 |
| Peak memory | 304676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844396391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.844396391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.2020047024 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 111491412275 ps |
| CPU time | 668.7 seconds |
| Started | Sep 09 01:00:49 PM UTC 24 |
| Finished | Sep 09 01:12:05 PM UTC 24 |
| Peak memory | 263176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020047024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2020047024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.773148707 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 401519930620 ps |
| CPU time | 2478.31 seconds |
| Started | Sep 09 01:05:22 PM UTC 24 |
| Finished | Sep 09 01:47:06 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773148707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.773148707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.1889014068 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 198585227293 ps |
| CPU time | 1808.36 seconds |
| Started | Sep 09 01:13:18 PM UTC 24 |
| Finished | Sep 09 01:43:46 PM UTC 24 |
| Peak memory | 303344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889014068 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.1889014068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all_with_rand_reset.1410876621 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 11671269775 ps |
| CPU time | 224.39 seconds |
| Started | Sep 09 01:44:47 PM UTC 24 |
| Finished | Sep 09 01:48:35 PM UTC 24 |
| Peak memory | 279476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1410876621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.a lert_handler_stress_all_with_rand_reset.1410876621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all_with_rand_reset.3680454073 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 38140086166 ps |
| CPU time | 704.2 seconds |
| Started | Sep 09 12:50:19 PM UTC 24 |
| Finished | Sep 09 01:02:12 PM UTC 24 |
| Peak memory | 295860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3680454073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.a lert_handler_stress_all_with_rand_reset.3680454073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.4286836679 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7366573507 ps |
| CPU time | 30.84 seconds |
| Started | Sep 09 11:46:12 AM UTC 24 |
| Finished | Sep 09 11:46:45 AM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286836679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.4286836679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.413507942 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 362430973 ps |
| CPU time | 28.79 seconds |
| Started | Sep 09 05:22:10 PM UTC 24 |
| Finished | Sep 09 05:22:40 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413507942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.413507942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2863180077 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 39556785156 ps |
| CPU time | 365.45 seconds |
| Started | Sep 09 05:22:59 PM UTC 24 |
| Finished | Sep 09 05:29:10 PM UTC 24 |
| Peak memory | 285604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863180077 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.2863180077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3449744542 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 6656302726 ps |
| CPU time | 442.97 seconds |
| Started | Sep 09 05:21:07 PM UTC 24 |
| Finished | Sep 09 05:28:36 PM UTC 24 |
| Peak memory | 279116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449744542 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shado w_reg_errors_with_csr_rw.3449744542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.2294001706 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 11252126 ps |
| CPU time | 2.03 seconds |
| Started | Sep 09 05:23:10 PM UTC 24 |
| Finished | Sep 09 05:23:13 PM UTC 24 |
| Peak memory | 250420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294001706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2294001706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.854369851 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 28679026706 ps |
| CPU time | 649.78 seconds |
| Started | Sep 09 05:21:11 PM UTC 24 |
| Finished | Sep 09 05:32:09 PM UTC 24 |
| Peak memory | 279468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854369851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow _reg_errors_with_csr_rw.854369851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.1904210289 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 42653430503 ps |
| CPU time | 2257.07 seconds |
| Started | Sep 09 11:57:18 AM UTC 24 |
| Finished | Sep 09 12:35:19 PM UTC 24 |
| Peak memory | 300588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904210289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1904210289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.1398899307 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 2410055802 ps |
| CPU time | 121.22 seconds |
| Started | Sep 09 11:56:57 AM UTC 24 |
| Finished | Sep 09 11:59:01 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398899307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1398899307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.107343030 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 137637698608 ps |
| CPU time | 846.17 seconds |
| Started | Sep 09 11:59:02 AM UTC 24 |
| Finished | Sep 09 12:13:18 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107343030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.107343030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.1615776769 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1332627355 ps |
| CPU time | 48.66 seconds |
| Started | Sep 09 12:08:26 PM UTC 24 |
| Finished | Sep 09 12:09:16 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615776769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1615776769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.1792913505 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 10320099326 ps |
| CPU time | 355.13 seconds |
| Started | Sep 09 12:20:14 PM UTC 24 |
| Finished | Sep 09 12:26:13 PM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792913505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1792913505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.406503831 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1174206509 ps |
| CPU time | 52.44 seconds |
| Started | Sep 09 12:30:39 PM UTC 24 |
| Finished | Sep 09 12:31:33 PM UTC 24 |
| Peak memory | 269080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406503831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.406503831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.2516355201 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 261690086 ps |
| CPU time | 25.15 seconds |
| Started | Sep 09 12:35:44 PM UTC 24 |
| Finished | Sep 09 12:36:10 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516355201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2516355201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all_with_rand_reset.1143280817 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 8112891192 ps |
| CPU time | 243.04 seconds |
| Started | Sep 09 12:36:43 PM UTC 24 |
| Finished | Sep 09 12:40:50 PM UTC 24 |
| Peak memory | 279804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1143280817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.a lert_handler_stress_all_with_rand_reset.1143280817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.2169936948 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 80481077580 ps |
| CPU time | 1422.83 seconds |
| Started | Sep 09 12:58:56 PM UTC 24 |
| Finished | Sep 09 01:22:58 PM UTC 24 |
| Peak memory | 302204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169936948 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.2169936948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.3395437662 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 889129391 ps |
| CPU time | 22.39 seconds |
| Started | Sep 09 01:00:26 PM UTC 24 |
| Finished | Sep 09 01:00:49 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395437662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3395437662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.811616789 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 39348850755 ps |
| CPU time | 1297.68 seconds |
| Started | Sep 09 01:17:56 PM UTC 24 |
| Finished | Sep 09 01:39:48 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811616789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.811616789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.1833745805 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 77206556442 ps |
| CPU time | 1597.57 seconds |
| Started | Sep 09 01:22:09 PM UTC 24 |
| Finished | Sep 09 01:49:03 PM UTC 24 |
| Peak memory | 318264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833745805 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.1833745805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.434771236 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 98420434 ps |
| CPU time | 8.43 seconds |
| Started | Sep 09 01:30:14 PM UTC 24 |
| Finished | Sep 09 01:30:23 PM UTC 24 |
| Peak memory | 252896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434771236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.434771236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2357639477 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 185248786 ps |
| CPU time | 4.2 seconds |
| Started | Sep 09 05:21:09 PM UTC 24 |
| Finished | Sep 09 05:21:14 PM UTC 24 |
| Peak memory | 250408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357639477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2357639477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1517319378 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2606610373 ps |
| CPU time | 130.15 seconds |
| Started | Sep 09 05:21:58 PM UTC 24 |
| Finished | Sep 09 05:24:10 PM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517319378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1517319378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1830174100 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1237444012 ps |
| CPU time | 87.4 seconds |
| Started | Sep 09 05:22:21 PM UTC 24 |
| Finished | Sep 09 05:23:50 PM UTC 24 |
| Peak memory | 260632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830174100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1830174100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1328327440 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1003693442 ps |
| CPU time | 94.63 seconds |
| Started | Sep 09 05:20:55 PM UTC 24 |
| Finished | Sep 09 05:22:32 PM UTC 24 |
| Peak memory | 279336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328327440 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.1328327440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1647461333 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 60425999 ps |
| CPU time | 4.46 seconds |
| Started | Sep 09 05:22:51 PM UTC 24 |
| Finished | Sep 09 05:22:56 PM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647461333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1647461333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.623386185 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 353897009 ps |
| CPU time | 47.57 seconds |
| Started | Sep 09 05:23:37 PM UTC 24 |
| Finished | Sep 09 05:24:26 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623386185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.623386185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2116381660 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 317425715 ps |
| CPU time | 49.16 seconds |
| Started | Sep 09 05:21:29 PM UTC 24 |
| Finished | Sep 09 05:22:20 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116381660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2116381660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2610863615 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1379219750 ps |
| CPU time | 67.34 seconds |
| Started | Sep 09 05:21:41 PM UTC 24 |
| Finished | Sep 09 05:22:50 PM UTC 24 |
| Peak memory | 250608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610863615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2610863615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3712403152 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 63101311 ps |
| CPU time | 2.02 seconds |
| Started | Sep 09 05:21:06 PM UTC 24 |
| Finished | Sep 09 05:21:09 PM UTC 24 |
| Peak memory | 250480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712403152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3712403152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3903094442 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1208197387 ps |
| CPU time | 51.01 seconds |
| Started | Sep 09 05:23:06 PM UTC 24 |
| Finished | Sep 09 05:23:59 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903094442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3903094442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2888633284 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 76376732 ps |
| CPU time | 5.16 seconds |
| Started | Sep 09 05:21:20 PM UTC 24 |
| Finished | Sep 09 05:21:26 PM UTC 24 |
| Peak memory | 250480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888633284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2888633284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3999358380 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 31691699 ps |
| CPU time | 3.99 seconds |
| Started | Sep 09 05:21:23 PM UTC 24 |
| Finished | Sep 09 05:21:28 PM UTC 24 |
| Peak memory | 250408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999358380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3999358380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1293709132 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 50975974 ps |
| CPU time | 2.83 seconds |
| Started | Sep 09 05:21:36 PM UTC 24 |
| Finished | Sep 09 05:21:40 PM UTC 24 |
| Peak memory | 250596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293709132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1293709132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.1834087688 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 45213401971 ps |
| CPU time | 364.42 seconds |
| Started | Sep 09 11:58:50 AM UTC 24 |
| Finished | Sep 09 12:04:59 PM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834087688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1834087688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.2330903133 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 42127120637 ps |
| CPU time | 2882.62 seconds |
| Started | Sep 09 11:59:21 AM UTC 24 |
| Finished | Sep 09 12:47:56 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330903133 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.2330903133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.4004492948 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11129993312 ps |
| CPU time | 1006.31 seconds |
| Started | Sep 09 12:44:54 PM UTC 24 |
| Finished | Sep 09 01:01:52 PM UTC 24 |
| Peak memory | 285504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004492948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.4004492948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1849271784 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 6754968952 ps |
| CPU time | 225.75 seconds |
| Started | Sep 09 05:21:06 PM UTC 24 |
| Finished | Sep 09 05:24:56 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849271784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1849271784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2357504716 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 855526559 ps |
| CPU time | 139.4 seconds |
| Started | Sep 09 05:21:06 PM UTC 24 |
| Finished | Sep 09 05:23:29 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357504716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2357504716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1423345010 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 236314091 ps |
| CPU time | 5.08 seconds |
| Started | Sep 09 05:21:06 PM UTC 24 |
| Finished | Sep 09 05:21:12 PM UTC 24 |
| Peak memory | 262628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423345010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1423345010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2636206523 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 174990438 ps |
| CPU time | 8.93 seconds |
| Started | Sep 09 05:21:06 PM UTC 24 |
| Finished | Sep 09 05:21:17 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636206523 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_ rw_with_rand_reset.2636206523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.1928600499 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 48999774 ps |
| CPU time | 4.01 seconds |
| Started | Sep 09 05:21:06 PM UTC 24 |
| Finished | Sep 09 05:21:11 PM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928600499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1928600499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.2572144621 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 7791820 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 05:21:06 PM UTC 24 |
| Finished | Sep 09 05:21:09 PM UTC 24 |
| Peak memory | 249680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572144621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2572144621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3617842661 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1038514351 ps |
| CPU time | 49.05 seconds |
| Started | Sep 09 05:21:06 PM UTC 24 |
| Finished | Sep 09 05:21:57 PM UTC 24 |
| Peak memory | 260640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617842661 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.3617842661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.1733588814 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 40205499 ps |
| CPU time | 5.43 seconds |
| Started | Sep 09 05:21:06 PM UTC 24 |
| Finished | Sep 09 05:21:13 PM UTC 24 |
| Peak memory | 266808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733588814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1733588814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4247143657 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 13868398017 ps |
| CPU time | 218.97 seconds |
| Started | Sep 09 05:21:11 PM UTC 24 |
| Finished | Sep 09 05:24:53 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247143657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.4247143657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.463973136 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 8171594998 ps |
| CPU time | 133.23 seconds |
| Started | Sep 09 05:21:10 PM UTC 24 |
| Finished | Sep 09 05:23:26 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463973136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.463973136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3157159565 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 117854516 ps |
| CPU time | 5.24 seconds |
| Started | Sep 09 05:21:10 PM UTC 24 |
| Finished | Sep 09 05:21:16 PM UTC 24 |
| Peak memory | 262624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157159565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3157159565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1805525380 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 374220245 ps |
| CPU time | 7.66 seconds |
| Started | Sep 09 05:21:11 PM UTC 24 |
| Finished | Sep 09 05:21:20 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805525380 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_ rw_with_rand_reset.1805525380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.3857051905 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 6317788 ps |
| CPU time | 1.51 seconds |
| Started | Sep 09 05:21:10 PM UTC 24 |
| Finished | Sep 09 05:21:12 PM UTC 24 |
| Peak memory | 246804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857051905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3857051905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1527471866 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 630897663 ps |
| CPU time | 27.85 seconds |
| Started | Sep 09 05:21:11 PM UTC 24 |
| Finished | Sep 09 05:21:40 PM UTC 24 |
| Peak memory | 262404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527471866 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.1527471866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.3765742201 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1057883324 ps |
| CPU time | 13.43 seconds |
| Started | Sep 09 05:21:09 PM UTC 24 |
| Finished | Sep 09 05:21:23 PM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765742201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3765742201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2966444808 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 67963039 ps |
| CPU time | 8.05 seconds |
| Started | Sep 09 05:21:52 PM UTC 24 |
| Finished | Sep 09 05:22:01 PM UTC 24 |
| Peak memory | 250596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966444808 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem _rw_with_rand_reset.2966444808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.300618152 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 183012798 ps |
| CPU time | 9.9 seconds |
| Started | Sep 09 05:21:51 PM UTC 24 |
| Finished | Sep 09 05:22:02 PM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300618152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.300618152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.350771498 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 9874169 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 05:21:50 PM UTC 24 |
| Finished | Sep 09 05:21:53 PM UTC 24 |
| Peak memory | 250336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350771498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.350771498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2818227828 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 331255310 ps |
| CPU time | 26.63 seconds |
| Started | Sep 09 05:21:51 PM UTC 24 |
| Finished | Sep 09 05:22:19 PM UTC 24 |
| Peak memory | 262688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818227828 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.2818227828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.592365493 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 4458005911 ps |
| CPU time | 279.33 seconds |
| Started | Sep 09 05:21:47 PM UTC 24 |
| Finished | Sep 09 05:26:31 PM UTC 24 |
| Peak memory | 279468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592365493 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.592365493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.3021712991 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 630711625 ps |
| CPU time | 29.53 seconds |
| Started | Sep 09 05:21:49 PM UTC 24 |
| Finished | Sep 09 05:22:20 PM UTC 24 |
| Peak memory | 268904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021712991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3021712991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3621900789 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 2523879613 ps |
| CPU time | 34.66 seconds |
| Started | Sep 09 05:21:49 PM UTC 24 |
| Finished | Sep 09 05:22:25 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621900789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3621900789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.620350751 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 274716712 ps |
| CPU time | 8.6 seconds |
| Started | Sep 09 05:22:03 PM UTC 24 |
| Finished | Sep 09 05:22:13 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620350751 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem_ rw_with_rand_reset.620350751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.2327043567 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 186651846 ps |
| CPU time | 6.11 seconds |
| Started | Sep 09 05:22:02 PM UTC 24 |
| Finished | Sep 09 05:22:09 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327043567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2327043567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.1642947967 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 21716019 ps |
| CPU time | 2.4 seconds |
| Started | Sep 09 05:22:02 PM UTC 24 |
| Finished | Sep 09 05:22:05 PM UTC 24 |
| Peak memory | 250344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642947967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1642947967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1395918778 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 177762301 ps |
| CPU time | 25.59 seconds |
| Started | Sep 09 05:22:02 PM UTC 24 |
| Finished | Sep 09 05:22:29 PM UTC 24 |
| Peak memory | 260640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395918778 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.1395918778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2514811132 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 8057699682 ps |
| CPU time | 175.71 seconds |
| Started | Sep 09 05:21:57 PM UTC 24 |
| Finished | Sep 09 05:24:55 PM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514811132 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.2514811132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.19287302 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 17710398353 ps |
| CPU time | 1012.35 seconds |
| Started | Sep 09 05:21:54 PM UTC 24 |
| Finished | Sep 09 05:38:59 PM UTC 24 |
| Peak memory | 282120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19287302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow _reg_errors_with_csr_rw.19287302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.31080883 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1285623640 ps |
| CPU time | 16.81 seconds |
| Started | Sep 09 05:21:57 PM UTC 24 |
| Finished | Sep 09 05:22:15 PM UTC 24 |
| Peak memory | 262964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31080883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_ SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handle r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.31080883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2408371936 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 152649626 ps |
| CPU time | 16.81 seconds |
| Started | Sep 09 05:22:17 PM UTC 24 |
| Finished | Sep 09 05:22:35 PM UTC 24 |
| Peak memory | 264796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408371936 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem _rw_with_rand_reset.2408371936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.2858041713 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 501484852 ps |
| CPU time | 7 seconds |
| Started | Sep 09 05:22:16 PM UTC 24 |
| Finished | Sep 09 05:22:24 PM UTC 24 |
| Peak memory | 250336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858041713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2858041713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.204773478 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 16446913 ps |
| CPU time | 2.07 seconds |
| Started | Sep 09 05:22:14 PM UTC 24 |
| Finished | Sep 09 05:22:17 PM UTC 24 |
| Peak memory | 250480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204773478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.204773478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1096923563 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 172233957 ps |
| CPU time | 22.42 seconds |
| Started | Sep 09 05:22:16 PM UTC 24 |
| Finished | Sep 09 05:22:40 PM UTC 24 |
| Peak memory | 260640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096923563 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.1096923563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3061022637 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 9177133287 ps |
| CPU time | 348.47 seconds |
| Started | Sep 09 05:22:03 PM UTC 24 |
| Finished | Sep 09 05:27:57 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061022637 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad ow_reg_errors_with_csr_rw.3061022637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.992286 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 973350182 ps |
| CPU time | 7.18 seconds |
| Started | Sep 09 05:22:07 PM UTC 24 |
| Finished | Sep 09 05:22:15 PM UTC 24 |
| Peak memory | 262824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SE Q=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.992286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3214256199 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 128995747 ps |
| CPU time | 7.45 seconds |
| Started | Sep 09 05:22:29 PM UTC 24 |
| Finished | Sep 09 05:22:38 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214256199 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem _rw_with_rand_reset.3214256199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.2454735305 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 50385255 ps |
| CPU time | 6.99 seconds |
| Started | Sep 09 05:22:26 PM UTC 24 |
| Finished | Sep 09 05:22:34 PM UTC 24 |
| Peak memory | 250536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454735305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2454735305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.3594681120 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 8515042 ps |
| CPU time | 2.1 seconds |
| Started | Sep 09 05:22:25 PM UTC 24 |
| Finished | Sep 09 05:22:28 PM UTC 24 |
| Peak memory | 250416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594681120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3594681120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2219626535 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 170433596 ps |
| CPU time | 36.03 seconds |
| Started | Sep 09 05:22:28 PM UTC 24 |
| Finished | Sep 09 05:23:06 PM UTC 24 |
| Peak memory | 262688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219626535 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.2219626535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2868875695 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 7692116291 ps |
| CPU time | 126.47 seconds |
| Started | Sep 09 05:22:20 PM UTC 24 |
| Finished | Sep 09 05:24:29 PM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868875695 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.2868875695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1892587442 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 8367149588 ps |
| CPU time | 312.95 seconds |
| Started | Sep 09 05:22:18 PM UTC 24 |
| Finished | Sep 09 05:27:36 PM UTC 24 |
| Peak memory | 279536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892587442 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shad ow_reg_errors_with_csr_rw.1892587442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.3378489628 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 262825665 ps |
| CPU time | 5.75 seconds |
| Started | Sep 09 05:22:21 PM UTC 24 |
| Finished | Sep 09 05:22:28 PM UTC 24 |
| Peak memory | 265012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378489628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3378489628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3231330189 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 142423501 ps |
| CPU time | 12.63 seconds |
| Started | Sep 09 05:22:41 PM UTC 24 |
| Finished | Sep 09 05:22:55 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231330189 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem _rw_with_rand_reset.3231330189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.1996354359 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 180790049 ps |
| CPU time | 7.32 seconds |
| Started | Sep 09 05:22:39 PM UTC 24 |
| Finished | Sep 09 05:22:48 PM UTC 24 |
| Peak memory | 250472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996354359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1996354359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.93793233 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 16586687 ps |
| CPU time | 2.07 seconds |
| Started | Sep 09 05:22:37 PM UTC 24 |
| Finished | Sep 09 05:22:40 PM UTC 24 |
| Peak memory | 250420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93793233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_ SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handle r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.93793233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4230664404 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 177324298 ps |
| CPU time | 31.74 seconds |
| Started | Sep 09 05:22:41 PM UTC 24 |
| Finished | Sep 09 05:23:14 PM UTC 24 |
| Peak memory | 262760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230664404 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.4230664404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.860448203 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 9044409230 ps |
| CPU time | 284.6 seconds |
| Started | Sep 09 05:22:33 PM UTC 24 |
| Finished | Sep 09 05:27:22 PM UTC 24 |
| Peak memory | 279468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860448203 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.860448203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.266844421 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2184276272 ps |
| CPU time | 293.05 seconds |
| Started | Sep 09 05:22:30 PM UTC 24 |
| Finished | Sep 09 05:27:28 PM UTC 24 |
| Peak memory | 279400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266844421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shado w_reg_errors_with_csr_rw.266844421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.3140752876 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 108193489 ps |
| CPU time | 14.43 seconds |
| Started | Sep 09 05:22:35 PM UTC 24 |
| Finished | Sep 09 05:22:51 PM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140752876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3140752876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2042359128 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4060318037 ps |
| CPU time | 94.79 seconds |
| Started | Sep 09 05:22:37 PM UTC 24 |
| Finished | Sep 09 05:24:14 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042359128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2042359128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.914343267 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 65212784 ps |
| CPU time | 15.43 seconds |
| Started | Sep 09 05:22:57 PM UTC 24 |
| Finished | Sep 09 05:23:14 PM UTC 24 |
| Peak memory | 268892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914343267 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem_ rw_with_rand_reset.914343267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.995374767 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 36366373 ps |
| CPU time | 4.37 seconds |
| Started | Sep 09 05:22:56 PM UTC 24 |
| Finished | Sep 09 05:23:02 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995374767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.995374767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.1734808799 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 7206820 ps |
| CPU time | 2.37 seconds |
| Started | Sep 09 05:22:52 PM UTC 24 |
| Finished | Sep 09 05:22:55 PM UTC 24 |
| Peak memory | 248296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734808799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1734808799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3497948674 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1723401406 ps |
| CPU time | 24.26 seconds |
| Started | Sep 09 05:22:56 PM UTC 24 |
| Finished | Sep 09 05:23:22 PM UTC 24 |
| Peak memory | 260636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497948674 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.3497948674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2762991520 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 19912547398 ps |
| CPU time | 366.04 seconds |
| Started | Sep 09 05:22:48 PM UTC 24 |
| Finished | Sep 09 05:29:00 PM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762991520 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.2762991520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.1985511113 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3819330488 ps |
| CPU time | 17.67 seconds |
| Started | Sep 09 05:22:51 PM UTC 24 |
| Finished | Sep 09 05:23:10 PM UTC 24 |
| Peak memory | 263088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985511113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1985511113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.246891323 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 614112228 ps |
| CPU time | 19.85 seconds |
| Started | Sep 09 05:23:14 PM UTC 24 |
| Finished | Sep 09 05:23:35 PM UTC 24 |
| Peak memory | 264796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246891323 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem_ rw_with_rand_reset.246891323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.1410718577 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 36432706 ps |
| CPU time | 8.65 seconds |
| Started | Sep 09 05:23:13 PM UTC 24 |
| Finished | Sep 09 05:23:23 PM UTC 24 |
| Peak memory | 250408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410718577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1410718577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.301081841 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3096712396 ps |
| CPU time | 28.53 seconds |
| Started | Sep 09 05:23:13 PM UTC 24 |
| Finished | Sep 09 05:23:43 PM UTC 24 |
| Peak memory | 262824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301081841 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.301081841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2515043510 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 17280346559 ps |
| CPU time | 329.51 seconds |
| Started | Sep 09 05:22:59 PM UTC 24 |
| Finished | Sep 09 05:28:33 PM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515043510 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad ow_reg_errors_with_csr_rw.2515043510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.1238431516 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 129842531 ps |
| CPU time | 8.24 seconds |
| Started | Sep 09 05:23:02 PM UTC 24 |
| Finished | Sep 09 05:23:12 PM UTC 24 |
| Peak memory | 266856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238431516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1238431516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4188786756 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 78286307 ps |
| CPU time | 11.33 seconds |
| Started | Sep 09 05:23:28 PM UTC 24 |
| Finished | Sep 09 05:23:41 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188786756 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem _rw_with_rand_reset.4188786756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.3090527065 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 472434208 ps |
| CPU time | 14.71 seconds |
| Started | Sep 09 05:23:26 PM UTC 24 |
| Finished | Sep 09 05:23:42 PM UTC 24 |
| Peak memory | 250536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090527065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3090527065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.2027941212 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 11646535 ps |
| CPU time | 2.17 seconds |
| Started | Sep 09 05:23:24 PM UTC 24 |
| Finished | Sep 09 05:23:27 PM UTC 24 |
| Peak memory | 250484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027941212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2027941212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2080940457 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 262986529 ps |
| CPU time | 31.86 seconds |
| Started | Sep 09 05:23:27 PM UTC 24 |
| Finished | Sep 09 05:24:00 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080940457 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.2080940457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2975453490 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 37333420111 ps |
| CPU time | 358.65 seconds |
| Started | Sep 09 05:23:15 PM UTC 24 |
| Finished | Sep 09 05:29:19 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975453490 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.2975453490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2101170408 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 7848233409 ps |
| CPU time | 316.26 seconds |
| Started | Sep 09 05:23:15 PM UTC 24 |
| Finished | Sep 09 05:28:36 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101170408 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad ow_reg_errors_with_csr_rw.2101170408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.1368881426 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 29324889 ps |
| CPU time | 7.33 seconds |
| Started | Sep 09 05:23:16 PM UTC 24 |
| Finished | Sep 09 05:23:25 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368881426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1368881426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4264267151 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 297517086 ps |
| CPU time | 16.71 seconds |
| Started | Sep 09 05:23:46 PM UTC 24 |
| Finished | Sep 09 05:24:04 PM UTC 24 |
| Peak memory | 254556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264267151 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem _rw_with_rand_reset.4264267151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.2854901591 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 133446117 ps |
| CPU time | 8.12 seconds |
| Started | Sep 09 05:23:43 PM UTC 24 |
| Finished | Sep 09 05:23:52 PM UTC 24 |
| Peak memory | 250472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854901591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2854901591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.1067368454 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 7392588 ps |
| CPU time | 2.23 seconds |
| Started | Sep 09 05:23:42 PM UTC 24 |
| Finished | Sep 09 05:23:45 PM UTC 24 |
| Peak memory | 248432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067368454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1067368454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1915446957 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 538691101 ps |
| CPU time | 52.98 seconds |
| Started | Sep 09 05:23:44 PM UTC 24 |
| Finished | Sep 09 05:24:39 PM UTC 24 |
| Peak memory | 260640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915446957 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.1915446957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3078212007 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 42224843967 ps |
| CPU time | 424.84 seconds |
| Started | Sep 09 05:23:30 PM UTC 24 |
| Finished | Sep 09 05:30:41 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078212007 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.3078212007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.674615306 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 163942028 ps |
| CPU time | 13.85 seconds |
| Started | Sep 09 05:23:36 PM UTC 24 |
| Finished | Sep 09 05:23:51 PM UTC 24 |
| Peak memory | 266992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674615306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.674615306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3626788816 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 290290830 ps |
| CPU time | 8.01 seconds |
| Started | Sep 09 05:24:06 PM UTC 24 |
| Finished | Sep 09 05:24:15 PM UTC 24 |
| Peak memory | 268896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626788816 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem _rw_with_rand_reset.3626788816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.1240038303 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 137244101 ps |
| CPU time | 13.48 seconds |
| Started | Sep 09 05:24:01 PM UTC 24 |
| Finished | Sep 09 05:24:16 PM UTC 24 |
| Peak memory | 250336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240038303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1240038303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.2398887559 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 8133409 ps |
| CPU time | 2.17 seconds |
| Started | Sep 09 05:24:00 PM UTC 24 |
| Finished | Sep 09 05:24:03 PM UTC 24 |
| Peak memory | 250344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398887559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2398887559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.65363989 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 203735838 ps |
| CPU time | 31.37 seconds |
| Started | Sep 09 05:24:04 PM UTC 24 |
| Finished | Sep 09 05:24:37 PM UTC 24 |
| Peak memory | 262684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65363989 -assert nopostproc +UVM_TESTNAME=alert_handler _base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.65363989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.359287116 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 16826634219 ps |
| CPU time | 313.29 seconds |
| Started | Sep 09 05:23:53 PM UTC 24 |
| Finished | Sep 09 05:29:11 PM UTC 24 |
| Peak memory | 285612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359287116 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.359287116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2417218164 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 18068694844 ps |
| CPU time | 1095.63 seconds |
| Started | Sep 09 05:23:51 PM UTC 24 |
| Finished | Sep 09 05:42:20 PM UTC 24 |
| Peak memory | 288252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417218164 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad ow_reg_errors_with_csr_rw.2417218164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.3287467257 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 242501347 ps |
| CPU time | 11.54 seconds |
| Started | Sep 09 05:23:54 PM UTC 24 |
| Finished | Sep 09 05:24:07 PM UTC 24 |
| Peak memory | 262760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287467257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3287467257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4125005529 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 68218864 ps |
| CPU time | 6.94 seconds |
| Started | Sep 09 05:23:58 PM UTC 24 |
| Finished | Sep 09 05:24:06 PM UTC 24 |
| Peak memory | 250396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125005529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.4125005529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2049980373 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 9413722748 ps |
| CPU time | 212.45 seconds |
| Started | Sep 09 05:21:13 PM UTC 24 |
| Finished | Sep 09 05:24:49 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049980373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2049980373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1748330080 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 3720711153 ps |
| CPU time | 203.1 seconds |
| Started | Sep 09 05:21:12 PM UTC 24 |
| Finished | Sep 09 05:24:39 PM UTC 24 |
| Peak memory | 250604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748330080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1748330080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1733720515 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 164934065 ps |
| CPU time | 4.77 seconds |
| Started | Sep 09 05:21:12 PM UTC 24 |
| Finished | Sep 09 05:21:18 PM UTC 24 |
| Peak memory | 262628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733720515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1733720515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1174631773 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 332478204 ps |
| CPU time | 13.93 seconds |
| Started | Sep 09 05:21:13 PM UTC 24 |
| Finished | Sep 09 05:21:28 PM UTC 24 |
| Peak memory | 264800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174631773 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_ rw_with_rand_reset.1174631773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.3861638300 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 7350252 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 05:21:11 PM UTC 24 |
| Finished | Sep 09 05:21:14 PM UTC 24 |
| Peak memory | 246804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861638300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3861638300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1593178778 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1002175410 ps |
| CPU time | 35.23 seconds |
| Started | Sep 09 05:21:13 PM UTC 24 |
| Finished | Sep 09 05:21:49 PM UTC 24 |
| Peak memory | 262688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593178778 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.1593178778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.2432248664 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 689665464 ps |
| CPU time | 25.97 seconds |
| Started | Sep 09 05:21:11 PM UTC 24 |
| Finished | Sep 09 05:21:38 PM UTC 24 |
| Peak memory | 268904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432248664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2432248664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1336999678 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1954222658 ps |
| CPU time | 35.07 seconds |
| Started | Sep 09 05:21:11 PM UTC 24 |
| Finished | Sep 09 05:21:48 PM UTC 24 |
| Peak memory | 252332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336999678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1336999678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.3899422030 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 12985355 ps |
| CPU time | 2.06 seconds |
| Started | Sep 09 05:24:07 PM UTC 24 |
| Finished | Sep 09 05:24:10 PM UTC 24 |
| Peak memory | 250420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899422030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3899422030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2767023883 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 10834095 ps |
| CPU time | 2.35 seconds |
| Started | Sep 09 05:24:08 PM UTC 24 |
| Finished | Sep 09 05:24:11 PM UTC 24 |
| Peak memory | 250348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767023883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2767023883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.4258748621 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 12482875 ps |
| CPU time | 2.04 seconds |
| Started | Sep 09 05:24:11 PM UTC 24 |
| Finished | Sep 09 05:24:14 PM UTC 24 |
| Peak memory | 250416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258748621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4258748621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.468002777 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 8136363 ps |
| CPU time | 2.27 seconds |
| Started | Sep 09 05:24:11 PM UTC 24 |
| Finished | Sep 09 05:24:14 PM UTC 24 |
| Peak memory | 250340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468002777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.468002777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2635902652 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 20052109 ps |
| CPU time | 2.3 seconds |
| Started | Sep 09 05:24:12 PM UTC 24 |
| Finished | Sep 09 05:24:16 PM UTC 24 |
| Peak memory | 250484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635902652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2635902652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.2676328895 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 10702366 ps |
| CPU time | 2.23 seconds |
| Started | Sep 09 05:24:14 PM UTC 24 |
| Finished | Sep 09 05:24:18 PM UTC 24 |
| Peak memory | 250344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676328895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2676328895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.3655514518 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 8909390 ps |
| CPU time | 2.39 seconds |
| Started | Sep 09 05:24:15 PM UTC 24 |
| Finished | Sep 09 05:24:19 PM UTC 24 |
| Peak memory | 250344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655514518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3655514518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.2927604314 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 11728583 ps |
| CPU time | 2.08 seconds |
| Started | Sep 09 05:24:16 PM UTC 24 |
| Finished | Sep 09 05:24:19 PM UTC 24 |
| Peak memory | 250484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927604314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2927604314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.3332173249 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 11075011 ps |
| CPU time | 2.58 seconds |
| Started | Sep 09 05:24:16 PM UTC 24 |
| Finished | Sep 09 05:24:19 PM UTC 24 |
| Peak memory | 250344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332173249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3332173249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2076023704 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 11382151 ps |
| CPU time | 2.68 seconds |
| Started | Sep 09 05:24:17 PM UTC 24 |
| Finished | Sep 09 05:24:20 PM UTC 24 |
| Peak memory | 250420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076023704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2076023704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1457990127 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2259576613 ps |
| CPU time | 139.65 seconds |
| Started | Sep 09 05:21:14 PM UTC 24 |
| Finished | Sep 09 05:23:36 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457990127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1457990127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.724670379 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 11879767799 ps |
| CPU time | 227.34 seconds |
| Started | Sep 09 05:21:14 PM UTC 24 |
| Finished | Sep 09 05:25:05 PM UTC 24 |
| Peak memory | 250464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724670379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.724670379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1718531496 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 40326169 ps |
| CPU time | 4.53 seconds |
| Started | Sep 09 05:21:13 PM UTC 24 |
| Finished | Sep 09 05:21:19 PM UTC 24 |
| Peak memory | 262628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718531496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1718531496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.932423728 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 23020425 ps |
| CPU time | 5.61 seconds |
| Started | Sep 09 05:21:14 PM UTC 24 |
| Finished | Sep 09 05:21:21 PM UTC 24 |
| Peak memory | 264804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932423728 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_r w_with_rand_reset.932423728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.2289533755 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 458199208 ps |
| CPU time | 12.21 seconds |
| Started | Sep 09 05:21:14 PM UTC 24 |
| Finished | Sep 09 05:21:27 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289533755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2289533755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.1985623982 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 7277256 ps |
| CPU time | 2.07 seconds |
| Started | Sep 09 05:21:13 PM UTC 24 |
| Finished | Sep 09 05:21:16 PM UTC 24 |
| Peak memory | 248432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985623982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1985623982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3286663355 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1473629130 ps |
| CPU time | 35.32 seconds |
| Started | Sep 09 05:21:14 PM UTC 24 |
| Finished | Sep 09 05:21:51 PM UTC 24 |
| Peak memory | 260648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286663355 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.3286663355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.940423373 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 18982437188 ps |
| CPU time | 333.15 seconds |
| Started | Sep 09 05:21:13 PM UTC 24 |
| Finished | Sep 09 05:26:51 PM UTC 24 |
| Peak memory | 285612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940423373 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.940423373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1433237423 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 13765336378 ps |
| CPU time | 682.01 seconds |
| Started | Sep 09 05:21:13 PM UTC 24 |
| Finished | Sep 09 05:32:44 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433237423 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado w_reg_errors_with_csr_rw.1433237423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.2569643310 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 96348890 ps |
| CPU time | 19.53 seconds |
| Started | Sep 09 05:21:13 PM UTC 24 |
| Finished | Sep 09 05:21:34 PM UTC 24 |
| Peak memory | 262836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569643310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2569643310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.1266775333 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 6688511 ps |
| CPU time | 2.29 seconds |
| Started | Sep 09 05:24:17 PM UTC 24 |
| Finished | Sep 09 05:24:20 PM UTC 24 |
| Peak memory | 250484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266775333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1266775333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.487323021 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 9841818 ps |
| CPU time | 2.32 seconds |
| Started | Sep 09 05:24:19 PM UTC 24 |
| Finished | Sep 09 05:24:22 PM UTC 24 |
| Peak memory | 250480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487323021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.487323021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1601763552 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 8568290 ps |
| CPU time | 2.21 seconds |
| Started | Sep 09 05:24:19 PM UTC 24 |
| Finished | Sep 09 05:24:22 PM UTC 24 |
| Peak memory | 250344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601763552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1601763552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.848451204 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 10990152 ps |
| CPU time | 2.06 seconds |
| Started | Sep 09 05:24:20 PM UTC 24 |
| Finished | Sep 09 05:24:23 PM UTC 24 |
| Peak memory | 250480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848451204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.848451204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3690558551 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 14210666 ps |
| CPU time | 1.92 seconds |
| Started | Sep 09 05:24:20 PM UTC 24 |
| Finished | Sep 09 05:24:23 PM UTC 24 |
| Peak memory | 248916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690558551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3690558551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.2026878776 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 9274050 ps |
| CPU time | 2.33 seconds |
| Started | Sep 09 05:24:21 PM UTC 24 |
| Finished | Sep 09 05:24:25 PM UTC 24 |
| Peak memory | 248296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026878776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2026878776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.642931416 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 7612818 ps |
| CPU time | 2.03 seconds |
| Started | Sep 09 05:24:21 PM UTC 24 |
| Finished | Sep 09 05:24:24 PM UTC 24 |
| Peak memory | 250480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642931416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.642931416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.907925646 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 17826894 ps |
| CPU time | 2.18 seconds |
| Started | Sep 09 05:24:24 PM UTC 24 |
| Finished | Sep 09 05:24:27 PM UTC 24 |
| Peak memory | 250416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907925646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.907925646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.2160606181 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 10716062 ps |
| CPU time | 1.97 seconds |
| Started | Sep 09 05:24:24 PM UTC 24 |
| Finished | Sep 09 05:24:27 PM UTC 24 |
| Peak memory | 248916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160606181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2160606181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.3296677445 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 11303783 ps |
| CPU time | 2.06 seconds |
| Started | Sep 09 05:24:24 PM UTC 24 |
| Finished | Sep 09 05:24:27 PM UTC 24 |
| Peak memory | 250484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296677445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3296677445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2538740768 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 13729411065 ps |
| CPU time | 266.46 seconds |
| Started | Sep 09 05:21:17 PM UTC 24 |
| Finished | Sep 09 05:25:47 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538740768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2538740768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2987095924 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 823563125 ps |
| CPU time | 116.09 seconds |
| Started | Sep 09 05:21:17 PM UTC 24 |
| Finished | Sep 09 05:23:15 PM UTC 24 |
| Peak memory | 252460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987095924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2987095924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.4143873161 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 128149233 ps |
| CPU time | 13.73 seconds |
| Started | Sep 09 05:21:15 PM UTC 24 |
| Finished | Sep 09 05:21:30 PM UTC 24 |
| Peak memory | 262624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143873161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.4143873161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.214551810 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 146494642 ps |
| CPU time | 6.99 seconds |
| Started | Sep 09 05:21:17 PM UTC 24 |
| Finished | Sep 09 05:21:25 PM UTC 24 |
| Peak memory | 250464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214551810 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_r w_with_rand_reset.214551810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.3540233857 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 52772256 ps |
| CPU time | 6.36 seconds |
| Started | Sep 09 05:21:17 PM UTC 24 |
| Finished | Sep 09 05:21:24 PM UTC 24 |
| Peak memory | 250472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540233857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3540233857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3181079428 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 498303274 ps |
| CPU time | 18.58 seconds |
| Started | Sep 09 05:21:17 PM UTC 24 |
| Finished | Sep 09 05:21:37 PM UTC 24 |
| Peak memory | 260640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181079428 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.3181079428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.138433425 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 18405175059 ps |
| CPU time | 281.65 seconds |
| Started | Sep 09 05:21:14 PM UTC 24 |
| Finished | Sep 09 05:26:00 PM UTC 24 |
| Peak memory | 279600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138433425 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.138433425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.626703420 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4657982679 ps |
| CPU time | 586.3 seconds |
| Started | Sep 09 05:21:14 PM UTC 24 |
| Finished | Sep 09 05:31:08 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626703420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow _reg_errors_with_csr_rw.626703420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.701697368 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 119889158 ps |
| CPU time | 15.26 seconds |
| Started | Sep 09 05:21:15 PM UTC 24 |
| Finished | Sep 09 05:21:32 PM UTC 24 |
| Peak memory | 264884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701697368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.701697368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.4279095078 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 24873361 ps |
| CPU time | 1.56 seconds |
| Started | Sep 09 05:24:24 PM UTC 24 |
| Finished | Sep 09 05:24:26 PM UTC 24 |
| Peak memory | 248788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279095078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.4279095078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.3135759741 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 7162420 ps |
| CPU time | 1.96 seconds |
| Started | Sep 09 05:24:25 PM UTC 24 |
| Finished | Sep 09 05:24:28 PM UTC 24 |
| Peak memory | 248916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135759741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3135759741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.293239176 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 8835779 ps |
| CPU time | 2.41 seconds |
| Started | Sep 09 05:24:26 PM UTC 24 |
| Finished | Sep 09 05:24:29 PM UTC 24 |
| Peak memory | 250480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293239176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.293239176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.2834510238 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 13291750 ps |
| CPU time | 1.67 seconds |
| Started | Sep 09 05:24:27 PM UTC 24 |
| Finished | Sep 09 05:24:30 PM UTC 24 |
| Peak memory | 248788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834510238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2834510238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.2702577845 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 11328103 ps |
| CPU time | 2.53 seconds |
| Started | Sep 09 05:24:27 PM UTC 24 |
| Finished | Sep 09 05:24:31 PM UTC 24 |
| Peak memory | 250416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702577845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2702577845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2268204747 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 8903303 ps |
| CPU time | 2.13 seconds |
| Started | Sep 09 05:24:27 PM UTC 24 |
| Finished | Sep 09 05:24:30 PM UTC 24 |
| Peak memory | 250344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268204747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2268204747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.576965765 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 20552296 ps |
| CPU time | 2.14 seconds |
| Started | Sep 09 05:24:27 PM UTC 24 |
| Finished | Sep 09 05:24:31 PM UTC 24 |
| Peak memory | 250344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576965765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.576965765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.2966981760 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 14749994 ps |
| CPU time | 1.99 seconds |
| Started | Sep 09 05:24:29 PM UTC 24 |
| Finished | Sep 09 05:24:32 PM UTC 24 |
| Peak memory | 248788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966981760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2966981760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.789692974 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 20210144 ps |
| CPU time | 1.75 seconds |
| Started | Sep 09 05:24:29 PM UTC 24 |
| Finished | Sep 09 05:24:32 PM UTC 24 |
| Peak memory | 248848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789692974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.789692974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.3906576536 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 8582015 ps |
| CPU time | 2.26 seconds |
| Started | Sep 09 05:24:30 PM UTC 24 |
| Finished | Sep 09 05:24:33 PM UTC 24 |
| Peak memory | 250548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906576536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3906576536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.624519359 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 581387319 ps |
| CPU time | 17.79 seconds |
| Started | Sep 09 05:21:20 PM UTC 24 |
| Finished | Sep 09 05:21:39 PM UTC 24 |
| Peak memory | 264804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624519359 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_r w_with_rand_reset.624519359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.12748357 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 26368433 ps |
| CPU time | 3.72 seconds |
| Started | Sep 09 05:21:20 PM UTC 24 |
| Finished | Sep 09 05:21:24 PM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12748357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_han dler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.12748357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.423998016 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 11160326 ps |
| CPU time | 2.15 seconds |
| Started | Sep 09 05:21:20 PM UTC 24 |
| Finished | Sep 09 05:21:23 PM UTC 24 |
| Peak memory | 250344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423998016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.423998016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2756841744 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 113280319 ps |
| CPU time | 15.82 seconds |
| Started | Sep 09 05:21:20 PM UTC 24 |
| Finished | Sep 09 05:21:37 PM UTC 24 |
| Peak memory | 262688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756841744 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.2756841744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3734781324 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 20245201217 ps |
| CPU time | 448.89 seconds |
| Started | Sep 09 05:21:18 PM UTC 24 |
| Finished | Sep 09 05:28:53 PM UTC 24 |
| Peak memory | 279596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734781324 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.3734781324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.220589781 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 124810550 ps |
| CPU time | 14.18 seconds |
| Started | Sep 09 05:21:18 PM UTC 24 |
| Finished | Sep 09 05:21:34 PM UTC 24 |
| Peak memory | 268980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220589781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.220589781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4061427809 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 230182859 ps |
| CPU time | 8.47 seconds |
| Started | Sep 09 05:21:26 PM UTC 24 |
| Finished | Sep 09 05:21:35 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061427809 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_ rw_with_rand_reset.4061427809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.2529695842 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 68464182 ps |
| CPU time | 4.98 seconds |
| Started | Sep 09 05:21:26 PM UTC 24 |
| Finished | Sep 09 05:21:32 PM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529695842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2529695842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4182112763 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 874700285 ps |
| CPU time | 16 seconds |
| Started | Sep 09 05:21:26 PM UTC 24 |
| Finished | Sep 09 05:21:43 PM UTC 24 |
| Peak memory | 260712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182112763 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.4182112763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3557531735 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2311804803 ps |
| CPU time | 297.97 seconds |
| Started | Sep 09 05:21:21 PM UTC 24 |
| Finished | Sep 09 05:26:23 PM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557531735 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shado w_reg_errors_with_csr_rw.3557531735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.2376017149 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 145350820 ps |
| CPU time | 18.75 seconds |
| Started | Sep 09 05:21:22 PM UTC 24 |
| Finished | Sep 09 05:21:42 PM UTC 24 |
| Peak memory | 262760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376017149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2376017149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.586035668 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 1970076510 ps |
| CPU time | 16 seconds |
| Started | Sep 09 05:21:32 PM UTC 24 |
| Finished | Sep 09 05:21:50 PM UTC 24 |
| Peak memory | 268676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586035668 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_r w_with_rand_reset.586035668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.2947321777 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 20477307 ps |
| CPU time | 4.57 seconds |
| Started | Sep 09 05:21:31 PM UTC 24 |
| Finished | Sep 09 05:21:37 PM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947321777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2947321777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.3897553522 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 8331727 ps |
| CPU time | 1.73 seconds |
| Started | Sep 09 05:21:29 PM UTC 24 |
| Finished | Sep 09 05:21:32 PM UTC 24 |
| Peak memory | 248916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897553522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3897553522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2682613806 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 273697440 ps |
| CPU time | 26.5 seconds |
| Started | Sep 09 05:21:32 PM UTC 24 |
| Finished | Sep 09 05:22:00 PM UTC 24 |
| Peak memory | 260380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682613806 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.2682613806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.21779187 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 3015997982 ps |
| CPU time | 193.79 seconds |
| Started | Sep 09 05:21:28 PM UTC 24 |
| Finished | Sep 09 05:24:45 PM UTC 24 |
| Peak memory | 279664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21779187 -assert nopostproc +UVM_TESTNAME=alert_handler_ba se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.21779187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3560572111 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 18154932158 ps |
| CPU time | 600.96 seconds |
| Started | Sep 09 05:21:27 PM UTC 24 |
| Finished | Sep 09 05:31:35 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560572111 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado w_reg_errors_with_csr_rw.3560572111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.912448583 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 378689517 ps |
| CPU time | 7.45 seconds |
| Started | Sep 09 05:21:29 PM UTC 24 |
| Finished | Sep 09 05:21:38 PM UTC 24 |
| Peak memory | 262964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912448583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.912448583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2857396029 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 128274483 ps |
| CPU time | 10.25 seconds |
| Started | Sep 09 05:21:38 PM UTC 24 |
| Finished | Sep 09 05:21:50 PM UTC 24 |
| Peak memory | 268896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857396029 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_ rw_with_rand_reset.2857396029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.3478898655 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 64546436 ps |
| CPU time | 8.56 seconds |
| Started | Sep 09 05:21:37 PM UTC 24 |
| Finished | Sep 09 05:21:47 PM UTC 24 |
| Peak memory | 250336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478898655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3478898655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.1718729625 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 7624982 ps |
| CPU time | 2.36 seconds |
| Started | Sep 09 05:21:37 PM UTC 24 |
| Finished | Sep 09 05:21:41 PM UTC 24 |
| Peak memory | 248300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718729625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1718729625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4128417433 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 433288320 ps |
| CPU time | 20.99 seconds |
| Started | Sep 09 05:21:38 PM UTC 24 |
| Finished | Sep 09 05:22:01 PM UTC 24 |
| Peak memory | 262756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128417433 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.4128417433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.4157935051 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1491641608 ps |
| CPU time | 39.9 seconds |
| Started | Sep 09 05:21:35 PM UTC 24 |
| Finished | Sep 09 05:22:16 PM UTC 24 |
| Peak memory | 268904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157935051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.4157935051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.9547421 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 320839481 ps |
| CPU time | 10.35 seconds |
| Started | Sep 09 05:21:44 PM UTC 24 |
| Finished | Sep 09 05:21:56 PM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9547421 -assert nopo stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_rw_ with_rand_reset.9547421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.3133945477 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 19938496 ps |
| CPU time | 5.05 seconds |
| Started | Sep 09 05:21:42 PM UTC 24 |
| Finished | Sep 09 05:21:48 PM UTC 24 |
| Peak memory | 250336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133945477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3133945477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.1423132661 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 8835951 ps |
| CPU time | 2.54 seconds |
| Started | Sep 09 05:21:41 PM UTC 24 |
| Finished | Sep 09 05:21:45 PM UTC 24 |
| Peak memory | 250484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423132661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1423132661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1350058567 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 157265666 ps |
| CPU time | 18.33 seconds |
| Started | Sep 09 05:21:43 PM UTC 24 |
| Finished | Sep 09 05:22:03 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350058567 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.1350058567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.87173507 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 4175928805 ps |
| CPU time | 194.04 seconds |
| Started | Sep 09 05:21:40 PM UTC 24 |
| Finished | Sep 09 05:24:57 PM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87173507 -assert nopostproc +UVM_TESTNAME=alert_handler_ba se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.87173507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3396732697 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 7552881196 ps |
| CPU time | 503.04 seconds |
| Started | Sep 09 05:21:40 PM UTC 24 |
| Finished | Sep 09 05:30:10 PM UTC 24 |
| Peak memory | 279468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396732697 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shado w_reg_errors_with_csr_rw.3396732697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.894836902 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 1492304344 ps |
| CPU time | 15.16 seconds |
| Started | Sep 09 05:21:40 PM UTC 24 |
| Finished | Sep 09 05:21:56 PM UTC 24 |
| Peak memory | 262760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894836902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.894836902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.3321911126 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 892746080 ps |
| CPU time | 7.01 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:46:23 AM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321911126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3321911126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.3692542053 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 26812616 ps |
| CPU time | 2.8 seconds |
| Started | Sep 09 11:46:12 AM UTC 24 |
| Finished | Sep 09 11:46:16 AM UTC 24 |
| Peak memory | 252728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692542053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3692542053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.3908098644 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 16010322737 ps |
| CPU time | 726.54 seconds |
| Started | Sep 09 11:46:14 AM UTC 24 |
| Finished | Sep 09 11:58:29 AM UTC 24 |
| Peak memory | 279684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908098644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3908098644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.3488046211 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 992583248 ps |
| CPU time | 78.99 seconds |
| Started | Sep 09 11:46:12 AM UTC 24 |
| Finished | Sep 09 11:47:33 AM UTC 24 |
| Peak memory | 269476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488046211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3488046211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.986158590 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1469957390 ps |
| CPU time | 35.03 seconds |
| Started | Sep 09 11:46:12 AM UTC 24 |
| Finished | Sep 09 11:46:49 AM UTC 24 |
| Peak memory | 262796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986158590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.986158590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.1566543421 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 353984837 ps |
| CPU time | 31.55 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:46:48 AM UTC 24 |
| Peak memory | 295404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566543421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1566543421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.1866071181 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 247032650 ps |
| CPU time | 12.22 seconds |
| Started | Sep 09 11:46:12 AM UTC 24 |
| Finished | Sep 09 11:46:26 AM UTC 24 |
| Peak memory | 263136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866071181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1866071181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.3230573216 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10581745143 ps |
| CPU time | 39.99 seconds |
| Started | Sep 09 11:46:12 AM UTC 24 |
| Finished | Sep 09 11:46:54 AM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230573216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3230573216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/0.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.284285114 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2592162916 ps |
| CPU time | 138.86 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:48:36 AM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284285114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.284285114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.2067729549 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 8522892947 ps |
| CPU time | 778.57 seconds |
| Started | Sep 09 11:46:16 AM UTC 24 |
| Finished | Sep 09 11:59:24 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067729549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2067729549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.3157935119 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1079069587 ps |
| CPU time | 50.31 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:47:07 AM UTC 24 |
| Peak memory | 269084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157935119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3157935119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.3908752791 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 461728608 ps |
| CPU time | 15.69 seconds |
| Started | Sep 09 11:46:15 AM UTC 24 |
| Finished | Sep 09 11:46:32 AM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908752791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3908752791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.3931925356 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 66982696698 ps |
| CPU time | 3467.06 seconds |
| Started | Sep 09 11:46:16 AM UTC 24 |
| Finished | Sep 09 12:44:39 PM UTC 24 |
| Peak memory | 321056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931925356 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.3931925356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/1.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.349053524 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1159249282 ps |
| CPU time | 20.76 seconds |
| Started | Sep 09 11:57:20 AM UTC 24 |
| Finished | Sep 09 11:57:42 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349053524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.349053524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.2403248115 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1638786123 ps |
| CPU time | 156.77 seconds |
| Started | Sep 09 11:56:40 AM UTC 24 |
| Finished | Sep 09 11:59:20 AM UTC 24 |
| Peak memory | 265016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403248115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2403248115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.1842630262 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1312403196 ps |
| CPU time | 71.63 seconds |
| Started | Sep 09 11:56:26 AM UTC 24 |
| Finished | Sep 09 11:57:39 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842630262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1842630262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.2780964365 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 27926537834 ps |
| CPU time | 1792.42 seconds |
| Started | Sep 09 11:57:04 AM UTC 24 |
| Finished | Sep 09 12:27:19 PM UTC 24 |
| Peak memory | 298180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780964365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2780964365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.4242526912 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 953279705 ps |
| CPU time | 38.64 seconds |
| Started | Sep 09 11:56:23 AM UTC 24 |
| Finished | Sep 09 11:57:03 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242526912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.4242526912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.410651614 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 579894540 ps |
| CPU time | 51.53 seconds |
| Started | Sep 09 11:56:25 AM UTC 24 |
| Finished | Sep 09 11:57:18 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410651614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.410651614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.544902050 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 116615380 ps |
| CPU time | 6 seconds |
| Started | Sep 09 11:56:49 AM UTC 24 |
| Finished | Sep 09 11:56:56 AM UTC 24 |
| Peak memory | 263264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544902050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.544902050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.533425709 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1035542774 ps |
| CPU time | 38.79 seconds |
| Started | Sep 09 11:56:14 AM UTC 24 |
| Finished | Sep 09 11:56:54 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533425709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.533425709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.3454693360 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 41264250821 ps |
| CPU time | 3031.72 seconds |
| Started | Sep 09 11:57:39 AM UTC 24 |
| Finished | Sep 09 12:48:45 PM UTC 24 |
| Peak memory | 315168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454693360 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.3454693360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.287468649 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 171612899 ps |
| CPU time | 5.21 seconds |
| Started | Sep 09 11:59:21 AM UTC 24 |
| Finished | Sep 09 11:59:27 AM UTC 24 |
| Peak memory | 263172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287468649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.287468649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.38553562 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 60452114906 ps |
| CPU time | 1536.7 seconds |
| Started | Sep 09 11:58:49 AM UTC 24 |
| Finished | Sep 09 12:24:43 PM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38553562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.38553562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.3241227929 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 526848500 ps |
| CPU time | 14.28 seconds |
| Started | Sep 09 11:59:04 AM UTC 24 |
| Finished | Sep 09 11:59:20 AM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241227929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3241227929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.2219861406 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 13465305671 ps |
| CPU time | 142.11 seconds |
| Started | Sep 09 11:58:28 AM UTC 24 |
| Finished | Sep 09 12:00:53 PM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219861406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2219861406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.1636438313 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1725894066 ps |
| CPU time | 37.78 seconds |
| Started | Sep 09 11:58:23 AM UTC 24 |
| Finished | Sep 09 11:59:02 AM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636438313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1636438313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.1089401952 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 30666350997 ps |
| CPU time | 1813.26 seconds |
| Started | Sep 09 11:59:03 AM UTC 24 |
| Finished | Sep 09 12:29:37 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089401952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1089401952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.918329536 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1440303833 ps |
| CPU time | 57.21 seconds |
| Started | Sep 09 11:57:49 AM UTC 24 |
| Finished | Sep 09 11:58:48 AM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918329536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.918329536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.1597417014 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 172909671 ps |
| CPU time | 29.93 seconds |
| Started | Sep 09 11:57:55 AM UTC 24 |
| Finished | Sep 09 11:58:27 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597417014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1597417014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.732593989 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 688234091 ps |
| CPU time | 31.59 seconds |
| Started | Sep 09 11:58:31 AM UTC 24 |
| Finished | Sep 09 11:59:04 AM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732593989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.732593989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.3842109564 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 991964592 ps |
| CPU time | 63.62 seconds |
| Started | Sep 09 11:57:43 AM UTC 24 |
| Finished | Sep 09 11:58:48 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842109564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3842109564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all_with_rand_reset.988111184 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 12718324750 ps |
| CPU time | 460.73 seconds |
| Started | Sep 09 11:59:26 AM UTC 24 |
| Finished | Sep 09 12:07:14 PM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=988111184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.al ert_handler_stress_all_with_rand_reset.988111184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.3305652126 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 12977560826 ps |
| CPU time | 1287.51 seconds |
| Started | Sep 09 12:01:29 PM UTC 24 |
| Finished | Sep 09 12:23:12 PM UTC 24 |
| Peak memory | 301952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305652126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3305652126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.1732918548 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1783234751 ps |
| CPU time | 33.82 seconds |
| Started | Sep 09 12:02:51 PM UTC 24 |
| Finished | Sep 09 12:03:26 PM UTC 24 |
| Peak memory | 262912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732918548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1732918548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.4109363318 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 403658976 ps |
| CPU time | 25.78 seconds |
| Started | Sep 09 12:01:01 PM UTC 24 |
| Finished | Sep 09 12:01:28 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109363318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.4109363318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.422114687 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 998145509 ps |
| CPU time | 37.43 seconds |
| Started | Sep 09 12:00:53 PM UTC 24 |
| Finished | Sep 09 12:01:32 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422114687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.422114687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.3082178370 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 540280981991 ps |
| CPU time | 2456.35 seconds |
| Started | Sep 09 12:01:37 PM UTC 24 |
| Finished | Sep 09 12:42:59 PM UTC 24 |
| Peak memory | 304680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082178370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3082178370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.3327861472 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 23318480969 ps |
| CPU time | 1709.03 seconds |
| Started | Sep 09 12:02:48 PM UTC 24 |
| Finished | Sep 09 12:31:37 PM UTC 24 |
| Peak memory | 285504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327861472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3327861472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.1050510025 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 5503531628 ps |
| CPU time | 86.35 seconds |
| Started | Sep 09 12:01:33 PM UTC 24 |
| Finished | Sep 09 12:03:01 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050510025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1050510025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.237226041 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 685091773 ps |
| CPU time | 66.85 seconds |
| Started | Sep 09 11:59:36 AM UTC 24 |
| Finished | Sep 09 12:00:45 PM UTC 24 |
| Peak memory | 269156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237226041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.237226041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.3013697478 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 324142828 ps |
| CPU time | 34.17 seconds |
| Started | Sep 09 12:00:46 PM UTC 24 |
| Finished | Sep 09 12:01:22 PM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013697478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3013697478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.3328740299 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 58787764 ps |
| CPU time | 5.79 seconds |
| Started | Sep 09 11:59:28 AM UTC 24 |
| Finished | Sep 09 11:59:34 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328740299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3328740299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.1367810793 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 62769781410 ps |
| CPU time | 2804.49 seconds |
| Started | Sep 09 12:03:02 PM UTC 24 |
| Finished | Sep 09 12:50:15 PM UTC 24 |
| Peak memory | 321312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367810793 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.1367810793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.1349579847 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 39321742 ps |
| CPU time | 5.39 seconds |
| Started | Sep 09 12:07:16 PM UTC 24 |
| Finished | Sep 09 12:07:22 PM UTC 24 |
| Peak memory | 263172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349579847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1349579847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.637425827 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 40890800786 ps |
| CPU time | 812.53 seconds |
| Started | Sep 09 12:05:39 PM UTC 24 |
| Finished | Sep 09 12:19:21 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637425827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.637425827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.3657056811 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 791133923 ps |
| CPU time | 18.65 seconds |
| Started | Sep 09 12:06:38 PM UTC 24 |
| Finished | Sep 09 12:06:58 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657056811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3657056811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.2664994547 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1418331357 ps |
| CPU time | 162.49 seconds |
| Started | Sep 09 12:05:13 PM UTC 24 |
| Finished | Sep 09 12:07:59 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664994547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2664994547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.2056878629 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 313449985 ps |
| CPU time | 36.52 seconds |
| Started | Sep 09 12:05:00 PM UTC 24 |
| Finished | Sep 09 12:05:38 PM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056878629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2056878629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.2020086715 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 33297691343 ps |
| CPU time | 1481.98 seconds |
| Started | Sep 09 12:05:52 PM UTC 24 |
| Finished | Sep 09 12:30:51 PM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020086715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2020086715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.393762597 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 52607532068 ps |
| CPU time | 1504.03 seconds |
| Started | Sep 09 12:06:06 PM UTC 24 |
| Finished | Sep 09 12:31:28 PM UTC 24 |
| Peak memory | 301960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393762597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.393762597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.2585946010 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2196618602 ps |
| CPU time | 133.89 seconds |
| Started | Sep 09 12:05:46 PM UTC 24 |
| Finished | Sep 09 12:08:02 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585946010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2585946010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.2561928119 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 427946448 ps |
| CPU time | 39.65 seconds |
| Started | Sep 09 12:04:03 PM UTC 24 |
| Finished | Sep 09 12:04:44 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561928119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2561928119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.525073719 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 688487409 ps |
| CPU time | 26.32 seconds |
| Started | Sep 09 12:04:45 PM UTC 24 |
| Finished | Sep 09 12:05:12 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525073719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.525073719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.3366168323 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 317955377 ps |
| CPU time | 39.76 seconds |
| Started | Sep 09 12:05:24 PM UTC 24 |
| Finished | Sep 09 12:06:05 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366168323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3366168323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.2196041445 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2632232835 ps |
| CPU time | 33.25 seconds |
| Started | Sep 09 12:03:27 PM UTC 24 |
| Finished | Sep 09 12:04:02 PM UTC 24 |
| Peak memory | 263040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196041445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2196041445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.301524696 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2798180082 ps |
| CPU time | 52.11 seconds |
| Started | Sep 09 12:07:00 PM UTC 24 |
| Finished | Sep 09 12:07:53 PM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301524696 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.301524696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all_with_rand_reset.361901927 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2358912781 ps |
| CPU time | 166.14 seconds |
| Started | Sep 09 12:07:24 PM UTC 24 |
| Finished | Sep 09 12:10:13 PM UTC 24 |
| Peak memory | 279480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=361901927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.al ert_handler_stress_all_with_rand_reset.361901927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.643409771 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 140889747 ps |
| CPU time | 4.87 seconds |
| Started | Sep 09 12:09:27 PM UTC 24 |
| Finished | Sep 09 12:09:33 PM UTC 24 |
| Peak memory | 263168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643409771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.643409771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.2234554299 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 14902366197 ps |
| CPU time | 1562.35 seconds |
| Started | Sep 09 12:08:27 PM UTC 24 |
| Finished | Sep 09 12:34:47 PM UTC 24 |
| Peak memory | 300160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234554299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2234554299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.2340406608 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 378279746 ps |
| CPU time | 16.59 seconds |
| Started | Sep 09 12:09:17 PM UTC 24 |
| Finished | Sep 09 12:09:35 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340406608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2340406608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.3333078765 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 468234491 ps |
| CPU time | 9.19 seconds |
| Started | Sep 09 12:08:23 PM UTC 24 |
| Finished | Sep 09 12:08:33 PM UTC 24 |
| Peak memory | 264940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333078765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3333078765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.369773602 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1377195480 ps |
| CPU time | 17.86 seconds |
| Started | Sep 09 12:08:03 PM UTC 24 |
| Finished | Sep 09 12:08:22 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369773602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.369773602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.4195537454 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 113294569141 ps |
| CPU time | 1935.83 seconds |
| Started | Sep 09 12:08:47 PM UTC 24 |
| Finished | Sep 09 12:41:25 PM UTC 24 |
| Peak memory | 288224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195537454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.4195537454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.1752416570 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 12965074317 ps |
| CPU time | 1289.38 seconds |
| Started | Sep 09 12:09:16 PM UTC 24 |
| Finished | Sep 09 12:31:00 PM UTC 24 |
| Peak memory | 301960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752416570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1752416570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.464487632 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 67746057249 ps |
| CPU time | 572.84 seconds |
| Started | Sep 09 12:08:34 PM UTC 24 |
| Finished | Sep 09 12:18:14 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464487632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.464487632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.4269547001 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 879696815 ps |
| CPU time | 82.26 seconds |
| Started | Sep 09 12:07:54 PM UTC 24 |
| Finished | Sep 09 12:09:19 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269547001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.4269547001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.4166820504 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 192373183 ps |
| CPU time | 24.58 seconds |
| Started | Sep 09 12:08:00 PM UTC 24 |
| Finished | Sep 09 12:08:26 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166820504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4166820504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.288153891 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1929421263 ps |
| CPU time | 46.62 seconds |
| Started | Sep 09 12:07:38 PM UTC 24 |
| Finished | Sep 09 12:08:27 PM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288153891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.288153891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.2029428130 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 56589365171 ps |
| CPU time | 3774.83 seconds |
| Started | Sep 09 12:09:19 PM UTC 24 |
| Finished | Sep 09 01:13:00 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029428130 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.2029428130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all_with_rand_reset.1664954295 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 6654176088 ps |
| CPU time | 254.5 seconds |
| Started | Sep 09 12:09:34 PM UTC 24 |
| Finished | Sep 09 12:13:52 PM UTC 24 |
| Peak memory | 281524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1664954295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.a lert_handler_stress_all_with_rand_reset.1664954295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.864153072 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 41001587 ps |
| CPU time | 3.63 seconds |
| Started | Sep 09 12:13:35 PM UTC 24 |
| Finished | Sep 09 12:13:39 PM UTC 24 |
| Peak memory | 263308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864153072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.864153072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.4055063565 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 84715001890 ps |
| CPU time | 2213.11 seconds |
| Started | Sep 09 12:11:11 PM UTC 24 |
| Finished | Sep 09 12:48:26 PM UTC 24 |
| Peak memory | 304868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055063565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.4055063565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.1264188940 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 578732855 ps |
| CPU time | 12.96 seconds |
| Started | Sep 09 12:13:19 PM UTC 24 |
| Finished | Sep 09 12:13:34 PM UTC 24 |
| Peak memory | 263240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264188940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1264188940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.4096211982 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1092440862 ps |
| CPU time | 115.61 seconds |
| Started | Sep 09 12:10:50 PM UTC 24 |
| Finished | Sep 09 12:12:48 PM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096211982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.4096211982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.200166473 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1629738635 ps |
| CPU time | 27.83 seconds |
| Started | Sep 09 12:10:42 PM UTC 24 |
| Finished | Sep 09 12:11:11 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200166473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.200166473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.1150595753 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 15188646209 ps |
| CPU time | 783.93 seconds |
| Started | Sep 09 12:12:49 PM UTC 24 |
| Finished | Sep 09 12:26:02 PM UTC 24 |
| Peak memory | 285832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150595753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1150595753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.2244305861 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1572569625 ps |
| CPU time | 24.53 seconds |
| Started | Sep 09 12:10:14 PM UTC 24 |
| Finished | Sep 09 12:10:40 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244305861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2244305861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.2494061172 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 795083422 ps |
| CPU time | 30.82 seconds |
| Started | Sep 09 12:10:16 PM UTC 24 |
| Finished | Sep 09 12:10:48 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494061172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2494061172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.4209093464 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 7974960671 ps |
| CPU time | 41.15 seconds |
| Started | Sep 09 12:11:02 PM UTC 24 |
| Finished | Sep 09 12:11:45 PM UTC 24 |
| Peak memory | 263164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209093464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.4209093464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.2513855330 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 427163331 ps |
| CPU time | 38.68 seconds |
| Started | Sep 09 12:09:36 PM UTC 24 |
| Finished | Sep 09 12:10:16 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513855330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2513855330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.1194025495 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2057782662 ps |
| CPU time | 157.96 seconds |
| Started | Sep 09 12:13:31 PM UTC 24 |
| Finished | Sep 09 12:16:11 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194025495 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.1194025495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all_with_rand_reset.601001068 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 6838858652 ps |
| CPU time | 438.32 seconds |
| Started | Sep 09 12:13:40 PM UTC 24 |
| Finished | Sep 09 12:21:04 PM UTC 24 |
| Peak memory | 285696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=601001068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.al ert_handler_stress_all_with_rand_reset.601001068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.3465936822 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 31230629 ps |
| CPU time | 4.76 seconds |
| Started | Sep 09 12:17:21 PM UTC 24 |
| Finished | Sep 09 12:17:27 PM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465936822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3465936822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.1455888895 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 179750745235 ps |
| CPU time | 2979.02 seconds |
| Started | Sep 09 12:15:16 PM UTC 24 |
| Finished | Sep 09 01:05:28 PM UTC 24 |
| Peak memory | 302552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455888895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1455888895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.1042949429 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4851059455 ps |
| CPU time | 143.46 seconds |
| Started | Sep 09 12:16:34 PM UTC 24 |
| Finished | Sep 09 12:19:00 PM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042949429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1042949429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.2022129636 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2129323214 ps |
| CPU time | 153.58 seconds |
| Started | Sep 09 12:14:44 PM UTC 24 |
| Finished | Sep 09 12:17:20 PM UTC 24 |
| Peak memory | 263160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022129636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2022129636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.1630669764 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 77464749 ps |
| CPU time | 8.2 seconds |
| Started | Sep 09 12:14:38 PM UTC 24 |
| Finished | Sep 09 12:14:47 PM UTC 24 |
| Peak memory | 253024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630669764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1630669764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.4278064523 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 14221839228 ps |
| CPU time | 645.91 seconds |
| Started | Sep 09 12:16:12 PM UTC 24 |
| Finished | Sep 09 12:27:06 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278064523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4278064523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.1813685449 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 204600817745 ps |
| CPU time | 1682.47 seconds |
| Started | Sep 09 12:16:30 PM UTC 24 |
| Finished | Sep 09 12:44:51 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813685449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1813685449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.65261825 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 7174189561 ps |
| CPU time | 266.24 seconds |
| Started | Sep 09 12:15:47 PM UTC 24 |
| Finished | Sep 09 12:20:17 PM UTC 24 |
| Peak memory | 263300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65261825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.65261825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.3653755224 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1768621742 ps |
| CPU time | 79.6 seconds |
| Started | Sep 09 12:13:53 PM UTC 24 |
| Finished | Sep 09 12:15:15 PM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653755224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3653755224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.4171290815 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 448295092 ps |
| CPU time | 38.95 seconds |
| Started | Sep 09 12:14:02 PM UTC 24 |
| Finished | Sep 09 12:14:43 PM UTC 24 |
| Peak memory | 269468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171290815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.4171290815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.3175522972 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1116646642 ps |
| CPU time | 56.58 seconds |
| Started | Sep 09 12:14:48 PM UTC 24 |
| Finished | Sep 09 12:15:46 PM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175522972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3175522972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.2991123535 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 78877575 ps |
| CPU time | 13.74 seconds |
| Started | Sep 09 12:13:47 PM UTC 24 |
| Finished | Sep 09 12:14:02 PM UTC 24 |
| Peak memory | 269248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991123535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2991123535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all_with_rand_reset.54921207 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 11328811638 ps |
| CPU time | 656.06 seconds |
| Started | Sep 09 12:17:27 PM UTC 24 |
| Finished | Sep 09 12:28:31 PM UTC 24 |
| Peak memory | 283652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=54921207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.ale rt_handler_stress_all_with_rand_reset.54921207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.683805204 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 169811841 ps |
| CPU time | 4.82 seconds |
| Started | Sep 09 12:21:05 PM UTC 24 |
| Finished | Sep 09 12:21:11 PM UTC 24 |
| Peak memory | 263172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683805204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.683805204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.3551281756 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 54254747893 ps |
| CPU time | 1021.59 seconds |
| Started | Sep 09 12:20:14 PM UTC 24 |
| Finished | Sep 09 12:37:27 PM UTC 24 |
| Peak memory | 299840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551281756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3551281756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.3257791155 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1334034898 ps |
| CPU time | 27.45 seconds |
| Started | Sep 09 12:20:38 PM UTC 24 |
| Finished | Sep 09 12:21:07 PM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257791155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3257791155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.1755878715 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2961027136 ps |
| CPU time | 234.86 seconds |
| Started | Sep 09 12:19:23 PM UTC 24 |
| Finished | Sep 09 12:23:22 PM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755878715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1755878715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.2051372720 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 5014304891 ps |
| CPU time | 70.07 seconds |
| Started | Sep 09 12:19:00 PM UTC 24 |
| Finished | Sep 09 12:20:12 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051372720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2051372720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.998006037 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 10196139269 ps |
| CPU time | 973.08 seconds |
| Started | Sep 09 12:20:16 PM UTC 24 |
| Finished | Sep 09 12:36:40 PM UTC 24 |
| Peak memory | 297856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998006037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.998006037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.333213909 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 16179307955 ps |
| CPU time | 1413.42 seconds |
| Started | Sep 09 12:20:18 PM UTC 24 |
| Finished | Sep 09 12:44:07 PM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333213909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.333213909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.1108240431 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 194483084 ps |
| CPU time | 27.89 seconds |
| Started | Sep 09 12:18:25 PM UTC 24 |
| Finished | Sep 09 12:18:54 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108240431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1108240431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.4274788693 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 4580695559 ps |
| CPU time | 78.08 seconds |
| Started | Sep 09 12:18:55 PM UTC 24 |
| Finished | Sep 09 12:20:15 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274788693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4274788693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.1512215906 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1186700172 ps |
| CPU time | 60 seconds |
| Started | Sep 09 12:19:35 PM UTC 24 |
| Finished | Sep 09 12:20:37 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512215906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1512215906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.4253061956 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 72966397 ps |
| CPU time | 7.18 seconds |
| Started | Sep 09 12:18:16 PM UTC 24 |
| Finished | Sep 09 12:18:24 PM UTC 24 |
| Peak memory | 264952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253061956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4253061956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.2758958111 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 10542282800 ps |
| CPU time | 1126.83 seconds |
| Started | Sep 09 12:20:59 PM UTC 24 |
| Finished | Sep 09 12:39:59 PM UTC 24 |
| Peak memory | 301876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758958111 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.2758958111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all_with_rand_reset.919678429 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2268095018 ps |
| CPU time | 143.84 seconds |
| Started | Sep 09 12:21:08 PM UTC 24 |
| Finished | Sep 09 12:23:35 PM UTC 24 |
| Peak memory | 279480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=919678429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.al ert_handler_stress_all_with_rand_reset.919678429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.972157672 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 450909528 ps |
| CPU time | 5.45 seconds |
| Started | Sep 09 12:24:27 PM UTC 24 |
| Finished | Sep 09 12:24:34 PM UTC 24 |
| Peak memory | 263168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972157672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.972157672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.3022159464 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 47412504618 ps |
| CPU time | 522.64 seconds |
| Started | Sep 09 12:23:14 PM UTC 24 |
| Finished | Sep 09 12:32:03 PM UTC 24 |
| Peak memory | 279680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022159464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3022159464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.4145326759 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 460742551 ps |
| CPU time | 35.09 seconds |
| Started | Sep 09 12:23:50 PM UTC 24 |
| Finished | Sep 09 12:24:26 PM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145326759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.4145326759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.1272257473 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 31892533665 ps |
| CPU time | 138.88 seconds |
| Started | Sep 09 12:21:57 PM UTC 24 |
| Finished | Sep 09 12:24:18 PM UTC 24 |
| Peak memory | 269104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272257473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1272257473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.1754104881 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 9094356462 ps |
| CPU time | 57.78 seconds |
| Started | Sep 09 12:21:55 PM UTC 24 |
| Finished | Sep 09 12:22:54 PM UTC 24 |
| Peak memory | 263392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754104881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1754104881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.3898126462 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 19708790036 ps |
| CPU time | 917.95 seconds |
| Started | Sep 09 12:23:24 PM UTC 24 |
| Finished | Sep 09 12:38:53 PM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898126462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3898126462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.3268404980 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 81544037403 ps |
| CPU time | 1178.38 seconds |
| Started | Sep 09 12:23:36 PM UTC 24 |
| Finished | Sep 09 12:43:27 PM UTC 24 |
| Peak memory | 279560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268404980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3268404980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.1513129938 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 9328211725 ps |
| CPU time | 151.34 seconds |
| Started | Sep 09 12:23:23 PM UTC 24 |
| Finished | Sep 09 12:25:57 PM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513129938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1513129938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.3489622782 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 724125602 ps |
| CPU time | 17.54 seconds |
| Started | Sep 09 12:21:36 PM UTC 24 |
| Finished | Sep 09 12:21:54 PM UTC 24 |
| Peak memory | 267324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489622782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3489622782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.306611147 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 76292385 ps |
| CPU time | 15.35 seconds |
| Started | Sep 09 12:21:40 PM UTC 24 |
| Finished | Sep 09 12:21:56 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306611147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.306611147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.717457109 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 813380605 ps |
| CPU time | 26.56 seconds |
| Started | Sep 09 12:22:55 PM UTC 24 |
| Finished | Sep 09 12:23:23 PM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717457109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.717457109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.3056193268 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1069616807 ps |
| CPU time | 22.01 seconds |
| Started | Sep 09 12:21:11 PM UTC 24 |
| Finished | Sep 09 12:21:35 PM UTC 24 |
| Peak memory | 263232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056193268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3056193268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all_with_rand_reset.385401713 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 7500941073 ps |
| CPU time | 311.12 seconds |
| Started | Sep 09 12:24:34 PM UTC 24 |
| Finished | Sep 09 12:29:50 PM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=385401713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.al ert_handler_stress_all_with_rand_reset.385401713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.3142395145 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 17752984 ps |
| CPU time | 4.25 seconds |
| Started | Sep 09 12:27:09 PM UTC 24 |
| Finished | Sep 09 12:27:14 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142395145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3142395145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.2595434964 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 88710996342 ps |
| CPU time | 2550.61 seconds |
| Started | Sep 09 12:26:31 PM UTC 24 |
| Finished | Sep 09 01:09:31 PM UTC 24 |
| Peak memory | 304932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595434964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2595434964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.255926412 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 342479518 ps |
| CPU time | 15.67 seconds |
| Started | Sep 09 12:26:51 PM UTC 24 |
| Finished | Sep 09 12:27:08 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255926412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.255926412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.2736589749 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 621112205 ps |
| CPU time | 72.18 seconds |
| Started | Sep 09 12:26:04 PM UTC 24 |
| Finished | Sep 09 12:27:18 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736589749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2736589749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.1540170855 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 461738943 ps |
| CPU time | 30.91 seconds |
| Started | Sep 09 12:25:58 PM UTC 24 |
| Finished | Sep 09 12:26:30 PM UTC 24 |
| Peak memory | 269408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540170855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1540170855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.2509249803 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 159766700899 ps |
| CPU time | 883.96 seconds |
| Started | Sep 09 12:26:45 PM UTC 24 |
| Finished | Sep 09 12:41:39 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509249803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2509249803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.2189689362 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 33068848658 ps |
| CPU time | 1442.88 seconds |
| Started | Sep 09 12:26:50 PM UTC 24 |
| Finished | Sep 09 12:51:09 PM UTC 24 |
| Peak memory | 303428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189689362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2189689362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.1571968067 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2946242286 ps |
| CPU time | 208.93 seconds |
| Started | Sep 09 12:26:41 PM UTC 24 |
| Finished | Sep 09 12:30:14 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571968067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1571968067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.2022360310 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 228925431 ps |
| CPU time | 21.94 seconds |
| Started | Sep 09 12:25:16 PM UTC 24 |
| Finished | Sep 09 12:25:39 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022360310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2022360310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.3709747883 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 747722906 ps |
| CPU time | 67.21 seconds |
| Started | Sep 09 12:25:40 PM UTC 24 |
| Finished | Sep 09 12:26:49 PM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709747883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3709747883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.968005742 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 372495425 ps |
| CPU time | 35.21 seconds |
| Started | Sep 09 12:26:14 PM UTC 24 |
| Finished | Sep 09 12:26:51 PM UTC 24 |
| Peak memory | 269408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968005742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.968005742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.703114616 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1505004905 ps |
| CPU time | 26.84 seconds |
| Started | Sep 09 12:24:46 PM UTC 24 |
| Finished | Sep 09 12:25:15 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703114616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.703114616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.2682537577 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 39675829553 ps |
| CPU time | 2712.9 seconds |
| Started | Sep 09 12:27:08 PM UTC 24 |
| Finished | Sep 09 01:12:51 PM UTC 24 |
| Peak memory | 304672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682537577 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.2682537577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/19.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.1046624530 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 35563896 ps |
| CPU time | 4.88 seconds |
| Started | Sep 09 11:46:41 AM UTC 24 |
| Finished | Sep 09 11:46:47 AM UTC 24 |
| Peak memory | 263500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046624530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1046624530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.2962082745 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 26722994059 ps |
| CPU time | 1152.34 seconds |
| Started | Sep 09 11:46:26 AM UTC 24 |
| Finished | Sep 09 12:05:50 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962082745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2962082745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.3668572680 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4210843215 ps |
| CPU time | 68.82 seconds |
| Started | Sep 09 11:46:36 AM UTC 24 |
| Finished | Sep 09 11:47:47 AM UTC 24 |
| Peak memory | 263300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668572680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3668572680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.2471369965 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 38207449035 ps |
| CPU time | 123.96 seconds |
| Started | Sep 09 11:46:24 AM UTC 24 |
| Finished | Sep 09 11:48:30 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471369965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2471369965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.2201777554 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 18228833530 ps |
| CPU time | 1775.13 seconds |
| Started | Sep 09 11:46:33 AM UTC 24 |
| Finished | Sep 09 12:16:28 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201777554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2201777554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.1703184289 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 14622573746 ps |
| CPU time | 960.82 seconds |
| Started | Sep 09 11:46:33 AM UTC 24 |
| Finished | Sep 09 12:02:46 PM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703184289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1703184289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.2214336432 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 80258059334 ps |
| CPU time | 196.47 seconds |
| Started | Sep 09 11:46:28 AM UTC 24 |
| Finished | Sep 09 11:49:47 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214336432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2214336432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.182060805 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 585999408 ps |
| CPU time | 14.65 seconds |
| Started | Sep 09 11:46:20 AM UTC 24 |
| Finished | Sep 09 11:46:36 AM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182060805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.182060805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.3898095434 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1191970608 ps |
| CPU time | 102.16 seconds |
| Started | Sep 09 11:46:22 AM UTC 24 |
| Finished | Sep 09 11:48:06 AM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898095434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3898095434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.3770660314 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3091610450 ps |
| CPU time | 21.98 seconds |
| Started | Sep 09 11:46:45 AM UTC 24 |
| Finished | Sep 09 11:47:08 AM UTC 24 |
| Peak memory | 295404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770660314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3770660314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.4012916752 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 713507805 ps |
| CPU time | 23.09 seconds |
| Started | Sep 09 11:46:20 AM UTC 24 |
| Finished | Sep 09 11:46:44 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012916752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4012916752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.3762496666 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 182339154530 ps |
| CPU time | 3147.72 seconds |
| Started | Sep 09 11:46:39 AM UTC 24 |
| Finished | Sep 09 12:39:43 PM UTC 24 |
| Peak memory | 304928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762496666 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.3762496666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/2.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.3346402160 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 231068541587 ps |
| CPU time | 3204.06 seconds |
| Started | Sep 09 12:28:33 PM UTC 24 |
| Finished | Sep 09 01:22:32 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346402160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3346402160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.4143445371 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 331245294 ps |
| CPU time | 41.59 seconds |
| Started | Sep 09 12:28:06 PM UTC 24 |
| Finished | Sep 09 12:28:50 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143445371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4143445371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.635591155 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3581003843 ps |
| CPU time | 47.97 seconds |
| Started | Sep 09 12:27:45 PM UTC 24 |
| Finished | Sep 09 12:28:35 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635591155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.635591155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.2085317777 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 54324818233 ps |
| CPU time | 1341.37 seconds |
| Started | Sep 09 12:28:42 PM UTC 24 |
| Finished | Sep 09 12:51:19 PM UTC 24 |
| Peak memory | 302084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085317777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2085317777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.1556087914 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 42732557338 ps |
| CPU time | 2243.32 seconds |
| Started | Sep 09 12:28:51 PM UTC 24 |
| Finished | Sep 09 01:06:38 PM UTC 24 |
| Peak memory | 304684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556087914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1556087914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.3505568775 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 41369594816 ps |
| CPU time | 337.69 seconds |
| Started | Sep 09 12:28:35 PM UTC 24 |
| Finished | Sep 09 12:34:17 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505568775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3505568775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.2759030062 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1165686954 ps |
| CPU time | 43.95 seconds |
| Started | Sep 09 12:27:20 PM UTC 24 |
| Finished | Sep 09 12:28:06 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759030062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2759030062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.2112655369 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 987489430 ps |
| CPU time | 20.43 seconds |
| Started | Sep 09 12:27:23 PM UTC 24 |
| Finished | Sep 09 12:27:45 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112655369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2112655369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.3634041262 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 421627147 ps |
| CPU time | 33.6 seconds |
| Started | Sep 09 12:28:07 PM UTC 24 |
| Finished | Sep 09 12:28:42 PM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634041262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3634041262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.834154854 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 3455828117 ps |
| CPU time | 43.89 seconds |
| Started | Sep 09 12:27:20 PM UTC 24 |
| Finished | Sep 09 12:28:06 PM UTC 24 |
| Peak memory | 263292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834154854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.834154854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.1083405958 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 234276817419 ps |
| CPU time | 1308.99 seconds |
| Started | Sep 09 12:28:57 PM UTC 24 |
| Finished | Sep 09 12:51:01 PM UTC 24 |
| Peak memory | 301948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083405958 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.1083405958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.3430312834 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 970830401 ps |
| CPU time | 135.32 seconds |
| Started | Sep 09 12:29:24 PM UTC 24 |
| Finished | Sep 09 12:31:42 PM UTC 24 |
| Peak memory | 279612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3430312834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a lert_handler_stress_all_with_rand_reset.3430312834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.3586902311 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 8409765413 ps |
| CPU time | 874.25 seconds |
| Started | Sep 09 12:30:50 PM UTC 24 |
| Finished | Sep 09 12:45:35 PM UTC 24 |
| Peak memory | 285568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586902311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3586902311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.1523416205 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3122843486 ps |
| CPU time | 166.54 seconds |
| Started | Sep 09 12:30:25 PM UTC 24 |
| Finished | Sep 09 12:33:15 PM UTC 24 |
| Peak memory | 269100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523416205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1523416205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.3746516638 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 692911834 ps |
| CPU time | 64.79 seconds |
| Started | Sep 09 12:30:22 PM UTC 24 |
| Finished | Sep 09 12:31:29 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746516638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3746516638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.1195911117 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 32966991463 ps |
| CPU time | 1668.06 seconds |
| Started | Sep 09 12:31:02 PM UTC 24 |
| Finished | Sep 09 12:59:09 PM UTC 24 |
| Peak memory | 288616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195911117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1195911117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.202347369 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 128139581366 ps |
| CPU time | 1723.24 seconds |
| Started | Sep 09 12:31:30 PM UTC 24 |
| Finished | Sep 09 01:00:32 PM UTC 24 |
| Peak memory | 302560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202347369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.202347369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.2877448729 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 17255559961 ps |
| CPU time | 149.75 seconds |
| Started | Sep 09 12:30:53 PM UTC 24 |
| Finished | Sep 09 12:33:25 PM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877448729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2877448729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.4038754361 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 507294224 ps |
| CPU time | 31.66 seconds |
| Started | Sep 09 12:29:51 PM UTC 24 |
| Finished | Sep 09 12:30:24 PM UTC 24 |
| Peak memory | 269436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038754361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.4038754361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.1368109461 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1577679420 ps |
| CPU time | 33.63 seconds |
| Started | Sep 09 12:30:15 PM UTC 24 |
| Finished | Sep 09 12:30:50 PM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368109461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1368109461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.1395865003 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2621028325 ps |
| CPU time | 57.37 seconds |
| Started | Sep 09 12:29:38 PM UTC 24 |
| Finished | Sep 09 12:30:38 PM UTC 24 |
| Peak memory | 269184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395865003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1395865003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.2510163008 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 15495798110 ps |
| CPU time | 1734.77 seconds |
| Started | Sep 09 12:31:31 PM UTC 24 |
| Finished | Sep 09 01:00:45 PM UTC 24 |
| Peak memory | 304672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510163008 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.2510163008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all_with_rand_reset.2187701464 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 50034100462 ps |
| CPU time | 491.67 seconds |
| Started | Sep 09 12:31:35 PM UTC 24 |
| Finished | Sep 09 12:39:53 PM UTC 24 |
| Peak memory | 297908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2187701464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.a lert_handler_stress_all_with_rand_reset.2187701464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.1652075521 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 71561345840 ps |
| CPU time | 1061.98 seconds |
| Started | Sep 09 12:32:52 PM UTC 24 |
| Finished | Sep 09 12:50:45 PM UTC 24 |
| Peak memory | 285824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652075521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1652075521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.2855049331 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 24844669949 ps |
| CPU time | 215.36 seconds |
| Started | Sep 09 12:32:17 PM UTC 24 |
| Finished | Sep 09 12:35:56 PM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855049331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2855049331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.1967197773 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2723529634 ps |
| CPU time | 32.69 seconds |
| Started | Sep 09 12:32:16 PM UTC 24 |
| Finished | Sep 09 12:32:50 PM UTC 24 |
| Peak memory | 263200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967197773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1967197773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.3451339411 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 95359611529 ps |
| CPU time | 1519 seconds |
| Started | Sep 09 12:33:19 PM UTC 24 |
| Finished | Sep 09 12:58:55 PM UTC 24 |
| Peak memory | 302212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451339411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3451339411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.261158790 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 32000618704 ps |
| CPU time | 1331.46 seconds |
| Started | Sep 09 12:33:27 PM UTC 24 |
| Finished | Sep 09 12:55:54 PM UTC 24 |
| Peak memory | 279432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261158790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.261158790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.3027666080 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 44160158020 ps |
| CPU time | 403.4 seconds |
| Started | Sep 09 12:33:16 PM UTC 24 |
| Finished | Sep 09 12:40:05 PM UTC 24 |
| Peak memory | 269192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027666080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3027666080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.1143174259 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 846752644 ps |
| CPU time | 31.16 seconds |
| Started | Sep 09 12:31:43 PM UTC 24 |
| Finished | Sep 09 12:32:15 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143174259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1143174259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.315908881 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 1466805700 ps |
| CPU time | 40.38 seconds |
| Started | Sep 09 12:32:04 PM UTC 24 |
| Finished | Sep 09 12:32:46 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315908881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.315908881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.3878701850 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 245122579 ps |
| CPU time | 44.45 seconds |
| Started | Sep 09 12:32:46 PM UTC 24 |
| Finished | Sep 09 12:33:32 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878701850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3878701850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.2857232936 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 676981774 ps |
| CPU time | 36.19 seconds |
| Started | Sep 09 12:31:39 PM UTC 24 |
| Finished | Sep 09 12:32:17 PM UTC 24 |
| Peak memory | 269440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857232936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2857232936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all_with_rand_reset.322919428 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 5022760163 ps |
| CPU time | 116.92 seconds |
| Started | Sep 09 12:34:09 PM UTC 24 |
| Finished | Sep 09 12:36:08 PM UTC 24 |
| Peak memory | 279556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=322919428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.al ert_handler_stress_all_with_rand_reset.322919428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.1401185042 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 26946407469 ps |
| CPU time | 797.8 seconds |
| Started | Sep 09 12:35:53 PM UTC 24 |
| Finished | Sep 09 12:49:20 PM UTC 24 |
| Peak memory | 285492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401185042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1401185042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.3583883214 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2671754777 ps |
| CPU time | 21.12 seconds |
| Started | Sep 09 12:35:21 PM UTC 24 |
| Finished | Sep 09 12:35:43 PM UTC 24 |
| Peak memory | 269104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583883214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3583883214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.3099196284 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1721479573 ps |
| CPU time | 54.94 seconds |
| Started | Sep 09 12:34:55 PM UTC 24 |
| Finished | Sep 09 12:35:52 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099196284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3099196284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.2003625635 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 40259206186 ps |
| CPU time | 2472.61 seconds |
| Started | Sep 09 12:36:09 PM UTC 24 |
| Finished | Sep 09 01:17:51 PM UTC 24 |
| Peak memory | 288296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003625635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2003625635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.4151378133 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 35805340866 ps |
| CPU time | 2165.98 seconds |
| Started | Sep 09 12:36:12 PM UTC 24 |
| Finished | Sep 09 01:12:42 PM UTC 24 |
| Peak memory | 304684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151378133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4151378133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.1060189488 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 8396059500 ps |
| CPU time | 281.7 seconds |
| Started | Sep 09 12:35:57 PM UTC 24 |
| Finished | Sep 09 12:40:42 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060189488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1060189488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.3113482813 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 163711436 ps |
| CPU time | 19.69 seconds |
| Started | Sep 09 12:34:33 PM UTC 24 |
| Finished | Sep 09 12:34:54 PM UTC 24 |
| Peak memory | 269436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113482813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3113482813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.2623098797 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1134936969 ps |
| CPU time | 91.78 seconds |
| Started | Sep 09 12:34:50 PM UTC 24 |
| Finished | Sep 09 12:36:24 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623098797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2623098797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.1092954323 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 241011062 ps |
| CPU time | 12.96 seconds |
| Started | Sep 09 12:34:18 PM UTC 24 |
| Finished | Sep 09 12:34:32 PM UTC 24 |
| Peak memory | 263040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092954323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1092954323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.3362237912 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 4718455033 ps |
| CPU time | 367.61 seconds |
| Started | Sep 09 12:36:25 PM UTC 24 |
| Finished | Sep 09 12:42:37 PM UTC 24 |
| Peak memory | 279420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362237912 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.3362237912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/23.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.1469975535 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 52805874643 ps |
| CPU time | 1684.47 seconds |
| Started | Sep 09 12:39:45 PM UTC 24 |
| Finished | Sep 09 01:08:08 PM UTC 24 |
| Peak memory | 304676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469975535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1469975535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.1851504494 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 9435616461 ps |
| CPU time | 133.44 seconds |
| Started | Sep 09 12:38:55 PM UTC 24 |
| Finished | Sep 09 12:41:11 PM UTC 24 |
| Peak memory | 269104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851504494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1851504494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.972471361 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 324124260 ps |
| CPU time | 15.95 seconds |
| Started | Sep 09 12:38:38 PM UTC 24 |
| Finished | Sep 09 12:38:55 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972471361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.972471361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.1167375143 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 28467551241 ps |
| CPU time | 1523.63 seconds |
| Started | Sep 09 12:40:01 PM UTC 24 |
| Finished | Sep 09 01:05:42 PM UTC 24 |
| Peak memory | 302148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167375143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1167375143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.3928933239 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 39200072792 ps |
| CPU time | 979.73 seconds |
| Started | Sep 09 12:40:06 PM UTC 24 |
| Finished | Sep 09 12:56:38 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928933239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3928933239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.2219810355 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 56511884842 ps |
| CPU time | 761.59 seconds |
| Started | Sep 09 12:39:55 PM UTC 24 |
| Finished | Sep 09 12:52:46 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219810355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2219810355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.87277634 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 3610867660 ps |
| CPU time | 44.01 seconds |
| Started | Sep 09 12:37:38 PM UTC 24 |
| Finished | Sep 09 12:38:24 PM UTC 24 |
| Peak memory | 269216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87277634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.87277634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.81271603 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 206476961 ps |
| CPU time | 11.06 seconds |
| Started | Sep 09 12:38:25 PM UTC 24 |
| Finished | Sep 09 12:38:37 PM UTC 24 |
| Peak memory | 263032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81271603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.81271603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.2506819302 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 4528160521 ps |
| CPU time | 97.63 seconds |
| Started | Sep 09 12:38:56 PM UTC 24 |
| Finished | Sep 09 12:40:36 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506819302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2506819302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.2131133340 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1804414518 ps |
| CPU time | 7.48 seconds |
| Started | Sep 09 12:37:29 PM UTC 24 |
| Finished | Sep 09 12:37:38 PM UTC 24 |
| Peak memory | 264952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131133340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2131133340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.2560214718 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 15368112007 ps |
| CPU time | 912.57 seconds |
| Started | Sep 09 12:40:36 PM UTC 24 |
| Finished | Sep 09 12:55:59 PM UTC 24 |
| Peak memory | 281532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560214718 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.2560214718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all_with_rand_reset.1111906338 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 17052588993 ps |
| CPU time | 201.96 seconds |
| Started | Sep 09 12:40:43 PM UTC 24 |
| Finished | Sep 09 12:44:09 PM UTC 24 |
| Peak memory | 281524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1111906338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.a lert_handler_stress_all_with_rand_reset.1111906338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.3643714818 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 50494883731 ps |
| CPU time | 1483.87 seconds |
| Started | Sep 09 12:41:35 PM UTC 24 |
| Finished | Sep 09 01:06:36 PM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643714818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3643714818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.3698602616 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 4398112882 ps |
| CPU time | 93.49 seconds |
| Started | Sep 09 12:41:26 PM UTC 24 |
| Finished | Sep 09 12:43:02 PM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698602616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3698602616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.2063488006 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 164371371 ps |
| CPU time | 13.32 seconds |
| Started | Sep 09 12:41:19 PM UTC 24 |
| Finished | Sep 09 12:41:34 PM UTC 24 |
| Peak memory | 263328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063488006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2063488006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.3726603300 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 28611764509 ps |
| CPU time | 1449.71 seconds |
| Started | Sep 09 12:42:18 PM UTC 24 |
| Finished | Sep 09 01:06:44 PM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726603300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3726603300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.2114780870 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 8873112643 ps |
| CPU time | 353.49 seconds |
| Started | Sep 09 12:41:41 PM UTC 24 |
| Finished | Sep 09 12:47:39 PM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114780870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2114780870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.3898776752 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 25415433 ps |
| CPU time | 5.03 seconds |
| Started | Sep 09 12:41:12 PM UTC 24 |
| Finished | Sep 09 12:41:18 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898776752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3898776752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.2902584256 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2034863944 ps |
| CPU time | 38.4 seconds |
| Started | Sep 09 12:41:17 PM UTC 24 |
| Finished | Sep 09 12:41:57 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902584256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2902584256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.1952884995 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1824212130 ps |
| CPU time | 45.37 seconds |
| Started | Sep 09 12:41:30 PM UTC 24 |
| Finished | Sep 09 12:42:16 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952884995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1952884995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.3204971138 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 448981005 ps |
| CPU time | 36.72 seconds |
| Started | Sep 09 12:40:51 PM UTC 24 |
| Finished | Sep 09 12:41:29 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204971138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3204971138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all_with_rand_reset.700257392 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1054756579 ps |
| CPU time | 196.84 seconds |
| Started | Sep 09 12:43:02 PM UTC 24 |
| Finished | Sep 09 12:46:22 PM UTC 24 |
| Peak memory | 279420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=700257392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.al ert_handler_stress_all_with_rand_reset.700257392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.1428216032 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 58407556797 ps |
| CPU time | 1963.19 seconds |
| Started | Sep 09 12:44:31 PM UTC 24 |
| Finished | Sep 09 01:17:36 PM UTC 24 |
| Peak memory | 288548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428216032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1428216032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.862862516 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 3711824807 ps |
| CPU time | 73.99 seconds |
| Started | Sep 09 12:44:10 PM UTC 24 |
| Finished | Sep 09 12:45:25 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862862516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.862862516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.1640532565 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1023528065 ps |
| CPU time | 45.12 seconds |
| Started | Sep 09 12:44:10 PM UTC 24 |
| Finished | Sep 09 12:44:56 PM UTC 24 |
| Peak memory | 269088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640532565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1640532565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.2497692920 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 75080441614 ps |
| CPU time | 1834.33 seconds |
| Started | Sep 09 12:44:42 PM UTC 24 |
| Finished | Sep 09 01:15:38 PM UTC 24 |
| Peak memory | 304680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497692920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2497692920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.3480393605 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 16511340126 ps |
| CPU time | 135.2 seconds |
| Started | Sep 09 12:44:37 PM UTC 24 |
| Finished | Sep 09 12:46:54 PM UTC 24 |
| Peak memory | 269512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480393605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3480393605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.2866651059 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 3542749333 ps |
| CPU time | 67.67 seconds |
| Started | Sep 09 12:43:09 PM UTC 24 |
| Finished | Sep 09 12:44:19 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866651059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2866651059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.3907191005 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1021287870 ps |
| CPU time | 64.68 seconds |
| Started | Sep 09 12:43:29 PM UTC 24 |
| Finished | Sep 09 12:44:36 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907191005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3907191005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.1884439992 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 77181954 ps |
| CPU time | 9.68 seconds |
| Started | Sep 09 12:44:20 PM UTC 24 |
| Finished | Sep 09 12:44:30 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884439992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1884439992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.858256604 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 64662897 ps |
| CPU time | 4.18 seconds |
| Started | Sep 09 12:43:03 PM UTC 24 |
| Finished | Sep 09 12:43:08 PM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858256604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.858256604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.3835202139 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 74250543382 ps |
| CPU time | 1587.6 seconds |
| Started | Sep 09 12:44:57 PM UTC 24 |
| Finished | Sep 09 01:11:43 PM UTC 24 |
| Peak memory | 301876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835202139 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.3835202139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/26.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.2981900098 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 42789463622 ps |
| CPU time | 2217.26 seconds |
| Started | Sep 09 12:47:00 PM UTC 24 |
| Finished | Sep 09 01:24:21 PM UTC 24 |
| Peak memory | 304932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981900098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2981900098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.3557172545 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1532413003 ps |
| CPU time | 28.45 seconds |
| Started | Sep 09 12:46:46 PM UTC 24 |
| Finished | Sep 09 12:47:15 PM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557172545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3557172545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.3381577033 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 337510735 ps |
| CPU time | 32.03 seconds |
| Started | Sep 09 12:46:43 PM UTC 24 |
| Finished | Sep 09 12:47:17 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381577033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3381577033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.3650307997 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 85779231773 ps |
| CPU time | 2185.33 seconds |
| Started | Sep 09 12:47:16 PM UTC 24 |
| Finished | Sep 09 01:24:04 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650307997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3650307997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.3316598283 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 145836352246 ps |
| CPU time | 2588.95 seconds |
| Started | Sep 09 12:47:18 PM UTC 24 |
| Finished | Sep 09 01:30:56 PM UTC 24 |
| Peak memory | 304940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316598283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3316598283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.3770307034 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 25342350159 ps |
| CPU time | 182.1 seconds |
| Started | Sep 09 12:47:11 PM UTC 24 |
| Finished | Sep 09 12:50:16 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770307034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3770307034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.712303454 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 737822061 ps |
| CPU time | 66.13 seconds |
| Started | Sep 09 12:45:52 PM UTC 24 |
| Finished | Sep 09 12:47:00 PM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712303454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.712303454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.1246262816 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 727234823 ps |
| CPU time | 46.04 seconds |
| Started | Sep 09 12:46:23 PM UTC 24 |
| Finished | Sep 09 12:47:11 PM UTC 24 |
| Peak memory | 262936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246262816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1246262816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.2838281726 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 940404826 ps |
| CPU time | 28.36 seconds |
| Started | Sep 09 12:46:56 PM UTC 24 |
| Finished | Sep 09 12:47:26 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838281726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2838281726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.1696921440 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 117217112 ps |
| CPU time | 13.52 seconds |
| Started | Sep 09 12:45:36 PM UTC 24 |
| Finished | Sep 09 12:45:51 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696921440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1696921440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.2574549651 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 6675401337 ps |
| CPU time | 312.47 seconds |
| Started | Sep 09 12:47:26 PM UTC 24 |
| Finished | Sep 09 12:52:43 PM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574549651 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.2574549651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/27.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.1848153248 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 8885302964 ps |
| CPU time | 791.69 seconds |
| Started | Sep 09 12:49:15 PM UTC 24 |
| Finished | Sep 09 01:02:36 PM UTC 24 |
| Peak memory | 285492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848153248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1848153248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.3556013162 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 476427555 ps |
| CPU time | 15.04 seconds |
| Started | Sep 09 12:48:58 PM UTC 24 |
| Finished | Sep 09 12:49:14 PM UTC 24 |
| Peak memory | 266996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556013162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3556013162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.2299639193 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 113519302 ps |
| CPU time | 7.12 seconds |
| Started | Sep 09 12:48:48 PM UTC 24 |
| Finished | Sep 09 12:48:57 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299639193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2299639193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.1900462861 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 77839721032 ps |
| CPU time | 1784.95 seconds |
| Started | Sep 09 12:49:57 PM UTC 24 |
| Finished | Sep 09 01:20:02 PM UTC 24 |
| Peak memory | 298792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900462861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1900462861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.3499676275 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 127879828000 ps |
| CPU time | 2151.61 seconds |
| Started | Sep 09 12:50:19 PM UTC 24 |
| Finished | Sep 09 01:26:34 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499676275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3499676275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.4061482732 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 11053879913 ps |
| CPU time | 193.27 seconds |
| Started | Sep 09 12:49:22 PM UTC 24 |
| Finished | Sep 09 12:52:39 PM UTC 24 |
| Peak memory | 267400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061482732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4061482732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.3956142790 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 215687180 ps |
| CPU time | 12.54 seconds |
| Started | Sep 09 12:48:29 PM UTC 24 |
| Finished | Sep 09 12:48:44 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956142790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3956142790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.704927914 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 883843375 ps |
| CPU time | 91.41 seconds |
| Started | Sep 09 12:48:44 PM UTC 24 |
| Finished | Sep 09 12:50:18 PM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704927914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.704927914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.1979845000 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 5924919271 ps |
| CPU time | 56.33 seconds |
| Started | Sep 09 12:48:59 PM UTC 24 |
| Finished | Sep 09 12:49:57 PM UTC 24 |
| Peak memory | 269436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979845000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1979845000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.190510357 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 786869533 ps |
| CPU time | 57.63 seconds |
| Started | Sep 09 12:47:58 PM UTC 24 |
| Finished | Sep 09 12:48:57 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190510357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.190510357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.296183007 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 32025652728 ps |
| CPU time | 1511.87 seconds |
| Started | Sep 09 12:50:19 PM UTC 24 |
| Finished | Sep 09 01:15:47 PM UTC 24 |
| Peak memory | 301876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296183007 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.296183007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/28.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.2712524329 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 143376336244 ps |
| CPU time | 2471.69 seconds |
| Started | Sep 09 12:51:44 PM UTC 24 |
| Finished | Sep 09 01:33:20 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712524329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2712524329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.2971955679 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 11431940033 ps |
| CPU time | 277.13 seconds |
| Started | Sep 09 12:51:22 PM UTC 24 |
| Finished | Sep 09 12:56:03 PM UTC 24 |
| Peak memory | 265340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971955679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2971955679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.605641757 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 7614994510 ps |
| CPU time | 107.22 seconds |
| Started | Sep 09 12:51:12 PM UTC 24 |
| Finished | Sep 09 12:53:01 PM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605641757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.605641757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.1189744522 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 138960216874 ps |
| CPU time | 2063.42 seconds |
| Started | Sep 09 12:51:57 PM UTC 24 |
| Finished | Sep 09 01:26:44 PM UTC 24 |
| Peak memory | 298464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189744522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1189744522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.1590761896 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 70552477747 ps |
| CPU time | 1648.27 seconds |
| Started | Sep 09 12:52:11 PM UTC 24 |
| Finished | Sep 09 01:19:57 PM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590761896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1590761896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.3483419133 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 8876000803 ps |
| CPU time | 447.74 seconds |
| Started | Sep 09 12:51:55 PM UTC 24 |
| Finished | Sep 09 12:59:29 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483419133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3483419133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.392804503 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 5745816201 ps |
| CPU time | 59.97 seconds |
| Started | Sep 09 12:50:52 PM UTC 24 |
| Finished | Sep 09 12:51:54 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392804503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.392804503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.3586099710 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 5596922886 ps |
| CPU time | 50.47 seconds |
| Started | Sep 09 12:51:04 PM UTC 24 |
| Finished | Sep 09 12:51:56 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586099710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3586099710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.2055761355 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1024371312 ps |
| CPU time | 81.05 seconds |
| Started | Sep 09 12:51:22 PM UTC 24 |
| Finished | Sep 09 12:52:45 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055761355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2055761355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.4222251784 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2579777034 ps |
| CPU time | 55 seconds |
| Started | Sep 09 12:50:47 PM UTC 24 |
| Finished | Sep 09 12:51:44 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222251784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.4222251784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.4131908717 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 34113371183 ps |
| CPU time | 1051.86 seconds |
| Started | Sep 09 12:52:40 PM UTC 24 |
| Finished | Sep 09 01:10:23 PM UTC 24 |
| Peak memory | 297852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131908717 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.4131908717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all_with_rand_reset.1684945109 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 36651233155 ps |
| CPU time | 394.37 seconds |
| Started | Sep 09 12:52:44 PM UTC 24 |
| Finished | Sep 09 12:59:24 PM UTC 24 |
| Peak memory | 281596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1684945109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.a lert_handler_stress_all_with_rand_reset.1684945109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.1868357731 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 46133512 ps |
| CPU time | 6.32 seconds |
| Started | Sep 09 11:47:10 AM UTC 24 |
| Finished | Sep 09 11:47:18 AM UTC 24 |
| Peak memory | 269392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868357731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1868357731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.2776165790 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 21436911825 ps |
| CPU time | 1489.59 seconds |
| Started | Sep 09 11:46:51 AM UTC 24 |
| Finished | Sep 09 12:12:10 PM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776165790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2776165790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.2537983821 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 900157744 ps |
| CPU time | 13.31 seconds |
| Started | Sep 09 11:47:08 AM UTC 24 |
| Finished | Sep 09 11:47:23 AM UTC 24 |
| Peak memory | 263236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537983821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2537983821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.511358512 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2028928588 ps |
| CPU time | 37.29 seconds |
| Started | Sep 09 11:46:49 AM UTC 24 |
| Finished | Sep 09 11:47:28 AM UTC 24 |
| Peak memory | 268828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511358512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.511358512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.2503223089 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 606231728 ps |
| CPU time | 19.42 seconds |
| Started | Sep 09 11:46:49 AM UTC 24 |
| Finished | Sep 09 11:47:10 AM UTC 24 |
| Peak memory | 266720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503223089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2503223089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.1167821931 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 24035255316 ps |
| CPU time | 1102.39 seconds |
| Started | Sep 09 11:47:08 AM UTC 24 |
| Finished | Sep 09 12:05:43 PM UTC 24 |
| Peak memory | 295740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167821931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1167821931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.1974108973 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 799254248 ps |
| CPU time | 75.5 seconds |
| Started | Sep 09 11:46:47 AM UTC 24 |
| Finished | Sep 09 11:48:05 AM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974108973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1974108973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.3863877935 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1080514298 ps |
| CPU time | 81.18 seconds |
| Started | Sep 09 11:46:48 AM UTC 24 |
| Finished | Sep 09 11:48:12 AM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863877935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3863877935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.2319395107 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1127684601 ps |
| CPU time | 61.78 seconds |
| Started | Sep 09 11:47:15 AM UTC 24 |
| Finished | Sep 09 11:48:18 AM UTC 24 |
| Peak memory | 297388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319395107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2319395107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.2913702704 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 286041568 ps |
| CPU time | 39.03 seconds |
| Started | Sep 09 11:46:46 AM UTC 24 |
| Finished | Sep 09 11:47:26 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913702704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2913702704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all_with_rand_reset.3220655299 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 826869600 ps |
| CPU time | 47.98 seconds |
| Started | Sep 09 11:47:11 AM UTC 24 |
| Finished | Sep 09 11:48:01 AM UTC 24 |
| Peak memory | 279412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3220655299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.al ert_handler_stress_all_with_rand_reset.3220655299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.1643159996 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 133452108898 ps |
| CPU time | 2095.74 seconds |
| Started | Sep 09 12:53:22 PM UTC 24 |
| Finished | Sep 09 01:28:40 PM UTC 24 |
| Peak memory | 288216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643159996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1643159996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.4131538061 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 685586079 ps |
| CPU time | 81.84 seconds |
| Started | Sep 09 12:53:10 PM UTC 24 |
| Finished | Sep 09 12:54:34 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131538061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.4131538061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.937914163 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 20203103 ps |
| CPU time | 4.97 seconds |
| Started | Sep 09 12:53:03 PM UTC 24 |
| Finished | Sep 09 12:53:09 PM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937914163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.937914163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.2741950101 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 6450667902 ps |
| CPU time | 775.55 seconds |
| Started | Sep 09 12:53:44 PM UTC 24 |
| Finished | Sep 09 01:06:49 PM UTC 24 |
| Peak memory | 285828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741950101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2741950101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.1787284126 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 28997891932 ps |
| CPU time | 1676.62 seconds |
| Started | Sep 09 12:54:11 PM UTC 24 |
| Finished | Sep 09 01:22:27 PM UTC 24 |
| Peak memory | 279688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787284126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1787284126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.2520297118 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 9709037381 ps |
| CPU time | 642.38 seconds |
| Started | Sep 09 12:53:36 PM UTC 24 |
| Finished | Sep 09 01:04:27 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520297118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2520297118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.2880290574 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 773133956 ps |
| CPU time | 46.6 seconds |
| Started | Sep 09 12:52:46 PM UTC 24 |
| Finished | Sep 09 12:53:35 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880290574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2880290574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.3700583614 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 133666906 ps |
| CPU time | 15.01 seconds |
| Started | Sep 09 12:53:02 PM UTC 24 |
| Finished | Sep 09 12:53:18 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700583614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3700583614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.4213397482 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2100807090 ps |
| CPU time | 47.56 seconds |
| Started | Sep 09 12:53:22 PM UTC 24 |
| Finished | Sep 09 12:54:11 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213397482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.4213397482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.3958578707 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 405743146 ps |
| CPU time | 14.54 seconds |
| Started | Sep 09 12:52:45 PM UTC 24 |
| Finished | Sep 09 12:53:01 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958578707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3958578707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.524093237 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 42725148031 ps |
| CPU time | 2445.37 seconds |
| Started | Sep 09 12:54:34 PM UTC 24 |
| Finished | Sep 09 01:35:46 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524093237 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.524093237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.4242358797 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1734178908 ps |
| CPU time | 100.19 seconds |
| Started | Sep 09 12:55:56 PM UTC 24 |
| Finished | Sep 09 12:57:38 PM UTC 24 |
| Peak memory | 285884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4242358797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.a lert_handler_stress_all_with_rand_reset.4242358797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.2806475187 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 49201938901 ps |
| CPU time | 3412.42 seconds |
| Started | Sep 09 12:57:33 PM UTC 24 |
| Finished | Sep 09 01:55:05 PM UTC 24 |
| Peak memory | 304676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806475187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2806475187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.1640918951 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2998203096 ps |
| CPU time | 40.43 seconds |
| Started | Sep 09 12:56:49 PM UTC 24 |
| Finished | Sep 09 12:57:31 PM UTC 24 |
| Peak memory | 269432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640918951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1640918951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.2641375771 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 104095547 ps |
| CPU time | 7.48 seconds |
| Started | Sep 09 12:56:40 PM UTC 24 |
| Finished | Sep 09 12:56:49 PM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641375771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2641375771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.3798276053 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 40713791876 ps |
| CPU time | 1280.58 seconds |
| Started | Sep 09 12:57:34 PM UTC 24 |
| Finished | Sep 09 01:19:10 PM UTC 24 |
| Peak memory | 296068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798276053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3798276053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.1182873159 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 127443025867 ps |
| CPU time | 975.7 seconds |
| Started | Sep 09 12:57:39 PM UTC 24 |
| Finished | Sep 09 01:14:06 PM UTC 24 |
| Peak memory | 285832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182873159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1182873159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.1964326239 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3642249288 ps |
| CPU time | 87.04 seconds |
| Started | Sep 09 12:56:04 PM UTC 24 |
| Finished | Sep 09 12:57:33 PM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964326239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1964326239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.3251401625 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 904977199 ps |
| CPU time | 40.27 seconds |
| Started | Sep 09 12:56:12 PM UTC 24 |
| Finished | Sep 09 12:56:54 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251401625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3251401625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.286299374 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 229287606 ps |
| CPU time | 36.56 seconds |
| Started | Sep 09 12:56:54 PM UTC 24 |
| Finished | Sep 09 12:57:32 PM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286299374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.286299374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.2753516791 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 314357146 ps |
| CPU time | 9.18 seconds |
| Started | Sep 09 12:56:00 PM UTC 24 |
| Finished | Sep 09 12:56:11 PM UTC 24 |
| Peak memory | 267000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753516791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2753516791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all_with_rand_reset.3580812814 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 10430599500 ps |
| CPU time | 600.47 seconds |
| Started | Sep 09 12:59:12 PM UTC 24 |
| Finished | Sep 09 01:09:20 PM UTC 24 |
| Peak memory | 297980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3580812814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.a lert_handler_stress_all_with_rand_reset.3580812814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.2579270091 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 7778026268 ps |
| CPU time | 609.48 seconds |
| Started | Sep 09 01:00:34 PM UTC 24 |
| Finished | Sep 09 01:10:52 PM UTC 24 |
| Peak memory | 285888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579270091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2579270091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.3733235935 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 12578493966 ps |
| CPU time | 55.65 seconds |
| Started | Sep 09 12:59:55 PM UTC 24 |
| Finished | Sep 09 01:00:52 PM UTC 24 |
| Peak memory | 269100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733235935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3733235935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.3206984743 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 964645483 ps |
| CPU time | 43.15 seconds |
| Started | Sep 09 12:59:40 PM UTC 24 |
| Finished | Sep 09 01:00:25 PM UTC 24 |
| Peak memory | 263264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206984743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3206984743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.3681525814 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 43383061137 ps |
| CPU time | 2301.54 seconds |
| Started | Sep 09 01:00:51 PM UTC 24 |
| Finished | Sep 09 01:39:36 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681525814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3681525814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.988648769 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 35414522560 ps |
| CPU time | 2166.09 seconds |
| Started | Sep 09 01:00:53 PM UTC 24 |
| Finished | Sep 09 01:37:23 PM UTC 24 |
| Peak memory | 305004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988648769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.988648769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.1741626812 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 79511461 ps |
| CPU time | 9.14 seconds |
| Started | Sep 09 12:59:29 PM UTC 24 |
| Finished | Sep 09 12:59:39 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741626812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1741626812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.1546741812 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 249653588 ps |
| CPU time | 17.49 seconds |
| Started | Sep 09 12:59:35 PM UTC 24 |
| Finished | Sep 09 12:59:54 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546741812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1546741812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.3643337103 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 643562232 ps |
| CPU time | 8.24 seconds |
| Started | Sep 09 12:59:25 PM UTC 24 |
| Finished | Sep 09 12:59:34 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643337103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3643337103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.3751736108 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1752733466 ps |
| CPU time | 237.96 seconds |
| Started | Sep 09 01:01:54 PM UTC 24 |
| Finished | Sep 09 01:05:55 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751736108 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.3751736108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all_with_rand_reset.2506056379 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1964283088 ps |
| CPU time | 183.48 seconds |
| Started | Sep 09 01:02:13 PM UTC 24 |
| Finished | Sep 09 01:05:20 PM UTC 24 |
| Peak memory | 283512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2506056379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.a lert_handler_stress_all_with_rand_reset.2506056379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.3291389236 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 89905393224 ps |
| CPU time | 2004 seconds |
| Started | Sep 09 01:05:15 PM UTC 24 |
| Finished | Sep 09 01:39:00 PM UTC 24 |
| Peak memory | 298464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291389236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3291389236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.2093658497 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 55341285 ps |
| CPU time | 11.33 seconds |
| Started | Sep 09 01:05:09 PM UTC 24 |
| Finished | Sep 09 01:05:21 PM UTC 24 |
| Peak memory | 269368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093658497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2093658497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.3619153963 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 851785752 ps |
| CPU time | 43.97 seconds |
| Started | Sep 09 01:04:27 PM UTC 24 |
| Finished | Sep 09 01:05:13 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619153963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3619153963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.41034120 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 32655362590 ps |
| CPU time | 2132.39 seconds |
| Started | Sep 09 01:05:31 PM UTC 24 |
| Finished | Sep 09 01:41:26 PM UTC 24 |
| Peak memory | 304808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41034120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.41034120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.3437685031 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 15053166309 ps |
| CPU time | 476.07 seconds |
| Started | Sep 09 01:05:21 PM UTC 24 |
| Finished | Sep 09 01:13:23 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437685031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3437685031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.2126802600 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3690294344 ps |
| CPU time | 68.45 seconds |
| Started | Sep 09 01:02:58 PM UTC 24 |
| Finished | Sep 09 01:04:08 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126802600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2126802600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.515052297 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1049064774 ps |
| CPU time | 56.41 seconds |
| Started | Sep 09 01:04:09 PM UTC 24 |
| Finished | Sep 09 01:05:07 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515052297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.515052297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.988794048 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 631392781 ps |
| CPU time | 18.01 seconds |
| Started | Sep 09 01:02:37 PM UTC 24 |
| Finished | Sep 09 01:02:57 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988794048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.988794048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.825371778 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 101264194550 ps |
| CPU time | 1056.69 seconds |
| Started | Sep 09 01:05:45 PM UTC 24 |
| Finished | Sep 09 01:23:34 PM UTC 24 |
| Peak memory | 299900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825371778 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.825371778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all_with_rand_reset.1107598094 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2439389437 ps |
| CPU time | 395.69 seconds |
| Started | Sep 09 01:05:56 PM UTC 24 |
| Finished | Sep 09 01:12:37 PM UTC 24 |
| Peak memory | 279476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1107598094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.a lert_handler_stress_all_with_rand_reset.1107598094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.3579905462 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 376135415461 ps |
| CPU time | 2490.68 seconds |
| Started | Sep 09 01:07:07 PM UTC 24 |
| Finished | Sep 09 01:49:05 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579905462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3579905462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.1339083313 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2868717511 ps |
| CPU time | 116.1 seconds |
| Started | Sep 09 01:06:51 PM UTC 24 |
| Finished | Sep 09 01:08:49 PM UTC 24 |
| Peak memory | 269432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339083313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1339083313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.394125084 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1235335200 ps |
| CPU time | 24.6 seconds |
| Started | Sep 09 01:06:46 PM UTC 24 |
| Finished | Sep 09 01:07:12 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394125084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.394125084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.1173150741 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 126831668561 ps |
| CPU time | 2212.61 seconds |
| Started | Sep 09 01:07:28 PM UTC 24 |
| Finished | Sep 09 01:44:44 PM UTC 24 |
| Peak memory | 304680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173150741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1173150741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.607756897 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 170821129229 ps |
| CPU time | 2916.43 seconds |
| Started | Sep 09 01:07:33 PM UTC 24 |
| Finished | Sep 09 01:56:42 PM UTC 24 |
| Peak memory | 305004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607756897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.607756897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.2841133592 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 14089146332 ps |
| CPU time | 634.41 seconds |
| Started | Sep 09 01:07:14 PM UTC 24 |
| Finished | Sep 09 01:17:56 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841133592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2841133592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.725997900 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 752101282 ps |
| CPU time | 46.47 seconds |
| Started | Sep 09 01:06:39 PM UTC 24 |
| Finished | Sep 09 01:07:27 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725997900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.725997900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.979554616 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 223538161 ps |
| CPU time | 22.95 seconds |
| Started | Sep 09 01:06:42 PM UTC 24 |
| Finished | Sep 09 01:07:06 PM UTC 24 |
| Peak memory | 269244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979554616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.979554616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.1727486886 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 166761185 ps |
| CPU time | 27.5 seconds |
| Started | Sep 09 01:07:03 PM UTC 24 |
| Finished | Sep 09 01:07:32 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727486886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1727486886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.1793495597 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 1381363803 ps |
| CPU time | 47.36 seconds |
| Started | Sep 09 01:06:13 PM UTC 24 |
| Finished | Sep 09 01:07:02 PM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793495597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1793495597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.2226992092 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 662385922 ps |
| CPU time | 38.45 seconds |
| Started | Sep 09 01:07:47 PM UTC 24 |
| Finished | Sep 09 01:08:27 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226992092 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.2226992092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/34.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.3079307366 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 75443835813 ps |
| CPU time | 1407.63 seconds |
| Started | Sep 09 01:09:56 PM UTC 24 |
| Finished | Sep 09 01:33:39 PM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079307366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3079307366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.263079681 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 13983527680 ps |
| CPU time | 219.36 seconds |
| Started | Sep 09 01:09:34 PM UTC 24 |
| Finished | Sep 09 01:13:17 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263079681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.263079681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.3008798351 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 395510647 ps |
| CPU time | 29.91 seconds |
| Started | Sep 09 01:09:24 PM UTC 24 |
| Finished | Sep 09 01:09:55 PM UTC 24 |
| Peak memory | 263136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008798351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3008798351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.3248753528 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 23271012119 ps |
| CPU time | 1070.49 seconds |
| Started | Sep 09 01:10:19 PM UTC 24 |
| Finished | Sep 09 01:28:23 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248753528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3248753528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.3674995082 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 42417804352 ps |
| CPU time | 2348.03 seconds |
| Started | Sep 09 01:10:25 PM UTC 24 |
| Finished | Sep 09 01:49:59 PM UTC 24 |
| Peak memory | 304748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674995082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3674995082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.370092171 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 858669583 ps |
| CPU time | 30.45 seconds |
| Started | Sep 09 01:08:51 PM UTC 24 |
| Finished | Sep 09 01:09:23 PM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370092171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.370092171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.2680203795 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 5104976363 ps |
| CPU time | 33.72 seconds |
| Started | Sep 09 01:09:22 PM UTC 24 |
| Finished | Sep 09 01:09:57 PM UTC 24 |
| Peak memory | 263068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680203795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2680203795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.2421147627 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 363524955 ps |
| CPU time | 35.67 seconds |
| Started | Sep 09 01:09:42 PM UTC 24 |
| Finished | Sep 09 01:10:19 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421147627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2421147627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.416990440 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 3504862857 ps |
| CPU time | 72.04 seconds |
| Started | Sep 09 01:08:28 PM UTC 24 |
| Finished | Sep 09 01:09:41 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416990440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.416990440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all_with_rand_reset.1155342741 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 6738435502 ps |
| CPU time | 195.89 seconds |
| Started | Sep 09 01:11:45 PM UTC 24 |
| Finished | Sep 09 01:15:04 PM UTC 24 |
| Peak memory | 279476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1155342741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.a lert_handler_stress_all_with_rand_reset.1155342741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.4051466990 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 51197026905 ps |
| CPU time | 1674.54 seconds |
| Started | Sep 09 01:12:53 PM UTC 24 |
| Finished | Sep 09 01:41:07 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051466990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.4051466990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.3468551250 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 584957505 ps |
| CPU time | 25.46 seconds |
| Started | Sep 09 01:12:38 PM UTC 24 |
| Finished | Sep 09 01:13:06 PM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468551250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3468551250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.1485899198 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 355350915 ps |
| CPU time | 52.77 seconds |
| Started | Sep 09 01:12:35 PM UTC 24 |
| Finished | Sep 09 01:13:30 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485899198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1485899198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.3738448276 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 22277607668 ps |
| CPU time | 1076.66 seconds |
| Started | Sep 09 01:13:07 PM UTC 24 |
| Finished | Sep 09 01:31:16 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738448276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3738448276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.2622595247 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 36751181620 ps |
| CPU time | 2079.31 seconds |
| Started | Sep 09 01:13:09 PM UTC 24 |
| Finished | Sep 09 01:48:10 PM UTC 24 |
| Peak memory | 300512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622595247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2622595247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.1373198219 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 25929633788 ps |
| CPU time | 318.92 seconds |
| Started | Sep 09 01:13:02 PM UTC 24 |
| Finished | Sep 09 01:18:26 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373198219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1373198219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.3029586305 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 355853418 ps |
| CPU time | 6.24 seconds |
| Started | Sep 09 01:12:27 PM UTC 24 |
| Finished | Sep 09 01:12:34 PM UTC 24 |
| Peak memory | 252988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029586305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3029586305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.2649858953 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1326259778 ps |
| CPU time | 51.38 seconds |
| Started | Sep 09 01:12:35 PM UTC 24 |
| Finished | Sep 09 01:13:28 PM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649858953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2649858953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.1038601330 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1165737809 ps |
| CPU time | 22.29 seconds |
| Started | Sep 09 01:12:45 PM UTC 24 |
| Finished | Sep 09 01:13:08 PM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038601330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1038601330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.2827601637 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 268104137 ps |
| CPU time | 17.88 seconds |
| Started | Sep 09 01:12:07 PM UTC 24 |
| Finished | Sep 09 01:12:26 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827601637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2827601637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/36.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.3095555909 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 41323330014 ps |
| CPU time | 2439.03 seconds |
| Started | Sep 09 01:14:08 PM UTC 24 |
| Finished | Sep 09 01:55:17 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095555909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3095555909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.1678829086 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 545952862 ps |
| CPU time | 46.63 seconds |
| Started | Sep 09 01:14:04 PM UTC 24 |
| Finished | Sep 09 01:14:52 PM UTC 24 |
| Peak memory | 269240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678829086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1678829086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.892600517 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 649469677 ps |
| CPU time | 26.33 seconds |
| Started | Sep 09 01:14:03 PM UTC 24 |
| Finished | Sep 09 01:14:30 PM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892600517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.892600517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.75824277 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 57966058789 ps |
| CPU time | 1393.84 seconds |
| Started | Sep 09 01:14:51 PM UTC 24 |
| Finished | Sep 09 01:38:20 PM UTC 24 |
| Peak memory | 297856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75824277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.75824277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.2638076147 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 62328913029 ps |
| CPU time | 2299.58 seconds |
| Started | Sep 09 01:14:53 PM UTC 24 |
| Finished | Sep 09 01:53:39 PM UTC 24 |
| Peak memory | 298464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638076147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2638076147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.1633011205 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 8644567208 ps |
| CPU time | 285.62 seconds |
| Started | Sep 09 01:14:32 PM UTC 24 |
| Finished | Sep 09 01:19:21 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633011205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1633011205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.1371926870 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 223402824 ps |
| CPU time | 30.28 seconds |
| Started | Sep 09 01:13:30 PM UTC 24 |
| Finished | Sep 09 01:14:02 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371926870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1371926870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.1642407878 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 640295462 ps |
| CPU time | 26.44 seconds |
| Started | Sep 09 01:13:39 PM UTC 24 |
| Finished | Sep 09 01:14:06 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642407878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1642407878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.763535569 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1180648343 ps |
| CPU time | 40.33 seconds |
| Started | Sep 09 01:14:08 PM UTC 24 |
| Finished | Sep 09 01:14:50 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763535569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.763535569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.2119357856 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1625964407 ps |
| CPU time | 31.91 seconds |
| Started | Sep 09 01:13:29 PM UTC 24 |
| Finished | Sep 09 01:14:03 PM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119357856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2119357856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.2480123605 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 76723350696 ps |
| CPU time | 2372.09 seconds |
| Started | Sep 09 01:15:05 PM UTC 24 |
| Finished | Sep 09 01:55:03 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480123605 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.2480123605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/37.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.3482243060 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 22818935272 ps |
| CPU time | 1234.43 seconds |
| Started | Sep 09 01:17:38 PM UTC 24 |
| Finished | Sep 09 01:38:25 PM UTC 24 |
| Peak memory | 285824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482243060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3482243060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.3833023736 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1216850263 ps |
| CPU time | 27.81 seconds |
| Started | Sep 09 01:17:25 PM UTC 24 |
| Finished | Sep 09 01:17:55 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833023736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3833023736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.4018782870 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1322168037 ps |
| CPU time | 30.62 seconds |
| Started | Sep 09 01:16:59 PM UTC 24 |
| Finished | Sep 09 01:17:31 PM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018782870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.4018782870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.1175004043 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 138588133098 ps |
| CPU time | 2056.08 seconds |
| Started | Sep 09 01:17:57 PM UTC 24 |
| Finished | Sep 09 01:52:35 PM UTC 24 |
| Peak memory | 304620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175004043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1175004043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.1653453015 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 45635549782 ps |
| CPU time | 551.6 seconds |
| Started | Sep 09 01:17:52 PM UTC 24 |
| Finished | Sep 09 01:27:11 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653453015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1653453015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.2335217780 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 439214548 ps |
| CPU time | 54.04 seconds |
| Started | Sep 09 01:16:03 PM UTC 24 |
| Finished | Sep 09 01:16:59 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335217780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2335217780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.1566645976 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 751900638 ps |
| CPU time | 65.55 seconds |
| Started | Sep 09 01:16:17 PM UTC 24 |
| Finished | Sep 09 01:17:24 PM UTC 24 |
| Peak memory | 262912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566645976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1566645976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.3896777462 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 359371756 ps |
| CPU time | 11.39 seconds |
| Started | Sep 09 01:15:48 PM UTC 24 |
| Finished | Sep 09 01:16:02 PM UTC 24 |
| Peak memory | 267000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896777462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3896777462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.3169388428 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 82002092890 ps |
| CPU time | 2238.64 seconds |
| Started | Sep 09 01:18:17 PM UTC 24 |
| Finished | Sep 09 01:55:59 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169388428 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.3169388428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/38.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.2895598169 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 21102965246 ps |
| CPU time | 1598.61 seconds |
| Started | Sep 09 01:20:08 PM UTC 24 |
| Finished | Sep 09 01:47:06 PM UTC 24 |
| Peak memory | 285492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895598169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2895598169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.2672704362 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 5635461714 ps |
| CPU time | 169.68 seconds |
| Started | Sep 09 01:19:59 PM UTC 24 |
| Finished | Sep 09 01:22:51 PM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672704362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2672704362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.3152441394 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 108595275 ps |
| CPU time | 13.62 seconds |
| Started | Sep 09 01:19:53 PM UTC 24 |
| Finished | Sep 09 01:20:08 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152441394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3152441394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.2694782050 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 51466846249 ps |
| CPU time | 1336.36 seconds |
| Started | Sep 09 01:20:45 PM UTC 24 |
| Finished | Sep 09 01:43:18 PM UTC 24 |
| Peak memory | 300164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694782050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2694782050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.2681146126 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 33747047425 ps |
| CPU time | 1079.01 seconds |
| Started | Sep 09 01:21:01 PM UTC 24 |
| Finished | Sep 09 01:39:14 PM UTC 24 |
| Peak memory | 296072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681146126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2681146126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.1254063699 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 6521185726 ps |
| CPU time | 305.2 seconds |
| Started | Sep 09 01:20:36 PM UTC 24 |
| Finished | Sep 09 01:25:45 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254063699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1254063699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.3938232825 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3684835638 ps |
| CPU time | 70.86 seconds |
| Started | Sep 09 01:19:22 PM UTC 24 |
| Finished | Sep 09 01:20:35 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938232825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3938232825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.301392836 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 197603988 ps |
| CPU time | 11.89 seconds |
| Started | Sep 09 01:19:39 PM UTC 24 |
| Finished | Sep 09 01:19:52 PM UTC 24 |
| Peak memory | 265276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301392836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.301392836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.138601602 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1924765708 ps |
| CPU time | 54.3 seconds |
| Started | Sep 09 01:20:04 PM UTC 24 |
| Finished | Sep 09 01:21:00 PM UTC 24 |
| Peak memory | 263200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138601602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.138601602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.1368530540 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1054107031 ps |
| CPU time | 25.22 seconds |
| Started | Sep 09 01:19:12 PM UTC 24 |
| Finished | Sep 09 01:19:38 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368530540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1368530540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/39.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.4234789420 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 112615681 ps |
| CPU time | 3.85 seconds |
| Started | Sep 09 11:48:02 AM UTC 24 |
| Finished | Sep 09 11:48:07 AM UTC 24 |
| Peak memory | 263500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234789420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.4234789420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.1912936319 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 419680670 ps |
| CPU time | 14.69 seconds |
| Started | Sep 09 11:47:53 AM UTC 24 |
| Finished | Sep 09 11:48:08 AM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912936319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1912936319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.309377090 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 10743383583 ps |
| CPU time | 448.09 seconds |
| Started | Sep 09 11:47:30 AM UTC 24 |
| Finished | Sep 09 11:55:04 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309377090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.309377090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.538719505 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3553158461 ps |
| CPU time | 28.14 seconds |
| Started | Sep 09 11:47:27 AM UTC 24 |
| Finished | Sep 09 11:47:57 AM UTC 24 |
| Peak memory | 269104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538719505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.538719505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.298778987 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 95549689978 ps |
| CPU time | 1884.77 seconds |
| Started | Sep 09 11:47:47 AM UTC 24 |
| Finished | Sep 09 12:19:33 PM UTC 24 |
| Peak memory | 287296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298778987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.298778987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.616417155 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2514877050 ps |
| CPU time | 99.43 seconds |
| Started | Sep 09 11:47:46 AM UTC 24 |
| Finished | Sep 09 11:49:28 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616417155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.616417155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.627394811 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5658554748 ps |
| CPU time | 61.12 seconds |
| Started | Sep 09 11:47:18 AM UTC 24 |
| Finished | Sep 09 11:48:21 AM UTC 24 |
| Peak memory | 269216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627394811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.627394811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.3578548600 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3270774533 ps |
| CPU time | 36.9 seconds |
| Started | Sep 09 11:47:23 AM UTC 24 |
| Finished | Sep 09 11:48:02 AM UTC 24 |
| Peak memory | 263324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578548600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3578548600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.639553560 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1244786090 ps |
| CPU time | 29.75 seconds |
| Started | Sep 09 11:48:06 AM UTC 24 |
| Finished | Sep 09 11:48:37 AM UTC 24 |
| Peak memory | 297316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639553560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_h andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.639553560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.946911300 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 122015877 ps |
| CPU time | 7.05 seconds |
| Started | Sep 09 11:47:34 AM UTC 24 |
| Finished | Sep 09 11:47:42 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946911300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.946911300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.1354294613 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1314677387 ps |
| CPU time | 27.36 seconds |
| Started | Sep 09 11:47:18 AM UTC 24 |
| Finished | Sep 09 11:47:47 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354294613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1354294613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all_with_rand_reset.1322924637 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3605405173 ps |
| CPU time | 69 seconds |
| Started | Sep 09 11:48:03 AM UTC 24 |
| Finished | Sep 09 11:49:14 AM UTC 24 |
| Peak memory | 279476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1322924637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.al ert_handler_stress_all_with_rand_reset.1322924637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.4283082020 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 78822105112 ps |
| CPU time | 1949.44 seconds |
| Started | Sep 09 01:24:07 PM UTC 24 |
| Finished | Sep 09 01:56:58 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283082020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.4283082020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.4229720092 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 15023398214 ps |
| CPU time | 216.05 seconds |
| Started | Sep 09 01:23:44 PM UTC 24 |
| Finished | Sep 09 01:27:24 PM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229720092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.4229720092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.960787754 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1925977531 ps |
| CPU time | 39.99 seconds |
| Started | Sep 09 01:23:36 PM UTC 24 |
| Finished | Sep 09 01:24:18 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960787754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.960787754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.995911949 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 67202704222 ps |
| CPU time | 756.67 seconds |
| Started | Sep 09 01:24:19 PM UTC 24 |
| Finished | Sep 09 01:37:04 PM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995911949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.995911949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.1128578553 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 31927195015 ps |
| CPU time | 1237.53 seconds |
| Started | Sep 09 01:24:24 PM UTC 24 |
| Finished | Sep 09 01:45:15 PM UTC 24 |
| Peak memory | 301960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128578553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1128578553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.2373665523 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 14549181636 ps |
| CPU time | 504.77 seconds |
| Started | Sep 09 01:24:07 PM UTC 24 |
| Finished | Sep 09 01:32:38 PM UTC 24 |
| Peak memory | 269512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373665523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2373665523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.3820017907 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3140222465 ps |
| CPU time | 72.12 seconds |
| Started | Sep 09 01:22:52 PM UTC 24 |
| Finished | Sep 09 01:24:06 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820017907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3820017907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.932707951 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 1939866319 ps |
| CPU time | 52.35 seconds |
| Started | Sep 09 01:23:00 PM UTC 24 |
| Finished | Sep 09 01:23:54 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932707951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.932707951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.2492463461 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 713232219 ps |
| CPU time | 57.95 seconds |
| Started | Sep 09 01:23:55 PM UTC 24 |
| Finished | Sep 09 01:24:54 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492463461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2492463461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.1606757907 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 842409997 ps |
| CPU time | 67.5 seconds |
| Started | Sep 09 01:22:35 PM UTC 24 |
| Finished | Sep 09 01:23:44 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606757907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1606757907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.774199970 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 41236329711 ps |
| CPU time | 2347.67 seconds |
| Started | Sep 09 01:24:55 PM UTC 24 |
| Finished | Sep 09 02:04:28 PM UTC 24 |
| Peak memory | 321056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774199970 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.774199970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all_with_rand_reset.1725976019 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1649387102 ps |
| CPU time | 65.36 seconds |
| Started | Sep 09 01:25:25 PM UTC 24 |
| Finished | Sep 09 01:26:33 PM UTC 24 |
| Peak memory | 281532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1725976019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.a lert_handler_stress_all_with_rand_reset.1725976019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.599031469 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 32583726957 ps |
| CPU time | 1982.01 seconds |
| Started | Sep 09 01:26:46 PM UTC 24 |
| Finished | Sep 09 02:00:11 PM UTC 24 |
| Peak memory | 288224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599031469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.599031469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.2707899631 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 20165560542 ps |
| CPU time | 233.7 seconds |
| Started | Sep 09 01:26:37 PM UTC 24 |
| Finished | Sep 09 01:30:34 PM UTC 24 |
| Peak memory | 269308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707899631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2707899631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.665485667 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 872862718 ps |
| CPU time | 73.44 seconds |
| Started | Sep 09 01:26:33 PM UTC 24 |
| Finished | Sep 09 01:27:49 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665485667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.665485667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.4259247483 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 13629969069 ps |
| CPU time | 756.94 seconds |
| Started | Sep 09 01:27:12 PM UTC 24 |
| Finished | Sep 09 01:39:58 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259247483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.4259247483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.3860148638 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 105357645319 ps |
| CPU time | 1084.5 seconds |
| Started | Sep 09 01:27:25 PM UTC 24 |
| Finished | Sep 09 01:45:42 PM UTC 24 |
| Peak memory | 296072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860148638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3860148638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.1435069538 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 6987921997 ps |
| CPU time | 170.75 seconds |
| Started | Sep 09 01:27:01 PM UTC 24 |
| Finished | Sep 09 01:29:54 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435069538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1435069538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.579603951 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 533723589 ps |
| CPU time | 15.61 seconds |
| Started | Sep 09 01:26:00 PM UTC 24 |
| Finished | Sep 09 01:26:17 PM UTC 24 |
| Peak memory | 267320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579603951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.579603951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.1116548832 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 579522069 ps |
| CPU time | 15.17 seconds |
| Started | Sep 09 01:26:18 PM UTC 24 |
| Finished | Sep 09 01:26:35 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116548832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1116548832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.3637142960 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 538660952 ps |
| CPU time | 21.7 seconds |
| Started | Sep 09 01:26:37 PM UTC 24 |
| Finished | Sep 09 01:27:00 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637142960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3637142960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.3399290688 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 173063202 ps |
| CPU time | 11.25 seconds |
| Started | Sep 09 01:25:47 PM UTC 24 |
| Finished | Sep 09 01:25:59 PM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399290688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3399290688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.1011968017 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 184140324714 ps |
| CPU time | 2666.55 seconds |
| Started | Sep 09 01:27:49 PM UTC 24 |
| Finished | Sep 09 02:12:44 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011968017 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.1011968017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all_with_rand_reset.762465525 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 8149849350 ps |
| CPU time | 485.56 seconds |
| Started | Sep 09 01:28:25 PM UTC 24 |
| Finished | Sep 09 01:36:37 PM UTC 24 |
| Peak memory | 281860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=762465525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.al ert_handler_stress_all_with_rand_reset.762465525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.2973148968 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 20078901681 ps |
| CPU time | 1471.42 seconds |
| Started | Sep 09 01:30:24 PM UTC 24 |
| Finished | Sep 09 01:55:12 PM UTC 24 |
| Peak memory | 301876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973148968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2973148968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.714569514 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1696803215 ps |
| CPU time | 108.52 seconds |
| Started | Sep 09 01:30:09 PM UTC 24 |
| Finished | Sep 09 01:32:00 PM UTC 24 |
| Peak memory | 269276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714569514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.714569514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.3815788456 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1228297745 ps |
| CPU time | 31.71 seconds |
| Started | Sep 09 01:30:03 PM UTC 24 |
| Finished | Sep 09 01:30:36 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815788456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3815788456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.2153640449 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 63252051678 ps |
| CPU time | 1082.47 seconds |
| Started | Sep 09 01:30:37 PM UTC 24 |
| Finished | Sep 09 01:48:52 PM UTC 24 |
| Peak memory | 299836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153640449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2153640449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.2635315617 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 14933078399 ps |
| CPU time | 1089.32 seconds |
| Started | Sep 09 01:30:59 PM UTC 24 |
| Finished | Sep 09 01:49:21 PM UTC 24 |
| Peak memory | 285504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635315617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2635315617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.812402681 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 12556491254 ps |
| CPU time | 723.19 seconds |
| Started | Sep 09 01:30:35 PM UTC 24 |
| Finished | Sep 09 01:42:47 PM UTC 24 |
| Peak memory | 269448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812402681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.812402681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.1597701236 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 410203081 ps |
| CPU time | 16.99 seconds |
| Started | Sep 09 01:29:54 PM UTC 24 |
| Finished | Sep 09 01:30:13 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597701236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1597701236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.862508869 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 580789272 ps |
| CPU time | 9.99 seconds |
| Started | Sep 09 01:29:57 PM UTC 24 |
| Finished | Sep 09 01:30:08 PM UTC 24 |
| Peak memory | 263292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862508869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.862508869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.3992894780 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1548944152 ps |
| CPU time | 78.01 seconds |
| Started | Sep 09 01:28:43 PM UTC 24 |
| Finished | Sep 09 01:30:03 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992894780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3992894780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.260262716 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3425678933 ps |
| CPU time | 79.59 seconds |
| Started | Sep 09 01:31:18 PM UTC 24 |
| Finished | Sep 09 01:32:40 PM UTC 24 |
| Peak memory | 269436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260262716 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.260262716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/42.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.596882495 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 130175831568 ps |
| CPU time | 683.02 seconds |
| Started | Sep 09 01:33:23 PM UTC 24 |
| Finished | Sep 09 01:44:54 PM UTC 24 |
| Peak memory | 285828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596882495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.596882495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.1547019883 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 14606257075 ps |
| CPU time | 319.43 seconds |
| Started | Sep 09 01:33:02 PM UTC 24 |
| Finished | Sep 09 01:38:26 PM UTC 24 |
| Peak memory | 269104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547019883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1547019883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.3336992094 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 561476017 ps |
| CPU time | 45.64 seconds |
| Started | Sep 09 01:33:00 PM UTC 24 |
| Finished | Sep 09 01:33:47 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336992094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3336992094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.1904888701 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 48024550749 ps |
| CPU time | 1193.72 seconds |
| Started | Sep 09 01:33:48 PM UTC 24 |
| Finished | Sep 09 01:53:56 PM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904888701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1904888701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.3953839676 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 88080814921 ps |
| CPU time | 1245.66 seconds |
| Started | Sep 09 01:33:58 PM UTC 24 |
| Finished | Sep 09 01:54:59 PM UTC 24 |
| Peak memory | 295740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953839676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3953839676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.3551604405 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 154527163397 ps |
| CPU time | 468.67 seconds |
| Started | Sep 09 01:33:42 PM UTC 24 |
| Finished | Sep 09 01:41:36 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551604405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3551604405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.1490425405 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 148919337 ps |
| CPU time | 9.01 seconds |
| Started | Sep 09 01:32:41 PM UTC 24 |
| Finished | Sep 09 01:32:52 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490425405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1490425405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.3588669891 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 383833711 ps |
| CPU time | 24.51 seconds |
| Started | Sep 09 01:32:53 PM UTC 24 |
| Finished | Sep 09 01:33:19 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588669891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3588669891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.1565285084 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 315893346 ps |
| CPU time | 52.47 seconds |
| Started | Sep 09 01:33:20 PM UTC 24 |
| Finished | Sep 09 01:34:14 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565285084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1565285084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.2111411055 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1117618806 ps |
| CPU time | 18.85 seconds |
| Started | Sep 09 01:32:38 PM UTC 24 |
| Finished | Sep 09 01:32:59 PM UTC 24 |
| Peak memory | 263232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111411055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2111411055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.3191774624 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 167888168696 ps |
| CPU time | 2227.77 seconds |
| Started | Sep 09 01:34:15 PM UTC 24 |
| Finished | Sep 09 02:11:46 PM UTC 24 |
| Peak memory | 298460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191774624 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.3191774624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all_with_rand_reset.3343540563 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1319041427 ps |
| CPU time | 194.48 seconds |
| Started | Sep 09 01:35:50 PM UTC 24 |
| Finished | Sep 09 01:39:08 PM UTC 24 |
| Peak memory | 279420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3343540563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.a lert_handler_stress_all_with_rand_reset.3343540563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.2522998654 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 118084437112 ps |
| CPU time | 1735.68 seconds |
| Started | Sep 09 01:37:42 PM UTC 24 |
| Finished | Sep 09 02:06:57 PM UTC 24 |
| Peak memory | 288548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522998654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2522998654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.1489719235 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2038715883 ps |
| CPU time | 221.44 seconds |
| Started | Sep 09 01:37:27 PM UTC 24 |
| Finished | Sep 09 01:41:12 PM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489719235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1489719235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.3769946064 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 882113127 ps |
| CPU time | 64.66 seconds |
| Started | Sep 09 01:37:25 PM UTC 24 |
| Finished | Sep 09 01:38:32 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769946064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3769946064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.384947685 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 11209678274 ps |
| CPU time | 1046.45 seconds |
| Started | Sep 09 01:38:23 PM UTC 24 |
| Finished | Sep 09 01:56:01 PM UTC 24 |
| Peak memory | 285828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384947685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.384947685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.2831654519 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 50718388023 ps |
| CPU time | 3218.93 seconds |
| Started | Sep 09 01:38:28 PM UTC 24 |
| Finished | Sep 09 02:32:43 PM UTC 24 |
| Peak memory | 302560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831654519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2831654519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.3963426429 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 59469632477 ps |
| CPU time | 586.73 seconds |
| Started | Sep 09 01:37:51 PM UTC 24 |
| Finished | Sep 09 01:47:45 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963426429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3963426429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.3050492043 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 849179532 ps |
| CPU time | 42.46 seconds |
| Started | Sep 09 01:37:07 PM UTC 24 |
| Finished | Sep 09 01:37:51 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050492043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3050492043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.1721254128 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 137924614 ps |
| CPU time | 13.26 seconds |
| Started | Sep 09 01:37:14 PM UTC 24 |
| Finished | Sep 09 01:37:28 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721254128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1721254128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.1167583542 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 218783001 ps |
| CPU time | 11.65 seconds |
| Started | Sep 09 01:37:29 PM UTC 24 |
| Finished | Sep 09 01:37:41 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167583542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1167583542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.2101611233 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1355620829 ps |
| CPU time | 45.59 seconds |
| Started | Sep 09 01:36:38 PM UTC 24 |
| Finished | Sep 09 01:37:26 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101611233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2101611233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.1493334334 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 68500168459 ps |
| CPU time | 1842.07 seconds |
| Started | Sep 09 01:38:28 PM UTC 24 |
| Finished | Sep 09 02:09:30 PM UTC 24 |
| Peak memory | 321056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493334334 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.1493334334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all_with_rand_reset.4004509715 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 14140129279 ps |
| CPU time | 220.89 seconds |
| Started | Sep 09 01:38:33 PM UTC 24 |
| Finished | Sep 09 01:42:17 PM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4004509715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.a lert_handler_stress_all_with_rand_reset.4004509715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.3492645336 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 922844791 ps |
| CPU time | 54.23 seconds |
| Started | Sep 09 01:39:35 PM UTC 24 |
| Finished | Sep 09 01:40:31 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492645336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3492645336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.2319937179 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 761094051 ps |
| CPU time | 21.55 seconds |
| Started | Sep 09 01:39:25 PM UTC 24 |
| Finished | Sep 09 01:39:47 PM UTC 24 |
| Peak memory | 263264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319937179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2319937179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.2413452384 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 40011033596 ps |
| CPU time | 1018.89 seconds |
| Started | Sep 09 01:39:50 PM UTC 24 |
| Finished | Sep 09 01:57:01 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413452384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2413452384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.583325955 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 87104333677 ps |
| CPU time | 793.7 seconds |
| Started | Sep 09 01:40:00 PM UTC 24 |
| Finished | Sep 09 01:53:23 PM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583325955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.583325955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.1010318568 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 36338304524 ps |
| CPU time | 420.4 seconds |
| Started | Sep 09 01:39:50 PM UTC 24 |
| Finished | Sep 09 01:46:55 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010318568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1010318568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.2830273319 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 495275548 ps |
| CPU time | 13.5 seconds |
| Started | Sep 09 01:39:09 PM UTC 24 |
| Finished | Sep 09 01:39:24 PM UTC 24 |
| Peak memory | 267324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830273319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2830273319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.320578141 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 11044678395 ps |
| CPU time | 57.82 seconds |
| Started | Sep 09 01:39:15 PM UTC 24 |
| Finished | Sep 09 01:40:15 PM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320578141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.320578141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.1467986585 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 68835756 ps |
| CPU time | 7.55 seconds |
| Started | Sep 09 01:39:39 PM UTC 24 |
| Finished | Sep 09 01:39:47 PM UTC 24 |
| Peak memory | 252732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467986585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1467986585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.909211535 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1343285589 ps |
| CPU time | 63.77 seconds |
| Started | Sep 09 01:39:03 PM UTC 24 |
| Finished | Sep 09 01:40:08 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909211535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.909211535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.1509194888 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 620880165 ps |
| CPU time | 29.88 seconds |
| Started | Sep 09 01:40:09 PM UTC 24 |
| Finished | Sep 09 01:40:40 PM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509194888 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.1509194888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all_with_rand_reset.498980419 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4952666969 ps |
| CPU time | 113.1 seconds |
| Started | Sep 09 01:40:16 PM UTC 24 |
| Finished | Sep 09 01:42:12 PM UTC 24 |
| Peak memory | 279812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=498980419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.al ert_handler_stress_all_with_rand_reset.498980419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.92683297 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 72995809808 ps |
| CPU time | 2318.91 seconds |
| Started | Sep 09 01:41:37 PM UTC 24 |
| Finished | Sep 09 02:20:43 PM UTC 24 |
| Peak memory | 300512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92683297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.92683297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.1315275910 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 348617752 ps |
| CPU time | 34.86 seconds |
| Started | Sep 09 01:41:18 PM UTC 24 |
| Finished | Sep 09 01:41:55 PM UTC 24 |
| Peak memory | 269432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315275910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1315275910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.3859046990 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 3533448483 ps |
| CPU time | 49.27 seconds |
| Started | Sep 09 01:41:13 PM UTC 24 |
| Finished | Sep 09 01:42:04 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859046990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3859046990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.1996043158 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 45149219860 ps |
| CPU time | 2395.79 seconds |
| Started | Sep 09 01:41:56 PM UTC 24 |
| Finished | Sep 09 02:22:16 PM UTC 24 |
| Peak memory | 302888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996043158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1996043158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.1574979002 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 39879025269 ps |
| CPU time | 844.07 seconds |
| Started | Sep 09 01:42:00 PM UTC 24 |
| Finished | Sep 09 01:56:13 PM UTC 24 |
| Peak memory | 295740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574979002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1574979002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.4236396040 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 28648581606 ps |
| CPU time | 252.73 seconds |
| Started | Sep 09 01:41:50 PM UTC 24 |
| Finished | Sep 09 01:46:06 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236396040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4236396040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.1139099575 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 274772277 ps |
| CPU time | 34.03 seconds |
| Started | Sep 09 01:40:42 PM UTC 24 |
| Finished | Sep 09 01:41:17 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139099575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1139099575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.3685195845 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2735704598 ps |
| CPU time | 38.1 seconds |
| Started | Sep 09 01:41:09 PM UTC 24 |
| Finished | Sep 09 01:41:48 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685195845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3685195845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.2330558262 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 685729391 ps |
| CPU time | 46.24 seconds |
| Started | Sep 09 01:41:29 PM UTC 24 |
| Finished | Sep 09 01:42:17 PM UTC 24 |
| Peak memory | 263292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330558262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2330558262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.2925580466 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 964704255 ps |
| CPU time | 85.61 seconds |
| Started | Sep 09 01:40:31 PM UTC 24 |
| Finished | Sep 09 01:41:59 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925580466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2925580466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.2291824093 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 58877777103 ps |
| CPU time | 2841.75 seconds |
| Started | Sep 09 01:42:05 PM UTC 24 |
| Finished | Sep 09 02:29:57 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291824093 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.2291824093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all_with_rand_reset.1816251497 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 2435299424 ps |
| CPU time | 253.84 seconds |
| Started | Sep 09 01:42:12 PM UTC 24 |
| Finished | Sep 09 01:46:30 PM UTC 24 |
| Peak memory | 279476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1816251497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.a lert_handler_stress_all_with_rand_reset.1816251497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.35579852 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 4986294821 ps |
| CPU time | 637.82 seconds |
| Started | Sep 09 01:43:21 PM UTC 24 |
| Finished | Sep 09 01:54:07 PM UTC 24 |
| Peak memory | 285504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35579852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.35579852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.250215333 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 3296742773 ps |
| CPU time | 97.03 seconds |
| Started | Sep 09 01:43:06 PM UTC 24 |
| Finished | Sep 09 01:44:45 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250215333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.250215333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.1591260752 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 99840906 ps |
| CPU time | 16.43 seconds |
| Started | Sep 09 01:42:48 PM UTC 24 |
| Finished | Sep 09 01:43:06 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591260752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1591260752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.1745224593 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 57161608948 ps |
| CPU time | 1100.01 seconds |
| Started | Sep 09 01:43:49 PM UTC 24 |
| Finished | Sep 09 02:02:21 PM UTC 24 |
| Peak memory | 302212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745224593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1745224593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.2520391146 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 77424998249 ps |
| CPU time | 1080.47 seconds |
| Started | Sep 09 01:43:52 PM UTC 24 |
| Finished | Sep 09 02:02:05 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520391146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2520391146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.2107117673 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 5669090818 ps |
| CPU time | 184.76 seconds |
| Started | Sep 09 01:43:21 PM UTC 24 |
| Finished | Sep 09 01:46:29 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107117673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2107117673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.1528268259 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3226646234 ps |
| CPU time | 27.09 seconds |
| Started | Sep 09 01:42:19 PM UTC 24 |
| Finished | Sep 09 01:42:47 PM UTC 24 |
| Peak memory | 262964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528268259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1528268259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.436783398 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 147286210 ps |
| CPU time | 24.74 seconds |
| Started | Sep 09 01:42:48 PM UTC 24 |
| Finished | Sep 09 01:43:14 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436783398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.436783398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.2793628329 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1578637594 ps |
| CPU time | 34.58 seconds |
| Started | Sep 09 01:43:15 PM UTC 24 |
| Finished | Sep 09 01:43:51 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793628329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2793628329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.487419279 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1662631620 ps |
| CPU time | 58.85 seconds |
| Started | Sep 09 01:42:19 PM UTC 24 |
| Finished | Sep 09 01:43:19 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487419279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.487419279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.3598002023 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 19752866770 ps |
| CPU time | 2084.6 seconds |
| Started | Sep 09 01:44:47 PM UTC 24 |
| Finished | Sep 09 02:19:57 PM UTC 24 |
| Peak memory | 315232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598002023 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.3598002023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/47.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.2428388002 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 19638414468 ps |
| CPU time | 1020.35 seconds |
| Started | Sep 09 01:46:06 PM UTC 24 |
| Finished | Sep 09 02:03:19 PM UTC 24 |
| Peak memory | 301876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428388002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2428388002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.1697695636 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 65090959 ps |
| CPU time | 10.6 seconds |
| Started | Sep 09 01:45:47 PM UTC 24 |
| Finished | Sep 09 01:45:59 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697695636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1697695636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.2782828001 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 576745656 ps |
| CPU time | 41.42 seconds |
| Started | Sep 09 01:45:45 PM UTC 24 |
| Finished | Sep 09 01:46:28 PM UTC 24 |
| Peak memory | 263264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782828001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2782828001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.2045259213 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 138134172848 ps |
| CPU time | 1800.45 seconds |
| Started | Sep 09 01:46:29 PM UTC 24 |
| Finished | Sep 09 02:16:50 PM UTC 24 |
| Peak memory | 288224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045259213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2045259213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.1628488065 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 18699679057 ps |
| CPU time | 394.55 seconds |
| Started | Sep 09 01:46:12 PM UTC 24 |
| Finished | Sep 09 01:52:51 PM UTC 24 |
| Peak memory | 269448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628488065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1628488065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.1088164490 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 384083965 ps |
| CPU time | 26.92 seconds |
| Started | Sep 09 01:45:17 PM UTC 24 |
| Finished | Sep 09 01:45:46 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088164490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1088164490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.3827182053 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 581129396 ps |
| CPU time | 49.88 seconds |
| Started | Sep 09 01:45:19 PM UTC 24 |
| Finished | Sep 09 01:46:11 PM UTC 24 |
| Peak memory | 263324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827182053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3827182053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.2284932286 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 1777791479 ps |
| CPU time | 25.53 seconds |
| Started | Sep 09 01:45:59 PM UTC 24 |
| Finished | Sep 09 01:46:26 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284932286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2284932286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.3962233896 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 390251927 ps |
| CPU time | 20.71 seconds |
| Started | Sep 09 01:44:56 PM UTC 24 |
| Finished | Sep 09 01:45:18 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962233896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3962233896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.814932388 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 150317834485 ps |
| CPU time | 1237.57 seconds |
| Started | Sep 09 01:46:30 PM UTC 24 |
| Finished | Sep 09 02:07:22 PM UTC 24 |
| Peak memory | 296060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814932388 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.814932388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/48.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.3140567424 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 36375673517 ps |
| CPU time | 2896.44 seconds |
| Started | Sep 09 01:48:07 PM UTC 24 |
| Finished | Sep 09 02:36:56 PM UTC 24 |
| Peak memory | 304676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140567424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3140567424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.1091147491 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 526511301 ps |
| CPU time | 75.62 seconds |
| Started | Sep 09 01:47:28 PM UTC 24 |
| Finished | Sep 09 01:48:46 PM UTC 24 |
| Peak memory | 269368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091147491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1091147491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.1738128239 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1599830707 ps |
| CPU time | 46.44 seconds |
| Started | Sep 09 01:47:19 PM UTC 24 |
| Finished | Sep 09 01:48:07 PM UTC 24 |
| Peak memory | 269080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738128239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1738128239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.1888017661 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 101621580705 ps |
| CPU time | 2464.37 seconds |
| Started | Sep 09 01:48:15 PM UTC 24 |
| Finished | Sep 09 02:29:45 PM UTC 24 |
| Peak memory | 298464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888017661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1888017661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.512591411 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 49351676636 ps |
| CPU time | 999.95 seconds |
| Started | Sep 09 01:48:25 PM UTC 24 |
| Finished | Sep 09 02:05:18 PM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512591411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.512591411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.945792584 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 53216385472 ps |
| CPU time | 395.15 seconds |
| Started | Sep 09 01:48:12 PM UTC 24 |
| Finished | Sep 09 01:54:52 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945792584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.945792584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.1189305546 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 910330825 ps |
| CPU time | 73.19 seconds |
| Started | Sep 09 01:47:10 PM UTC 24 |
| Finished | Sep 09 01:48:25 PM UTC 24 |
| Peak memory | 269436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189305546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1189305546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.3548849565 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 798476331 ps |
| CPU time | 6.95 seconds |
| Started | Sep 09 01:47:10 PM UTC 24 |
| Finished | Sep 09 01:47:18 PM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548849565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3548849565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.1472349443 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 3576433386 ps |
| CPU time | 26.82 seconds |
| Started | Sep 09 01:47:46 PM UTC 24 |
| Finished | Sep 09 01:48:14 PM UTC 24 |
| Peak memory | 263036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472349443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1472349443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.2215304047 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 2056323148 ps |
| CPU time | 28.92 seconds |
| Started | Sep 09 01:46:56 PM UTC 24 |
| Finished | Sep 09 01:47:27 PM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215304047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2215304047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.2378317393 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 226723480983 ps |
| CPU time | 2782.72 seconds |
| Started | Sep 09 01:48:36 PM UTC 24 |
| Finished | Sep 09 02:35:28 PM UTC 24 |
| Peak memory | 304928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378317393 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.2378317393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.2066902514 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1029788254 ps |
| CPU time | 78.94 seconds |
| Started | Sep 09 01:48:47 PM UTC 24 |
| Finished | Sep 09 01:50:08 PM UTC 24 |
| Peak memory | 281852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2066902514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.a lert_handler_stress_all_with_rand_reset.2066902514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.654838734 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 167426172 ps |
| CPU time | 5.45 seconds |
| Started | Sep 09 11:48:39 AM UTC 24 |
| Finished | Sep 09 11:48:46 AM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654838734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.654838734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.2215994509 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 436558712 ps |
| CPU time | 19.17 seconds |
| Started | Sep 09 11:48:38 AM UTC 24 |
| Finished | Sep 09 11:48:58 AM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215994509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2215994509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.3716153746 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 22136892683 ps |
| CPU time | 103.22 seconds |
| Started | Sep 09 11:48:13 AM UTC 24 |
| Finished | Sep 09 11:49:58 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716153746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3716153746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.1327471247 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1651201221 ps |
| CPU time | 31.36 seconds |
| Started | Sep 09 11:48:11 AM UTC 24 |
| Finished | Sep 09 11:48:44 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327471247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1327471247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.3489013629 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 28873902151 ps |
| CPU time | 1678.08 seconds |
| Started | Sep 09 11:48:31 AM UTC 24 |
| Finished | Sep 09 12:16:50 PM UTC 24 |
| Peak memory | 285828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489013629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3489013629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.81180695 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 72173232231 ps |
| CPU time | 861.5 seconds |
| Started | Sep 09 11:48:36 AM UTC 24 |
| Finished | Sep 09 12:03:07 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81180695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.81180695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.484221048 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 17624288494 ps |
| CPU time | 155.95 seconds |
| Started | Sep 09 11:48:29 AM UTC 24 |
| Finished | Sep 09 11:51:08 AM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484221048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.484221048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.995918833 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 786635102 ps |
| CPU time | 19.76 seconds |
| Started | Sep 09 11:48:07 AM UTC 24 |
| Finished | Sep 09 11:48:28 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995918833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.995918833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.395788592 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 346820040 ps |
| CPU time | 24.43 seconds |
| Started | Sep 09 11:48:09 AM UTC 24 |
| Finished | Sep 09 11:48:35 AM UTC 24 |
| Peak memory | 262892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395788592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.395788592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.1389346288 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 489723032 ps |
| CPU time | 33.03 seconds |
| Started | Sep 09 11:48:19 AM UTC 24 |
| Finished | Sep 09 11:48:53 AM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389346288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1389346288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.2582794144 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 686126503 ps |
| CPU time | 32.44 seconds |
| Started | Sep 09 11:48:07 AM UTC 24 |
| Finished | Sep 09 11:48:41 AM UTC 24 |
| Peak memory | 269244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582794144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2582794144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.985431642 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 9245251141 ps |
| CPU time | 191.46 seconds |
| Started | Sep 09 11:48:38 AM UTC 24 |
| Finished | Sep 09 11:51:52 AM UTC 24 |
| Peak memory | 269444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985431642 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.985431642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all_with_rand_reset.189595300 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4131982470 ps |
| CPU time | 453.55 seconds |
| Started | Sep 09 11:48:42 AM UTC 24 |
| Finished | Sep 09 11:56:22 AM UTC 24 |
| Peak memory | 283580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=189595300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.ale rt_handler_stress_all_with_rand_reset.189595300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.3809725107 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 20157245 ps |
| CPU time | 4.53 seconds |
| Started | Sep 09 11:49:29 AM UTC 24 |
| Finished | Sep 09 11:49:34 AM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809725107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3809725107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.3089850613 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 140048378629 ps |
| CPU time | 2452.56 seconds |
| Started | Sep 09 11:48:59 AM UTC 24 |
| Finished | Sep 09 12:30:19 PM UTC 24 |
| Peak memory | 304680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089850613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3089850613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.426263597 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 460495509 ps |
| CPU time | 29.92 seconds |
| Started | Sep 09 11:49:24 AM UTC 24 |
| Finished | Sep 09 11:49:56 AM UTC 24 |
| Peak memory | 263300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426263597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.426263597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.1761078249 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1492186368 ps |
| CPU time | 103.85 seconds |
| Started | Sep 09 11:48:55 AM UTC 24 |
| Finished | Sep 09 11:50:41 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761078249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1761078249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.113054543 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 865930483 ps |
| CPU time | 28.02 seconds |
| Started | Sep 09 11:48:54 AM UTC 24 |
| Finished | Sep 09 11:49:23 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113054543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.113054543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.4267511827 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 47201321414 ps |
| CPU time | 1206.43 seconds |
| Started | Sep 09 11:49:03 AM UTC 24 |
| Finished | Sep 09 12:09:24 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267511827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.4267511827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.50691178 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 53500182546 ps |
| CPU time | 1437.21 seconds |
| Started | Sep 09 11:49:14 AM UTC 24 |
| Finished | Sep 09 12:13:28 PM UTC 24 |
| Peak memory | 301956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50691178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.50691178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.79668064 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 33567414 ps |
| CPU time | 6.68 seconds |
| Started | Sep 09 11:48:47 AM UTC 24 |
| Finished | Sep 09 11:48:55 AM UTC 24 |
| Peak memory | 265316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79668064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.79668064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.312601655 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 353716965 ps |
| CPU time | 13.85 seconds |
| Started | Sep 09 11:48:47 AM UTC 24 |
| Finished | Sep 09 11:49:02 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312601655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.312601655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.1379765962 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 556212898 ps |
| CPU time | 47.14 seconds |
| Started | Sep 09 11:48:55 AM UTC 24 |
| Finished | Sep 09 11:49:44 AM UTC 24 |
| Peak memory | 263264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379765962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1379765962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.1365348668 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 8371718803 ps |
| CPU time | 85.75 seconds |
| Started | Sep 09 11:48:45 AM UTC 24 |
| Finished | Sep 09 11:50:13 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365348668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1365348668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.3631739351 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 35920573826 ps |
| CPU time | 2598.99 seconds |
| Started | Sep 09 11:49:27 AM UTC 24 |
| Finished | Sep 09 12:33:15 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631739351 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.3631739351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all_with_rand_reset.308998954 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1483327265 ps |
| CPU time | 185.17 seconds |
| Started | Sep 09 11:49:35 AM UTC 24 |
| Finished | Sep 09 11:52:43 AM UTC 24 |
| Peak memory | 281540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=308998954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.ale rt_handler_stress_all_with_rand_reset.308998954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.4206839155 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 21167377 ps |
| CPU time | 4.73 seconds |
| Started | Sep 09 11:51:03 AM UTC 24 |
| Finished | Sep 09 11:51:09 AM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206839155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.4206839155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.4080199673 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 7413568717 ps |
| CPU time | 896.89 seconds |
| Started | Sep 09 11:50:14 AM UTC 24 |
| Finished | Sep 09 12:05:22 PM UTC 24 |
| Peak memory | 281796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080199673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.4080199673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.3561926830 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 815416584 ps |
| CPU time | 19.32 seconds |
| Started | Sep 09 11:50:42 AM UTC 24 |
| Finished | Sep 09 11:51:02 AM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561926830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3561926830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.3624982537 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 7715351669 ps |
| CPU time | 196.52 seconds |
| Started | Sep 09 11:49:59 AM UTC 24 |
| Finished | Sep 09 11:53:19 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624982537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3624982537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.3560485711 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 100322896 ps |
| CPU time | 16.32 seconds |
| Started | Sep 09 11:49:56 AM UTC 24 |
| Finished | Sep 09 11:50:14 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560485711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3560485711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.1140556747 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 28898552774 ps |
| CPU time | 634.49 seconds |
| Started | Sep 09 11:50:17 AM UTC 24 |
| Finished | Sep 09 12:00:59 PM UTC 24 |
| Peak memory | 285832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140556747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1140556747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.3060234940 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 272212940799 ps |
| CPU time | 3017.37 seconds |
| Started | Sep 09 11:50:25 AM UTC 24 |
| Finished | Sep 09 12:41:14 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060234940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3060234940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.2110043585 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 151415927 ps |
| CPU time | 12.25 seconds |
| Started | Sep 09 11:49:47 AM UTC 24 |
| Finished | Sep 09 11:50:01 AM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110043585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2110043585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.1535622309 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 840023498 ps |
| CPU time | 20.84 seconds |
| Started | Sep 09 11:49:54 AM UTC 24 |
| Finished | Sep 09 11:50:16 AM UTC 24 |
| Peak memory | 262936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535622309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1535622309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.1074548135 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 214105551 ps |
| CPU time | 20.12 seconds |
| Started | Sep 09 11:50:02 AM UTC 24 |
| Finished | Sep 09 11:50:24 AM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074548135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1074548135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.423922338 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 861881005 ps |
| CPU time | 68.06 seconds |
| Started | Sep 09 11:49:44 AM UTC 24 |
| Finished | Sep 09 11:50:54 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423922338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.423922338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.1905656603 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1555574741 ps |
| CPU time | 99.63 seconds |
| Started | Sep 09 11:50:55 AM UTC 24 |
| Finished | Sep 09 11:52:36 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905656603 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.1905656603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/7.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.898599917 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 49854956 ps |
| CPU time | 3.83 seconds |
| Started | Sep 09 11:53:07 AM UTC 24 |
| Finished | Sep 09 11:53:12 AM UTC 24 |
| Peak memory | 263180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898599917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.898599917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.3979408692 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 328657475388 ps |
| CPU time | 1876.85 seconds |
| Started | Sep 09 11:52:10 AM UTC 24 |
| Finished | Sep 09 12:23:48 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979408692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3979408692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.2102620745 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 927538148 ps |
| CPU time | 17.85 seconds |
| Started | Sep 09 11:52:45 AM UTC 24 |
| Finished | Sep 09 11:53:04 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102620745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2102620745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.2437006517 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3514060795 ps |
| CPU time | 239.75 seconds |
| Started | Sep 09 11:51:50 AM UTC 24 |
| Finished | Sep 09 11:55:53 AM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437006517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2437006517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.695410639 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1869265089 ps |
| CPU time | 84.54 seconds |
| Started | Sep 09 11:51:40 AM UTC 24 |
| Finished | Sep 09 11:53:06 AM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695410639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.695410639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.271456597 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 15383666574 ps |
| CPU time | 985.38 seconds |
| Started | Sep 09 11:52:38 AM UTC 24 |
| Finished | Sep 09 12:09:14 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271456597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.271456597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.928914023 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 113631632902 ps |
| CPU time | 1675.17 seconds |
| Started | Sep 09 11:52:44 AM UTC 24 |
| Finished | Sep 09 12:20:57 PM UTC 24 |
| Peak memory | 295736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928914023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.928914023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.4163448393 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 6336277114 ps |
| CPU time | 232.68 seconds |
| Started | Sep 09 11:52:15 AM UTC 24 |
| Finished | Sep 09 11:56:12 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163448393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.4163448393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.1448615224 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 514094822 ps |
| CPU time | 36.74 seconds |
| Started | Sep 09 11:51:10 AM UTC 24 |
| Finished | Sep 09 11:51:49 AM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448615224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1448615224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.3015846280 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 931181345 ps |
| CPU time | 54.08 seconds |
| Started | Sep 09 11:51:13 AM UTC 24 |
| Finished | Sep 09 11:52:09 AM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015846280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3015846280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.1117312123 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 281512470 ps |
| CPU time | 20.15 seconds |
| Started | Sep 09 11:51:53 AM UTC 24 |
| Finished | Sep 09 11:52:14 AM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117312123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1117312123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.477809308 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 333346308 ps |
| CPU time | 28.81 seconds |
| Started | Sep 09 11:51:09 AM UTC 24 |
| Finished | Sep 09 11:51:39 AM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477809308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.477809308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.964985928 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 19039940 ps |
| CPU time | 4.7 seconds |
| Started | Sep 09 11:56:08 AM UTC 24 |
| Finished | Sep 09 11:56:13 AM UTC 24 |
| Peak memory | 263376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964985928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.964985928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.3338707961 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 113513195581 ps |
| CPU time | 3356.15 seconds |
| Started | Sep 09 11:54:43 AM UTC 24 |
| Finished | Sep 09 12:51:17 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338707961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3338707961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.666878638 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 732088017 ps |
| CPU time | 43.69 seconds |
| Started | Sep 09 11:55:54 AM UTC 24 |
| Finished | Sep 09 11:56:39 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666878638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.666878638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.1196309371 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1579735273 ps |
| CPU time | 185.69 seconds |
| Started | Sep 09 11:54:10 AM UTC 24 |
| Finished | Sep 09 11:57:19 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196309371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1196309371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.1057238234 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2930908678 ps |
| CPU time | 19.35 seconds |
| Started | Sep 09 11:54:06 AM UTC 24 |
| Finished | Sep 09 11:54:26 AM UTC 24 |
| Peak memory | 262964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057238234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1057238234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.1258115121 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 119715692943 ps |
| CPU time | 1830.93 seconds |
| Started | Sep 09 11:55:51 AM UTC 24 |
| Finished | Sep 09 12:26:43 PM UTC 24 |
| Peak memory | 300164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258115121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1258115121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.2629839622 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 2312173589 ps |
| CPU time | 77.88 seconds |
| Started | Sep 09 11:55:05 AM UTC 24 |
| Finished | Sep 09 11:56:24 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629839622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2629839622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.3800087966 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 943910804 ps |
| CPU time | 19.07 seconds |
| Started | Sep 09 11:53:41 AM UTC 24 |
| Finished | Sep 09 11:54:02 AM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800087966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3800087966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.4033264473 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 4097021332 ps |
| CPU time | 105.61 seconds |
| Started | Sep 09 11:54:02 AM UTC 24 |
| Finished | Sep 09 11:55:50 AM UTC 24 |
| Peak memory | 262964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033264473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.4033264473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.3867718888 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 481805694 ps |
| CPU time | 44 seconds |
| Started | Sep 09 11:54:27 AM UTC 24 |
| Finished | Sep 09 11:55:12 AM UTC 24 |
| Peak memory | 269080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867718888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3867718888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.1735755699 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2286171825 ps |
| CPU time | 47.23 seconds |
| Started | Sep 09 11:53:20 AM UTC 24 |
| Finished | Sep 09 11:54:09 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735755699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1735755699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.3900797222 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 57495560339 ps |
| CPU time | 1518.08 seconds |
| Started | Sep 09 11:56:02 AM UTC 24 |
| Finished | Sep 09 12:21:38 PM UTC 24 |
| Peak memory | 285492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900797222 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.3900797222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all_with_rand_reset.2017740175 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1238851532 ps |
| CPU time | 126.52 seconds |
| Started | Sep 09 11:56:13 AM UTC 24 |
| Finished | Sep 09 11:58:22 AM UTC 24 |
| Peak memory | 279740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2017740175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.al ert_handler_stress_all_with_rand_reset.2017740175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest |
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