ASSERT | PROPERTIES | SEQUENCES | |
Total | 1279 | 0 | 10 |
Category 0 | 1279 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 1279 | 0 | 10 |
Severity 0 | 1279 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 1279 | 100.00 |
Uncovered | 2 | 0.16 |
Success | 1277 | 99.84 |
Failure | 0 | 0.00 |
Incomplete | 49 | 3.83 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 6 | 60.00 |
All Matches | 4 | 40.00 |
First Matches | 4 | 40.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | |
tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed.CheckSwAccessIsLegal_A | 0 | 0 | 828 | 828 | 0 | 0 | |
tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed.MubiIsNotYetSupported_A | 0 | 0 | 578087495 | 577460106 | 0 | 0 | |
tb.dut.u_reg_wrap.u_reg.u_reg_if.AllowedLatency_A | 0 | 0 | 828 | 828 | 0 | 0 | |
tb.dut.u_reg_wrap.u_reg.u_reg_if.MatchedWidthAssert | 0 | 0 | 828 | 828 | 0 | 0 | |
tb.dut.u_reg_wrap.u_reg.u_reg_if.u_err.dataWidthOnly32_A | 0 | 0 | 828 | 828 | 0 | 0 | |
tb.dut.u_reg_wrap.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A | 0 | 0 | 828 | 828 | 0 | 0 | |
tb.dut.u_reg_wrap.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck | 0 | 0 | 828 | 828 | 0 | 0 | |
tb.dut.u_reg_wrap.u_reg.u_rsp_intg_gen.DataWidthCheck_A | 0 | 0 | 828 | 828 | 0 | 0 | |
tb.dut.u_reg_wrap.u_reg.u_rsp_intg_gen.PayLoadWidthCheck | 0 | 0 | 828 | 828 | 0 | 0 | |
tb.dut.u_reg_wrap.u_reg.wePulse | 0 | 0 | 578087495 | 65239814 | 0 | 0 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 578088007 | 0 | 0 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 578088007 | 0 | 0 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 578088007 | 0 | 0 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 578088007 | 0 | 0 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 578088007 | 0 | 0 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 578088007 | 0 | 0 | 0 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 578088007 | 142918 | 142918 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 578088007 | 52567 | 52567 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 578088007 | 2073774 | 2073774 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 578088007 | 39213747 | 39213747 | 776 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 578088007 | 142918 | 142918 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 578088007 | 52567 | 52567 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 578088007 | 2073774 | 2073774 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 578088007 | 39213747 | 39213747 | 776 |