Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	554507586	0	0	623
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	554507586	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	554507586	554357095	0	0
tb.dut.CheckAccuCntDw	0	0	623	623	0	0
tb.dut.CheckEscCntDw	0	0	623	623	0	0
tb.dut.CheckNAlerts	0	0	623	623	0	0
tb.dut.CheckNClasses	0	0	623	623	0	0
tb.dut.CheckNEscSev	0	0	623	623	0	0
tb.dut.CrashdumpKnownO_A	0	0	554507586	554357095	0	0
tb.dut.EdnKnownO_A	0	0	554507586	554357095	0	0
tb.dut.EscPKnownO_A	0	0	554507586	554357095	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	554507586	60	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	554507586	60	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	554507586	60	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	554507586	60	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	554507586	60	0	0
tb.dut.IrqAKnownO_A	0	0	554507586	554357095	0	0
tb.dut.IrqBKnownO_A	0	0	554507586	554357095	0	0
tb.dut.IrqCKnownO_A	0	0	554507586	554357095	0	0
tb.dut.IrqDKnownO_A	0	0	554507586	554357095	0	0
tb.dut.TlAReadyKnownO_A	0	0	554507586	554357095	0	0
tb.dut.TlDValidKnownO_A	0	0	554507586	554357095	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	578087495	197440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	578087495	9868	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	578087495	10094	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	578087495	9713	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	578087495	9646	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	578087495	9798	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	578087495	10970	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	578087495	10928	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	578087495	11841	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	578087495	10978	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	578087495	9762	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	578087495	11130	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	578087495	10806	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	578087495	9896	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	578087495	11009	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	578087495	9779	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	578087495	10005	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	578087495	12149	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	578087495	10989	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	578087495	10718	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	578087495	9566	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	578087495	11190	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	578087495	9677	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	578087495	9740	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	578087495	11008	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	578087495	10044	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	578087495	10046	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	578087495	9815	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	578087495	9970	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	578087495	12350	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	578087495	9891	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	578087495	9835	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	578087495	9736	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	578087495	11017	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	578087495	9718	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	578087495	10067	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	578087495	10797	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	578087495	9951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	578087495	10995	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	578087495	10301	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	578087495	9780	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	578087495	9572	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	578087495	9931	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	578087495	10975	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	578087495	9806	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	578087495	11297	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	578087495	9916	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	578087495	9738	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	578087495	11086	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	578087495	11038	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	578087495	9578	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	578087495	10091	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	578087495	9775	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	578087495	11013	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	578087495	9784	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	578087495	9581	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	578087495	9769	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	578087495	9732	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	578087495	9696	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	578087495	9981	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	578087495	11034	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	578087495	9751	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	578087495	9670	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	578087495	9887	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	578087495	12479	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	578087495	11000	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	578087495	9839	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	578087495	9963	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	578087495	11162	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	578087495	11128	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	578087495	20378	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	578087495	11024	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	578087495	10009	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	578087495	10959	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	578087495	9849	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	578087495	11025	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	578087495	11143	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	578087495	12255	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	578087495	10851	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	554507586	4341	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	554507586	192734	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	554507586	276407872	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	554507586	171	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	554507586	871	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	554507586	61	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	554507586	474	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	554394044	205444603	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	554507586	962	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	554507586	935	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	554507586	907	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	554507586	882	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	554507586	1013	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	554507586	93741	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	554507586	887	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	554507586	61	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	554507586	976	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	554507586	796	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	554392683	554319245	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	554507586	554357095	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	554507586	1254	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	554507586	170308	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	554507586	303928857	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	554507586	188	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	554507586	476	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	554507586	27	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	554507586	216	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	554394044	230573210	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	554507586	548	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	554507586	535	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	554507586	525	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	554507586	517	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	554507586	820	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	554507586	82154	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	554507586	727	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	554507586	59	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	554507586	927	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	554507586	747	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	554392683	554319245	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	554507586	554357095	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	554507586	3778	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	554507586	161284	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	554507586	320725432	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	554507586	217	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	554507586	497	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	554507586	21	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	554507586	241	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	554394044	256409559	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	554507586	563	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	554507586	550	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	554507586	537	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	554507586	526	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	554507586	882	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	554507586	90440	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	554507586	803	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	554507586	57	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	554507586	958	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	554507586	778	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	554392683	554319245	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	554507586	554357095	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	554507586	60	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	554507586	3770	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	554507586	150242	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	554507586	336454586	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	554507586	185	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	554507586	507	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	554507586	16	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	554507586	243	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	554394044	241028878	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	554507586	568	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	554507586	559	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	554507586	547	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	554507586	537	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	554507586	846	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	554507586	95338	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	554507586	770	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	554507586	58	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	554507586	1011	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	554507586	831	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	554392683	554319245	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	554507586	554357095	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	578087495	83331606	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	578087495	577460106	0	0
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