Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	53197	1			T12	36		T45	4		T18	1
class_i[0x1]	47273	1			T30	4		T18	1		T53	73
class_i[0x2]	50203	1			T30	130		T45	49		T18	1
class_i[0x3]	62648	1			T45	6		T74	130		T18	1

---

Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	52627	1			T12	12		T30	17		T45	1
alert[0x1]	56613	1			T12	11		T30	16		T45	11
alert[0x2]	51287	1			T12	7		T30	72		T45	3
alert[0x3]	52794	1			T12	6		T30	29		T45	44

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

213065

1

T12

36

T30

134

T45

59

esc_ping_fail

256

1

T18

4

T20

7

T21

4

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	52548	1			T12	12		T30	17		T45	1
esc_integrity_fail	alert[0x1]	56555	1			T12	11		T30	16		T45	11
esc_integrity_fail	alert[0x2]	51219	1			T12	7		T30	72		T45	3
esc_integrity_fail	alert[0x3]	52743	1			T12	6		T30	29		T45	44
esc_ping_fail	alert[0x0]	79	1			T18	2		T20	1		T21	1
esc_ping_fail	alert[0x1]	58	1			T18	1		T20	3		T21	1
esc_ping_fail	alert[0x2]	68	1			T18	1		T20	2		T21	1
esc_ping_fail	alert[0x3]	51	1			T20	1		T21	1		T136	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	53148	1			T12	36		T45	4		T90	1
esc_integrity_fail	class_i[0x1]	47201	1			T30	4		T53	73		T55	13
esc_integrity_fail	class_i[0x2]	50126	1			T30	130		T45	49		T55	1767
esc_integrity_fail	class_i[0x3]	62590	1			T45	6		T74	130		T53	249
esc_ping_fail	class_i[0x0]	49	1			T18	1		T21	1		T136	5
esc_ping_fail	class_i[0x1]	72	1			T18	1		T21	3		T138	7
esc_ping_fail	class_i[0x2]	77	1			T18	1		T314	4		T309	2
esc_ping_fail	class_i[0x3]	58	1			T18	1		T20	7		T311	4