Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	0	44	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	0	44	100.00	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	185	1			T2	1		T10	1		T31	1
index[0x1]	152	1			T17	1		T18	1		T55	1
index[0x2]	184	1			T13	1		T74	1		T41	1
index[0x3]	177	1			T12	1		T52	1		T94	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	222	1			T12	1		T17	1		T74	1
lens_less_than_1000[1]	129	1			T10	1		T31	1		T77	1
lens_less_than_1000[2]	101	1			T2	1		T13	1		T52	1
lens_less_than_1000[3]	60	1			T55	1		T37	1		T62	1
lens_less_than_1000[4]	56	1			T31	2		T46	1		T84	1
lens_less_than_1000[5]	40	1			T55	1		T26	1		T37	1
lens_less_than_1000[6]	46	1			T46	1		T55	1		T32	1
lens_less_than_1000[7]	23	1			T125	1		T337	1		T306	1
lens_less_than_1000[8]	4	1			T338	1		T276	1		T339	2
lens_less_than_1000[9]	8	1			T340	2		T124	1		T341	1
len_2	9	1			T19	1		T37	1		T88	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	0	44	100.00

Automatically Generated Cross Bins for len_per_esc_sig

Bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	55	1			T84	1		T79	1		T310	1
index[0x0]	lens_less_than_1000[1]	27	1			T10	1		T31	1		T26	1
index[0x0]	lens_less_than_1000[2]	25	1			T2	1		T35	1		T342	1
index[0x0]	lens_less_than_1000[3]	18	1			T33	1		T35	1		T343	1
index[0x0]	lens_less_than_1000[4]	11	1			T46	1		T84	1		T293	1
index[0x0]	lens_less_than_1000[5]	13	1			T55	1		T26	1		T140	1
index[0x0]	lens_less_than_1000[6]	22	1			T46	1		T32	1		T260	1
index[0x0]	lens_less_than_1000[7]	9	1			T125	1		T337	1		T344	1
index[0x0]	lens_less_than_1000[8]	1	1			T338	1		-	-		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T281	1		-	-		-	-
index[0x0]	len_2	3	1			T88	1		T132	1		T345	1
index[0x1]	lens_less_than_1000[0]	54	1			T17	1		T18	1		T86	1
index[0x1]	lens_less_than_1000[1]	37	1			T79	1		T32	1		T109	6
index[0x1]	lens_less_than_1000[2]	17	1			T297	1		T340	1		T262	1
index[0x1]	lens_less_than_1000[3]	12	1			T55	1		T37	1		T62	1
index[0x1]	lens_less_than_1000[4]	12	1			T346	1		T265	1		T70	1
index[0x1]	lens_less_than_1000[5]	11	1			T312	1		T340	1		T347	1
index[0x1]	lens_less_than_1000[6]	4	1			T63	1		T319	1		T121	1
index[0x1]	lens_less_than_1000[7]	1	1			T348	1		-	-		-	-
index[0x1]	lens_less_than_1000[8]	1	1			T276	1		-	-		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T341	1		-	-		-	-
index[0x1]	len_2	2	1			T349	1		T291	1		-	-
index[0x2]	lens_less_than_1000[0]	58	1			T74	1		T55	1		T26	3
index[0x2]	lens_less_than_1000[1]	31	1			T77	1		T126	1		T67	1
index[0x2]	lens_less_than_1000[2]	27	1			T13	1		T41	1		T20	1
index[0x2]	lens_less_than_1000[3]	18	1			T350	1		T118	1		T351	1
index[0x2]	lens_less_than_1000[4]	16	1			T26	2		T62	1		T262	1
index[0x2]	lens_less_than_1000[5]	5	1			T37	1		T136	1		T352	1
index[0x2]	lens_less_than_1000[6]	13	1			T340	4		T153	3		T263	1
index[0x2]	lens_less_than_1000[7]	9	1			T265	1		T153	2		T135	1
index[0x2]	lens_less_than_1000[8]	1	1			T339	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	3	1			T353	1		T281	1		T354	1
index[0x2]	len_2	3	1			T19	1		T37	1		T355	1
index[0x3]	lens_less_than_1000[0]	55	1			T12	1		T61	1		T62	1
index[0x3]	lens_less_than_1000[1]	34	1			T46	1		T86	1		T48	1
index[0x3]	lens_less_than_1000[2]	32	1			T52	1		T94	1		T20	1
index[0x3]	lens_less_than_1000[3]	12	1			T319	1		T70	1		T356	1
index[0x3]	lens_less_than_1000[4]	17	1			T31	2		T26	1		T88	2
index[0x3]	lens_less_than_1000[5]	11	1			T93	1		T141	1		T263	1
index[0x3]	lens_less_than_1000[6]	7	1			T55	1		T340	1		T357	1
index[0x3]	lens_less_than_1000[7]	4	1			T306	1		T358	1		T359	1
index[0x3]	lens_less_than_1000[8]	1	1			T339	1		-	-		-	-
index[0x3]	lens_less_than_1000[9]	3	1			T340	2		T124	1		-	-
index[0x3]	len_2	1	1			T360	1		-	-		-	-