Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	61	1			T13	1		T40	1		T53	1
class_index[0x1]	59	1			T40	1		T90	1		T99	1
class_index[0x2]	57	1			T30	1		T57	1		T47	1
class_index[0x3]	58	1			T16	1		T13	1		T74	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	84	1			T16	1		T13	1		T30	1
intr_timeout_cnt[1]	62	1			T13	1		T26	1		T93	2
intr_timeout_cnt[2]	26	1			T40	1		T53	1		T90	1
intr_timeout_cnt[3]	9	1			T98	1		T61	1		T264	1
intr_timeout_cnt[4]	12	1			T101	1		T265	1		T124	1
intr_timeout_cnt[5]	6	1			T53	1		T266	3		T267	1
intr_timeout_cnt[6]	9	1			T110	1		T124	1		T268	1
intr_timeout_cnt[7]	4	1			T266	1		T269	1		T270	1
intr_timeout_cnt[8]	13	1			T57	1		T154	1		T110	2
intr_timeout_cnt[9]	10	1			T37	1		T86	1		T266	3

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[7] , intr_timeout_cnt[8]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	23	1			T13	1		T40	1		T55	1
class_index[0x0]	intr_timeout_cnt[1]	17	1			T26	1		T93	1		T271	6
class_index[0x0]	intr_timeout_cnt[2]	10	1			T53	1		T101	4		T102	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T98	1		T264	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	2	1			T272	1		T273	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T124	1		T268	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	5	1			T37	1		T86	1		T266	3
class_index[0x1]	intr_timeout_cnt[0]	17	1			T99	1		T100	1		T103	1
class_index[0x1]	intr_timeout_cnt[1]	16	1			T274	1		T70	1		T116	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T40	1		T90	1		T64	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T61	1		T117	1		T273	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T101	1		T265	1		T273	1
class_index[0x1]	intr_timeout_cnt[5]	4	1			T266	3		T135	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T275	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T269	1		T270	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	5	1			T110	2		T269	1		T276	1
class_index[0x1]	intr_timeout_cnt[9]	2	1			T277	1		T278	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	24	1			T30	1		T47	1		T142	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T88	1		T140	1		T64	3
class_index[0x2]	intr_timeout_cnt[2]	4	1			T143	1		T279	1		T254	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T272	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	3	1			T124	1		T280	1		T281	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T267	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	3	1			T282	1		T283	1		T273	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T266	1		T284	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T57	1		T285	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T286	1		T270	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	20	1			T16	1		T74	1		T61	1
class_index[0x3]	intr_timeout_cnt[1]	15	1			T13	1		T93	1		T143	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T37	1		T265	1		T263	2
class_index[0x3]	intr_timeout_cnt[3]	2	1			T287	1		T149	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	4	1			T288	1		T285	1		T289	1
class_index[0x3]	intr_timeout_cnt[5]	1	1			T53	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	3	1			T110	1		T290	2		-	-
class_index[0x3]	intr_timeout_cnt[8]	6	1			T154	1		T279	1		T276	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T291	1		-	-		-	-