Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	296435	1			T1	3		T2	11		T3	13
all_values[1]	296435	1			T1	3		T2	11		T3	13
all_values[2]	296435	1			T1	3		T2	11		T3	13
all_values[3]	296435	1			T1	3		T2	11		T3	13

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

589813

1

T1

9

T2

20

T3

30

auto[1]

595927

1

T1

3

T2

24

T3

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

699979

1

T1

8

T2

24

T3

46

auto[1]

485761

1

T1

4

T2

20

T3

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	85754	1			T1	2		T2	1		T3	4
all_values[0]	auto[0]	auto[1]	61889	1			T1	1		T2	1		T3	4
all_values[0]	auto[1]	auto[0]	86919	1			T2	5		T3	3		T10	7
all_values[0]	auto[1]	auto[1]	61873	1			T2	4		T3	2		T10	1
all_values[1]	auto[0]	auto[0]	87528	1			T1	2		T2	3		T3	11
all_values[1]	auto[0]	auto[1]	60408	1			T1	1		T2	3		T12	2
all_values[1]	auto[1]	auto[0]	88503	1			T2	3		T3	2		T10	6
all_values[1]	auto[1]	auto[1]	59996	1			T2	2		T12	1		T16	1
all_values[2]	auto[0]	auto[0]	85755	1			T2	3		T3	4		T10	4
all_values[2]	auto[0]	auto[1]	60917	1			T2	3		T12	4		T16	1
all_values[2]	auto[1]	auto[0]	88064	1			T1	2		T2	3		T3	9
all_values[2]	auto[1]	auto[1]	61699	1			T1	1		T2	2		T12	2
all_values[3]	auto[0]	auto[0]	88136	1			T1	2		T2	3		T3	7
all_values[3]	auto[0]	auto[1]	59426	1			T1	1		T2	3		T12	4
all_values[3]	auto[1]	auto[0]	89320	1			T2	3		T3	6		T10	2
all_values[3]	auto[1]	auto[1]	59553	1			T2	2		T12	2		T16	1