Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	296435	1			T1	3		T2	11		T3	13
all_pins[1]	296435	1			T1	3		T2	11		T3	13
all_pins[2]	296435	1			T1	3		T2	11		T3	13
all_pins[3]	296435	1			T1	3		T2	11		T3	13

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	942619	1			T1	11		T2	34		T3	50
values[0x1]	243121	1			T1	1		T2	10		T3	2
transitions[0x0=>0x1]	160483	1			T1	1		T2	6		T3	2
transitions[0x1=>0x0]	160736	1			T1	1		T2	7		T3	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	234562	1			T1	3		T2	7		T3	11
all_pins[0]	values[0x1]	61873	1			T2	4		T3	2		T10	1
all_pins[0]	transitions[0x0=>0x1]	61319	1			T2	3		T3	2		T10	1
all_pins[0]	transitions[0x1=>0x0]	59252	1			T2	2		T12	1		T16	1
all_pins[1]	values[0x0]	236439	1			T1	3		T2	9		T3	13
all_pins[1]	values[0x1]	59996	1			T2	2		T12	1		T16	1
all_pins[1]	transitions[0x0=>0x1]	33256	1			T2	1		T12	1		T17	1
all_pins[1]	transitions[0x1=>0x0]	35133	1			T2	3		T3	2		T10	1
all_pins[2]	values[0x0]	234736	1			T1	2		T2	9		T3	13
all_pins[2]	values[0x1]	61699	1			T1	1		T2	2		T12	2
all_pins[2]	transitions[0x0=>0x1]	33848	1			T1	1		T2	1		T12	2
all_pins[2]	transitions[0x1=>0x0]	32145	1			T2	1		T12	1		T17	1
all_pins[3]	values[0x0]	236882	1			T1	3		T2	9		T3	13
all_pins[3]	values[0x1]	59553	1			T2	2		T12	2		T16	1
all_pins[3]	transitions[0x0=>0x1]	32060	1			T2	1		T12	2		T16	1
all_pins[3]	transitions[0x1=>0x0]	34206	1			T1	1		T2	1		T12	2