Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T221	7		T222	4		T251	7
all_values[1]	278	1			T221	7		T222	4		T251	7
all_values[2]	278	1			T221	7		T222	4		T251	7
all_values[3]	278	1			T221	7		T222	4		T251	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

604

1

T221

14

T222

12

T251

15

auto[1]

508

1

T221

14

T222

4

T251

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

470

1

T221

8

T222

8

T251

12

auto[1]

642

1

T221

20

T222

8

T251

16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668

1

T221

11

T222

12

T251

17

auto[1]

444

1

T221

17

T222

4

T251

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

49

1

T221

1

T222

2

T251

2

all_values[0]

auto[0]

auto[0]

auto[1]

16

1

T251

1

T383

1

T384

3

all_values[0]

auto[0]

auto[1]

auto[0]

59

1

T221

1

T222

1

T383

2

all_values[0]

auto[0]

auto[1]

auto[1]

32

1

T251

1

T383

1

T385

1

all_values[0]

auto[1]

auto[0]

auto[1]

63

1

T222

1

T251

1

T383

2

all_values[0]

auto[1]

auto[1]

auto[1]

59

1

T221

5

T251

2

T383

1

all_values[1]

auto[0]

auto[0]

auto[0]

66

1

T221

3

T222

1

T251

4

all_values[1]

auto[0]

auto[0]

auto[1]

19

1

T222

1

T385

1

T386

1

all_values[1]

auto[0]

auto[1]

auto[0]

62

1

T221

1

T383

3

T387

2

all_values[1]

auto[0]

auto[1]

auto[1]

26

1

T222

1

T251

1

T383

2

all_values[1]

auto[1]

auto[0]

auto[1]

61

1

T221

3

T222

1

T383

1

all_values[1]

auto[1]

auto[1]

auto[1]

44

1

T251

2

T385

1

T388

1

all_values[2]

auto[0]

auto[0]

auto[0]

59

1

T222

3

T251

3

T383

2

all_values[2]

auto[0]

auto[0]

auto[1]

33

1

T383

1

T385

1

T388

1

all_values[2]

auto[0]

auto[1]

auto[0]

48

1

T222

1

T383

1

T386

2

all_values[2]

auto[0]

auto[1]

auto[1]

30

1

T221

1

T251

1

T387

2

all_values[2]

auto[1]

auto[0]

auto[1]

64

1

T221

3

T383

3

T387

1

all_values[2]

auto[1]

auto[1]

auto[1]

44

1

T221

3

T251

3

T387

1

all_values[3]

auto[0]

auto[0]

auto[0]

84

1

T221

1

T383

3

T387

3

all_values[3]

auto[0]

auto[0]

auto[1]

24

1

T221

1

T222

1

T251

1

all_values[3]

auto[0]

auto[1]

auto[0]

43

1

T221

1

T251

3

T387

1

all_values[3]

auto[0]

auto[1]

auto[1]

18

1

T221

1

T222

1

T386

2

all_values[3]

auto[1]

auto[0]

auto[1]

66

1

T221

2

T222

2

T251

3

all_values[3]

auto[1]

auto[1]

auto[1]

43

1

T221

1

T386

1

T388

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal