Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	79085	1			T55	26		T125	453		T303	1008
accum_cnt_1000	175111	1			T53	1		T55	25		T26	2
accum_cnt_100	23129	1			T43	5		T44	6		T30	5
accum_cnt_50	53529	1			T3	8		T43	14		T15	28
accum_cnt_10	162636	1			T1	4		T2	14		T3	2
accum_cnt_0	342367	1			T1	4		T2	18		T3	30

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	219736	1			T1	2		T2	8		T3	10
class_index[0x1]	219736	1			T1	2		T2	8		T3	10
class_index[0x2]	219736	1			T1	2		T2	8		T3	10
class_index[0x3]	219736	1			T1	2		T2	8		T3	10

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	21729	1			T143	71		T304	74		T305	706
class_index[0x0]	accum_cnt_1000	44664	1			T55	15		T48	6		T137	16
class_index[0x0]	accum_cnt_100	8488	1			T43	5		T52	9		T94	17
class_index[0x0]	accum_cnt_50	10795	1			T3	8		T43	14		T30	12
class_index[0x0]	accum_cnt_10	40656	1			T2	5		T3	2		T10	4
class_index[0x0]	accum_cnt_0	80982	1			T1	2		T2	3		T10	5
class_index[0x1]	accum_cnt_2000	20461	1			T125	250		T303	533		T141	55
class_index[0x1]	accum_cnt_1000	43855	1			T55	6		T162	33		T87	1
class_index[0x1]	accum_cnt_100	4328	1			T94	3		T95	5		T55	22
class_index[0x1]	accum_cnt_50	12066	1			T94	22		T95	12		T40	4
class_index[0x1]	accum_cnt_10	40397	1			T2	1		T12	8		T16	1
class_index[0x1]	accum_cnt_0	87619	1			T1	2		T2	7		T3	10
class_index[0x2]	accum_cnt_2000	21382	1			T55	26		T303	475		T143	21
class_index[0x2]	accum_cnt_1000	45959	1			T162	30		T79	28		T137	44
class_index[0x2]	accum_cnt_100	4700	1			T44	6		T30	5		T45	12
class_index[0x2]	accum_cnt_50	12019	1			T15	14		T44	12		T30	9
class_index[0x2]	accum_cnt_10	39713	1			T1	2		T2	3		T12	1
class_index[0x2]	accum_cnt_0	86116	1			T2	5		T3	10		T10	9
class_index[0x3]	accum_cnt_2000	15513	1			T125	203		T143	69		T306	190
class_index[0x3]	accum_cnt_1000	40633	1			T53	1		T55	4		T26	2
class_index[0x3]	accum_cnt_100	5613	1			T94	6		T74	9		T55	17
class_index[0x3]	accum_cnt_50	18649	1			T15	14		T30	14		T94	20
class_index[0x3]	accum_cnt_10	41870	1			T1	2		T2	5		T16	1
class_index[0x3]	accum_cnt_0	87650	1			T2	3		T3	10		T10	9