Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	6358	1			T53	2		T57	1		T21	1
alert[0x1]	3327	1			T86	5		T21	1		T48	7
alert[0x2]	2976	1			T53	19		T37	18		T86	2
alert[0x3]	3905	1			T45	1		T74	2		T55	71
alert[0x4]	4812	1			T57	1		T307	150		T308	1
alert[0x5]	6658	1			T138	1		T64	23		T294	1
alert[0x6]	8229	1			T55	1		T57	5		T309	1
alert[0x7]	5145	1			T57	6		T26	4		T20	1
alert[0x8]	7403	1			T53	1		T57	6		T136	1
alert[0x9]	2212	1			T136	1		T138	1		T310	2
alert[0xa]	3755	1			T57	10		T20	1		T87	2
alert[0xb]	5918	1			T12	1		T138	1		T115	3
alert[0xc]	2283	1			T19	1		T87	38		T311	1
alert[0xd]	5442	1			T48	6		T136	1		T252	4
alert[0xe]	4583	1			T48	2		T138	1		T310	1
alert[0xf]	2829	1			T48	30		T136	1		T138	1
alert[0x10]	5054	1			T30	9		T20	1		T21	1
alert[0x11]	5528	1			T12	5		T55	1		T60	1
alert[0x12]	10067	1			T53	5		T37	1		T20	1
alert[0x13]	3427	1			T74	9		T307	39		T308	1
alert[0x14]	2975	1			T57	15		T252	3		T307	24
alert[0x15]	5700	1			T312	23		T313	60		T67	9
alert[0x16]	11118	1			T48	436		T136	1		T138	1
alert[0x17]	8380	1			T35	6		T125	21		T113	1
alert[0x18]	2732	1			T55	1		T87	9		T48	2
alert[0x19]	4797	1			T53	1		T55	2		T310	1
alert[0x1a]	4005	1			T45	29		T18	1		T87	2
alert[0x1b]	7936	1			T30	31		T310	1		T33	9
alert[0x1c]	12802	1			T312	107		T141	4		T143	2
alert[0x1d]	5152	1			T30	8		T48	17		T310	1
alert[0x1e]	4532	1			T45	17		T48	184		T136	1
alert[0x1f]	8203	1			T30	2		T55	2		T48	3
alert[0x20]	10347	1			T30	1		T60	1		T32	2
alert[0x21]	3371	1			T26	2		T21	1		T138	1
alert[0x22]	2314	1			T55	1		T20	2		T87	11
alert[0x23]	1431	1			T45	1		T48	20		T310	1
alert[0x24]	2726	1			T53	1		T55	3		T314	1
alert[0x25]	5190	1			T55	21		T86	2		T48	1
alert[0x26]	5046	1			T20	1		T61	1		T315	1
alert[0x27]	5879	1			T45	2		T87	1		T314	1
alert[0x28]	7378	1			T33	19		T316	1		T315	1
alert[0x29]	5543	1			T53	3		T48	1		T33	96
alert[0x2a]	1544	1			T87	1		T48	70		T33	1
alert[0x2b]	1898	1			T20	1		T21	1		T310	1
alert[0x2c]	3700	1			T18	1		T19	1		T87	5
alert[0x2d]	4923	1			T48	10		T138	1		T60	2
alert[0x2e]	2815	1			T20	1		T87	1		T61	1
alert[0x2f]	13043	1			T18	1		T21	1		T87	2
alert[0x30]	5946	1			T87	8		T48	28		T136	1
alert[0x31]	2796	1			T26	74		T19	1		T317	1
alert[0x32]	1196	1			T138	1		T316	1		T312	104
alert[0x33]	2121	1			T30	5		T57	1		T87	10
alert[0x34]	2881	1			T115	4		T252	1		T315	1
alert[0x35]	4196	1			T45	13		T314	1		T317	1
alert[0x36]	2619	1			T74	5		T18	1		T57	6
alert[0x37]	3955	1			T74	2		T18	1		T57	4
alert[0x38]	7017	1			T19	1		T87	6		T138	1
alert[0x39]	3909	1			T45	10		T74	3		T136	2
alert[0x3a]	6413	1			T12	3		T60	13		T115	15
alert[0x3b]	3992	1			T309	1		T316	1		T312	39
alert[0x3c]	2845	1			T57	2		T48	16		T310	1
alert[0x3d]	6557	1			T12	6		T74	1		T18	1
alert[0x3e]	3456	1			T138	1		T310	1		T60	31
alert[0x3f]	4511	1			T48	2		T138	1		T98	32
alert[0x40]	2752	1			T12	1		T45	11		T317	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	125411	1			T45	83		T74	15		T18	1
class_i[0x1]	50960	1			T12	6		T74	1		T18	1
class_i[0x2]	78245	1			T12	10		T30	5		T45	1
class_i[0x3]	67937	1			T30	51		T18	1		T53	2

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

321895

1

T12

16

T30

56

T45

84

alert_ping_fail

658

1

T18

6

T19

6

T20

12

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	6350	1			T53	2		T57	1		T61	2
alert_integrity_fail	alert[0x1]	3312	1			T86	5		T48	7		T253	1
alert_integrity_fail	alert[0x2]	2967	1			T53	19		T37	18		T86	2
alert_integrity_fail	alert[0x3]	3894	1			T45	1		T74	2		T55	71
alert_integrity_fail	alert[0x4]	4805	1			T57	1		T307	150		T312	23
alert_integrity_fail	alert[0x5]	6643	1			T64	23		T101	1		T313	3
alert_integrity_fail	alert[0x6]	8211	1			T55	1		T57	5		T35	2
alert_integrity_fail	alert[0x7]	5133	1			T57	6		T26	4		T115	7
alert_integrity_fail	alert[0x8]	7390	1			T53	1		T57	6		T61	1
alert_integrity_fail	alert[0x9]	2204	1			T312	5		T313	79		T67	16
alert_integrity_fail	alert[0xa]	3743	1			T57	10		T87	2		T48	1
alert_integrity_fail	alert[0xb]	5911	1			T12	1		T115	3		T307	19
alert_integrity_fail	alert[0xc]	2272	1			T87	38		T318	72		T319	2
alert_integrity_fail	alert[0xd]	5437	1			T48	6		T252	4		T125	4
alert_integrity_fail	alert[0xe]	4569	1			T48	2		T61	26		T125	10
alert_integrity_fail	alert[0xf]	2819	1			T48	30		T252	6		T307	83
alert_integrity_fail	alert[0x10]	5044	1			T30	9		T32	1		T320	1
alert_integrity_fail	alert[0x11]	5521	1			T12	5		T55	1		T60	1
alert_integrity_fail	alert[0x12]	10056	1			T53	5		T37	1		T61	1
alert_integrity_fail	alert[0x13]	3416	1			T74	9		T307	39		T125	58
alert_integrity_fail	alert[0x14]	2963	1			T57	15		T252	3		T307	24
alert_integrity_fail	alert[0x15]	5688	1			T312	23		T313	60		T67	9
alert_integrity_fail	alert[0x16]	11108	1			T48	436		T33	2		T307	1
alert_integrity_fail	alert[0x17]	8370	1			T35	6		T125	21		T313	69
alert_integrity_fail	alert[0x18]	2727	1			T55	1		T87	9		T48	2
alert_integrity_fail	alert[0x19]	4787	1			T53	1		T55	2		T60	1
alert_integrity_fail	alert[0x1a]	3989	1			T45	29		T87	2		T48	3
alert_integrity_fail	alert[0x1b]	7928	1			T30	31		T33	9		T101	5
alert_integrity_fail	alert[0x1c]	12794	1			T312	107		T141	4		T143	2
alert_integrity_fail	alert[0x1d]	5138	1			T30	8		T48	17		T60	1
alert_integrity_fail	alert[0x1e]	4526	1			T45	17		T48	184		T35	2
alert_integrity_fail	alert[0x1f]	8194	1			T30	2		T55	2		T48	3
alert_integrity_fail	alert[0x20]	10343	1			T30	1		T60	1		T32	2
alert_integrity_fail	alert[0x21]	3359	1			T26	2		T35	49		T312	44
alert_integrity_fail	alert[0x22]	2302	1			T55	1		T87	11		T115	1
alert_integrity_fail	alert[0x23]	1420	1			T45	1		T48	20		T307	23
alert_integrity_fail	alert[0x24]	2716	1			T53	1		T55	3		T32	1
alert_integrity_fail	alert[0x25]	5178	1			T55	21		T86	2		T48	1
alert_integrity_fail	alert[0x26]	5036	1			T61	1		T141	18		T313	34
alert_integrity_fail	alert[0x27]	5870	1			T45	2		T87	1		T307	16
alert_integrity_fail	alert[0x28]	7367	1			T33	19		T312	2		T143	3
alert_integrity_fail	alert[0x29]	5534	1			T53	3		T48	1		T33	96
alert_integrity_fail	alert[0x2a]	1533	1			T87	1		T48	70		T33	1
alert_integrity_fail	alert[0x2b]	1881	1			T312	26		T313	4		T318	10
alert_integrity_fail	alert[0x2c]	3685	1			T87	5		T32	1		T115	3
alert_integrity_fail	alert[0x2d]	4912	1			T48	10		T60	2		T35	1
alert_integrity_fail	alert[0x2e]	2805	1			T87	1		T61	1		T115	1
alert_integrity_fail	alert[0x2f]	13031	1			T87	2		T35	1		T271	7
alert_integrity_fail	alert[0x30]	5930	1			T87	8		T48	28		T307	46
alert_integrity_fail	alert[0x31]	2788	1			T26	74		T35	6		T101	2
alert_integrity_fail	alert[0x32]	1187	1			T312	104		T101	1		T313	54
alert_integrity_fail	alert[0x33]	2115	1			T30	5		T57	1		T87	10
alert_integrity_fail	alert[0x34]	2868	1			T115	4		T252	1		T313	35
alert_integrity_fail	alert[0x35]	4185	1			T45	13		T125	87		T312	8
alert_integrity_fail	alert[0x36]	2610	1			T74	5		T57	6		T33	62
alert_integrity_fail	alert[0x37]	3942	1			T74	2		T57	4		T87	1
alert_integrity_fail	alert[0x38]	7011	1			T87	6		T307	4		T312	523
alert_integrity_fail	alert[0x39]	3900	1			T45	10		T74	3		T61	2
alert_integrity_fail	alert[0x3a]	6410	1			T12	3		T60	13		T115	15
alert_integrity_fail	alert[0x3b]	3983	1			T312	39		T66	1		T101	1
alert_integrity_fail	alert[0x3c]	2840	1			T57	2		T48	16		T307	26
alert_integrity_fail	alert[0x3d]	6545	1			T12	6		T74	1		T307	34
alert_integrity_fail	alert[0x3e]	3446	1			T60	31		T115	5		T252	2
alert_integrity_fail	alert[0x3f]	4504	1			T48	2		T98	32		T60	1
alert_integrity_fail	alert[0x40]	2750	1			T12	1		T45	11		T125	86
alert_ping_fail	alert[0x0]	8	1			T21	1		T321	2		T114	1
alert_ping_fail	alert[0x1]	15	1			T21	1		T136	2		T314	2
alert_ping_fail	alert[0x2]	9	1			T20	1		T36	1		T322	1
alert_ping_fail	alert[0x3]	11	1			T19	1		T136	1		T314	1
alert_ping_fail	alert[0x4]	7	1			T308	1		T315	1		T114	1
alert_ping_fail	alert[0x5]	15	1			T138	1		T294	1		T323	1
alert_ping_fail	alert[0x6]	18	1			T309	1		T317	2		T298	1
alert_ping_fail	alert[0x7]	12	1			T20	1		T138	1		T310	1
alert_ping_fail	alert[0x8]	13	1			T136	1		T317	1		T302	1
alert_ping_fail	alert[0x9]	8	1			T136	1		T138	1		T310	2
alert_ping_fail	alert[0xa]	12	1			T20	1		T317	1		T323	1
alert_ping_fail	alert[0xb]	7	1			T138	1		T324	1		T325	1
alert_ping_fail	alert[0xc]	11	1			T19	1		T311	1		T321	1
alert_ping_fail	alert[0xd]	5	1			T136	1		T111	1		T326	2
alert_ping_fail	alert[0xe]	14	1			T138	1		T310	1		T311	1
alert_ping_fail	alert[0xf]	10	1			T136	1		T138	1		T314	1
alert_ping_fail	alert[0x10]	10	1			T20	1		T21	1		T36	1
alert_ping_fail	alert[0x11]	7	1			T308	1		T315	1		T321	1
alert_ping_fail	alert[0x12]	11	1			T20	1		T138	1		T309	1
alert_ping_fail	alert[0x13]	11	1			T308	1		T316	1		T293	1
alert_ping_fail	alert[0x14]	12	1			T315	1		T294	1		T296	2
alert_ping_fail	alert[0x15]	12	1			T301	1		T327	1		T328	1
alert_ping_fail	alert[0x16]	10	1			T136	1		T138	1		T111	1
alert_ping_fail	alert[0x17]	10	1			T113	1		T329	1		T322	1
alert_ping_fail	alert[0x18]	5	1			T311	1		T316	1		T114	1
alert_ping_fail	alert[0x19]	10	1			T310	1		T309	1		T315	1
alert_ping_fail	alert[0x1a]	16	1			T18	1		T138	2		T311	1
alert_ping_fail	alert[0x1b]	8	1			T310	1		T323	1		T329	1
alert_ping_fail	alert[0x1c]	8	1			T295	1		T329	1		T330	1
alert_ping_fail	alert[0x1d]	14	1			T310	1		T309	2		T315	1
alert_ping_fail	alert[0x1e]	6	1			T136	1		T315	1		T323	1
alert_ping_fail	alert[0x1f]	9	1			T138	1		T114	1		T331	1
alert_ping_fail	alert[0x20]	4	1			T321	1		T322	1		T332	1
alert_ping_fail	alert[0x21]	12	1			T21	1		T138	1		T310	1
alert_ping_fail	alert[0x22]	12	1			T20	2		T136	1		T310	1
alert_ping_fail	alert[0x23]	11	1			T310	1		T323	3		T114	2
alert_ping_fail	alert[0x24]	10	1			T314	1		T317	1		T316	1
alert_ping_fail	alert[0x25]	12	1			T138	2		T36	1		T316	1
alert_ping_fail	alert[0x26]	10	1			T20	1		T315	1		T113	1
alert_ping_fail	alert[0x27]	9	1			T314	1		T36	1		T321	1
alert_ping_fail	alert[0x28]	11	1			T316	1		T315	1		T297	1
alert_ping_fail	alert[0x29]	9	1			T316	1		T315	1		T328	1
alert_ping_fail	alert[0x2a]	11	1			T316	2		T296	2		T321	1
alert_ping_fail	alert[0x2b]	17	1			T20	1		T21	1		T310	1
alert_ping_fail	alert[0x2c]	15	1			T18	1		T19	1		T118	1
alert_ping_fail	alert[0x2d]	11	1			T138	1		T315	1		T323	2
alert_ping_fail	alert[0x2e]	10	1			T20	1		T309	1		T323	1
alert_ping_fail	alert[0x2f]	12	1			T18	1		T21	1		T308	1
alert_ping_fail	alert[0x30]	16	1			T136	1		T138	1		T314	1
alert_ping_fail	alert[0x31]	8	1			T19	1		T317	1		T325	1
alert_ping_fail	alert[0x32]	9	1			T138	1		T316	1		T323	1
alert_ping_fail	alert[0x33]	6	1			T136	1		T333	1		T334	1
alert_ping_fail	alert[0x34]	13	1			T315	1		T113	1		T329	1
alert_ping_fail	alert[0x35]	11	1			T314	1		T317	1		T308	1
alert_ping_fail	alert[0x36]	9	1			T18	1		T20	1		T136	1
alert_ping_fail	alert[0x37]	13	1			T18	1		T19	1		T317	1
alert_ping_fail	alert[0x38]	6	1			T19	1		T138	1		T111	1
alert_ping_fail	alert[0x39]	9	1			T136	2		T317	1		T308	1
alert_ping_fail	alert[0x3a]	3	1			T316	1		T333	1		T335	1
alert_ping_fail	alert[0x3b]	9	1			T309	1		T316	1		T329	1
alert_ping_fail	alert[0x3c]	5	1			T310	1		T315	1		T322	1
alert_ping_fail	alert[0x3d]	12	1			T18	1		T20	1		T317	1
alert_ping_fail	alert[0x3e]	10	1			T138	1		T310	1		T113	1
alert_ping_fail	alert[0x3f]	7	1			T138	1		T315	1		T323	1
alert_ping_fail	alert[0x40]	2	1			T317	1		T336	1		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	125195	1			T45	83		T74	15		T53	30
alert_integrity_fail	class_i[0x1]	50789	1			T12	6		T74	1		T57	12
alert_integrity_fail	class_i[0x2]	78147	1			T12	10		T30	5		T45	1
alert_integrity_fail	class_i[0x3]	67764	1			T30	51		T53	2		T57	14
alert_ping_fail	class_i[0x0]	216	1			T18	1		T21	2		T138	3
alert_ping_fail	class_i[0x1]	171	1			T18	1		T19	2		T20	12
alert_ping_fail	class_i[0x2]	98	1			T18	3		T19	2		T136	13
alert_ping_fail	class_i[0x3]	173	1			T18	1		T19	2		T21	2