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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.99 98.66 97.09 100.00 100.00 99.38 99.60


Total test records in report: 828
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T781 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.3106248814 Sep 18 04:33:57 PM UTC 24 Sep 18 04:34:06 PM UTC 24 253419466 ps
T782 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.1433460006 Sep 18 04:34:05 PM UTC 24 Sep 18 04:34:08 PM UTC 24 6863372 ps
T783 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.3383558655 Sep 18 04:34:05 PM UTC 24 Sep 18 04:34:14 PM UTC 24 293528297 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1465146124 Sep 18 04:30:27 PM UTC 24 Sep 18 04:34:18 PM UTC 24 3054291257 ps
T784 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1074960090 Sep 18 04:34:09 PM UTC 24 Sep 18 04:34:23 PM UTC 24 409162017 ps
T785 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2079049866 Sep 18 04:34:07 PM UTC 24 Sep 18 04:34:24 PM UTC 24 357318124 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.732067736 Sep 18 04:34:25 PM UTC 24 Sep 18 04:34:28 PM UTC 24 9782766 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.1305738379 Sep 18 04:34:19 PM UTC 24 Sep 18 04:34:30 PM UTC 24 43581197 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.3048921544 Sep 18 04:34:29 PM UTC 24 Sep 18 04:34:38 PM UTC 24 51607945 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4228205807 Sep 18 04:34:34 PM UTC 24 Sep 18 04:34:53 PM UTC 24 65673525 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2801185609 Sep 18 04:33:35 PM UTC 24 Sep 18 04:35:06 PM UTC 24 2480460407 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3585067430 Sep 18 04:31:59 PM UTC 24 Sep 18 04:35:20 PM UTC 24 6232661413 ps
T790 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.3363883523 Sep 18 04:35:07 PM UTC 24 Sep 18 04:35:26 PM UTC 24 83879163 ps
T791 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.2163460711 Sep 18 04:35:27 PM UTC 24 Sep 18 04:35:31 PM UTC 24 14759585 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2217570555 Sep 18 04:32:18 PM UTC 24 Sep 18 04:35:41 PM UTC 24 8952565837 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.3014271598 Sep 18 04:35:32 PM UTC 24 Sep 18 04:35:42 PM UTC 24 315411357 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4203356867 Sep 18 04:34:31 PM UTC 24 Sep 18 04:35:46 PM UTC 24 678229650 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.1998424094 Sep 18 04:35:47 PM UTC 24 Sep 18 04:35:51 PM UTC 24 12105363 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1605371006 Sep 18 04:34:18 PM UTC 24 Sep 18 04:35:51 PM UTC 24 1112221511 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.2832593798 Sep 18 04:35:52 PM UTC 24 Sep 18 04:35:55 PM UTC 24 51871386 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.3612751547 Sep 18 04:35:52 PM UTC 24 Sep 18 04:35:55 PM UTC 24 8486423 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2711559471 Sep 18 04:35:42 PM UTC 24 Sep 18 04:35:57 PM UTC 24 411214166 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1052027927 Sep 18 04:35:56 PM UTC 24 Sep 18 04:35:59 PM UTC 24 44382228 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2727293222 Sep 18 04:35:56 PM UTC 24 Sep 18 04:35:59 PM UTC 24 6655079 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.1799448491 Sep 18 04:35:56 PM UTC 24 Sep 18 04:35:59 PM UTC 24 11377533 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3367400699 Sep 18 04:29:28 PM UTC 24 Sep 18 04:36:01 PM UTC 24 9215832250 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.2321671644 Sep 18 04:35:58 PM UTC 24 Sep 18 04:36:02 PM UTC 24 11759973 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2963826006 Sep 18 04:36:00 PM UTC 24 Sep 18 04:36:06 PM UTC 24 7173092 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.2741447827 Sep 18 04:36:00 PM UTC 24 Sep 18 04:36:06 PM UTC 24 10853273 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2842108830 Sep 18 04:36:00 PM UTC 24 Sep 18 04:36:07 PM UTC 24 40354019 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.2744600192 Sep 18 04:36:02 PM UTC 24 Sep 18 04:36:07 PM UTC 24 16278266 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2824671163 Sep 18 04:33:05 PM UTC 24 Sep 18 04:36:07 PM UTC 24 1951877051 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1931125780 Sep 18 04:22:11 PM UTC 24 Sep 18 04:36:09 PM UTC 24 17978561740 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1880378427 Sep 18 04:35:21 PM UTC 24 Sep 18 04:36:10 PM UTC 24 446782343 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2328218824 Sep 18 04:36:07 PM UTC 24 Sep 18 04:36:10 PM UTC 24 12177347 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.3331888120 Sep 18 04:36:08 PM UTC 24 Sep 18 04:36:11 PM UTC 24 7971806 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.920341107 Sep 18 04:36:09 PM UTC 24 Sep 18 04:36:12 PM UTC 24 14640145 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3727179097 Sep 18 04:36:09 PM UTC 24 Sep 18 04:36:13 PM UTC 24 34683456 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.3757578822 Sep 18 04:36:09 PM UTC 24 Sep 18 04:36:13 PM UTC 24 16290343 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.4200004484 Sep 18 04:36:09 PM UTC 24 Sep 18 04:36:13 PM UTC 24 10686375 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.484555424 Sep 18 04:36:09 PM UTC 24 Sep 18 04:36:13 PM UTC 24 7913191 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.285889780 Sep 18 04:36:11 PM UTC 24 Sep 18 04:36:15 PM UTC 24 18915837 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.588005765 Sep 18 04:36:11 PM UTC 24 Sep 18 04:36:15 PM UTC 24 10307957 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.3546991965 Sep 18 04:36:11 PM UTC 24 Sep 18 04:36:16 PM UTC 24 14924671 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2035525428 Sep 18 04:34:24 PM UTC 24 Sep 18 04:36:16 PM UTC 24 2144871061 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.2090924251 Sep 18 04:36:11 PM UTC 24 Sep 18 04:36:17 PM UTC 24 26768574 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.1285253176 Sep 18 04:36:13 PM UTC 24 Sep 18 04:36:17 PM UTC 24 12354568 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.1161157662 Sep 18 04:36:14 PM UTC 24 Sep 18 04:36:17 PM UTC 24 6529880 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.1862423645 Sep 18 04:36:15 PM UTC 24 Sep 18 04:36:18 PM UTC 24 10401131 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.1980899412 Sep 18 04:36:15 PM UTC 24 Sep 18 04:36:18 PM UTC 24 8216053 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.3692405451 Sep 18 04:36:15 PM UTC 24 Sep 18 04:36:18 PM UTC 24 7953730 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.3110764943 Sep 18 04:36:17 PM UTC 24 Sep 18 04:36:19 PM UTC 24 9713008 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.1156236476 Sep 18 04:36:17 PM UTC 24 Sep 18 04:36:20 PM UTC 24 8045477 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.2801752084 Sep 18 04:36:17 PM UTC 24 Sep 18 04:36:20 PM UTC 24 10554633 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3527952076 Sep 18 04:27:57 PM UTC 24 Sep 18 04:36:22 PM UTC 24 29260010615 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3081633521 Sep 18 04:35:42 PM UTC 24 Sep 18 04:36:24 PM UTC 24 531354218 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.646327475 Sep 18 04:27:31 PM UTC 24 Sep 18 04:36:24 PM UTC 24 34242412454 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3300850220 Sep 18 04:32:41 PM UTC 24 Sep 18 04:36:36 PM UTC 24 4566707624 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3593220627 Sep 18 04:33:34 PM UTC 24 Sep 18 04:37:50 PM UTC 24 6581734210 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2927398364 Sep 18 04:34:54 PM UTC 24 Sep 18 04:38:13 PM UTC 24 2290968411 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3914055718 Sep 18 04:26:52 PM UTC 24 Sep 18 04:38:39 PM UTC 24 17781027855 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1630829806 Sep 18 04:29:07 PM UTC 24 Sep 18 04:38:52 PM UTC 24 6381726794 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3808861467 Sep 18 04:33:25 PM UTC 24 Sep 18 04:39:20 PM UTC 24 8371771376 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1593116287 Sep 18 04:31:08 PM UTC 24 Sep 18 04:39:21 PM UTC 24 26898838407 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2951277788 Sep 18 04:33:46 PM UTC 24 Sep 18 04:39:45 PM UTC 24 8631213103 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2505260916 Sep 18 04:33:47 PM UTC 24 Sep 18 04:40:09 PM UTC 24 5072042340 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3526956268 Sep 18 04:23:13 PM UTC 24 Sep 18 04:40:19 PM UTC 24 174191652604 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2538501338 Sep 18 04:32:18 PM UTC 24 Sep 18 04:40:44 PM UTC 24 27611276959 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1975813342 Sep 18 04:34:15 PM UTC 24 Sep 18 04:41:12 PM UTC 24 9010854634 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2062764725 Sep 18 04:31:34 PM UTC 24 Sep 18 04:41:20 PM UTC 24 68508416311 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.275921439 Sep 18 04:30:45 PM UTC 24 Sep 18 04:41:50 PM UTC 24 10370430001 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2270717695 Sep 18 04:30:24 PM UTC 24 Sep 18 04:42:02 PM UTC 24 5240424296 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2159014964 Sep 18 04:25:35 PM UTC 24 Sep 18 04:42:04 PM UTC 24 119770646256 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3917497250 Sep 18 04:29:59 PM UTC 24 Sep 18 04:45:12 PM UTC 24 18654290383 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.677417706 Sep 18 04:34:38 PM UTC 24 Sep 18 04:45:22 PM UTC 24 17946409372 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.99899474 Sep 18 04:31:57 PM UTC 24 Sep 18 04:50:01 PM UTC 24 154719379600 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3979640763 Sep 18 04:33:02 PM UTC 24 Sep 18 04:51:45 PM UTC 24 24895662145 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2476238172 Sep 18 04:32:41 PM UTC 24 Sep 18 04:55:03 PM UTC 24 153745328054 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.1595618684
Short name T12
Test name
Test status
Simulation time 1297208889 ps
CPU time 21.08 seconds
Started Sep 18 02:47:58 PM UTC 24
Finished Sep 18 02:48:20 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595618684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1595618684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all_with_rand_reset.1277012086
Short name T26
Test name
Test status
Simulation time 4010309884 ps
CPU time 257.63 seconds
Started Sep 18 02:48:38 PM UTC 24
Finished Sep 18 02:52:59 PM UTC 24
Peak memory 283148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1277012086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.al
ert_handler_stress_all_with_rand_reset.1277012086
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.4070625829
Short name T9
Test name
Test status
Simulation time 1030604841 ps
CPU time 17.72 seconds
Started Sep 18 02:49:24 PM UTC 24
Finished Sep 18 02:49:45 PM UTC 24
Peak memory 292808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070625829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4070625829
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.1746906552
Short name T30
Test name
Test status
Simulation time 843500961 ps
CPU time 71.33 seconds
Started Sep 18 02:48:19 PM UTC 24
Finished Sep 18 02:49:32 PM UTC 24
Peak memory 260436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746906552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1746906552
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.718278272
Short name T4
Test name
Test status
Simulation time 157658888 ps
CPU time 9.74 seconds
Started Sep 18 02:48:07 PM UTC 24
Finished Sep 18 02:48:17 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718278272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.718278272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3598010273
Short name T219
Test name
Test status
Simulation time 4747194020 ps
CPU time 67.04 seconds
Started Sep 18 04:24:14 PM UTC 24
Finished Sep 18 04:25:22 PM UTC 24
Peak memory 250596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598010273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3598010273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.3352277692
Short name T37
Test name
Test status
Simulation time 3545626451 ps
CPU time 255.44 seconds
Started Sep 18 02:49:22 PM UTC 24
Finished Sep 18 02:53:41 PM UTC 24
Peak memory 277004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3352277692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.al
ert_handler_stress_all_with_rand_reset.3352277692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all_with_rand_reset.1558792979
Short name T35
Test name
Test status
Simulation time 4192899070 ps
CPU time 201.71 seconds
Started Sep 18 03:00:15 PM UTC 24
Finished Sep 18 03:03:40 PM UTC 24
Peak memory 277008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1558792979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.a
lert_handler_stress_all_with_rand_reset.1558792979
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all_with_rand_reset.3708987214
Short name T344
Test name
Test status
Simulation time 5967550072 ps
CPU time 330.79 seconds
Started Sep 18 03:40:40 PM UTC 24
Finished Sep 18 03:46:15 PM UTC 24
Peak memory 281496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3708987214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.a
lert_handler_stress_all_with_rand_reset.3708987214
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.3062354987
Short name T43
Test name
Test status
Simulation time 5195326660 ps
CPU time 64.16 seconds
Started Sep 18 02:52:51 PM UTC 24
Finished Sep 18 02:53:57 PM UTC 24
Peak memory 267000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062354987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3062354987
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3593220627
Short name T191
Test name
Test status
Simulation time 6581734210 ps
CPU time 252.3 seconds
Started Sep 18 04:33:34 PM UTC 24
Finished Sep 18 04:37:50 PM UTC 24
Peak memory 277740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593220627 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.3593220627
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.884392991
Short name T152
Test name
Test status
Simulation time 78751115271 ps
CPU time 1896.34 seconds
Started Sep 18 02:57:47 PM UTC 24
Finished Sep 18 03:29:45 PM UTC 24
Peak memory 299468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884392991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.884392991
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.1900189221
Short name T296
Test name
Test status
Simulation time 147627956839 ps
CPU time 1731.32 seconds
Started Sep 18 02:48:03 PM UTC 24
Finished Sep 18 03:17:14 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900189221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1900189221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.1614169295
Short name T318
Test name
Test status
Simulation time 367259737007 ps
CPU time 1584.54 seconds
Started Sep 18 02:48:57 PM UTC 24
Finished Sep 18 03:15:40 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614169295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1614169295
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3526956268
Short name T210
Test name
Test status
Simulation time 174191652604 ps
CPU time 1013.47 seconds
Started Sep 18 04:23:13 PM UTC 24
Finished Sep 18 04:40:19 PM UTC 24
Peak memory 277536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526956268 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shado
w_reg_errors_with_csr_rw.3526956268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.880780441
Short name T182
Test name
Test status
Simulation time 3227055661 ps
CPU time 219.73 seconds
Started Sep 18 04:25:42 PM UTC 24
Finished Sep 18 04:29:25 PM UTC 24
Peak memory 281640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880780441 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.880780441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.3750104100
Short name T118
Test name
Test status
Simulation time 49856348010 ps
CPU time 152.22 seconds
Started Sep 18 03:22:38 PM UTC 24
Finished Sep 18 03:25:13 PM UTC 24
Peak memory 260640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750104100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3750104100
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.232201092
Short name T630
Test name
Test status
Simulation time 4878010027 ps
CPU time 211.26 seconds
Started Sep 18 04:06:44 PM UTC 24
Finished Sep 18 04:10:18 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232201092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.232201092
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.2226690549
Short name T138
Test name
Test status
Simulation time 63957031866 ps
CPU time 691.53 seconds
Started Sep 18 02:51:31 PM UTC 24
Finished Sep 18 03:03:11 PM UTC 24
Peak memory 260568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226690549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2226690549
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.275921439
Short name T212
Test name
Test status
Simulation time 10370430001 ps
CPU time 656.51 seconds
Started Sep 18 04:30:45 PM UTC 24
Finished Sep 18 04:41:50 PM UTC 24
Peak memory 283680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275921439 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow
_reg_errors_with_csr_rw.275921439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.2942338893
Short name T300
Test name
Test status
Simulation time 177272627772 ps
CPU time 2354.86 seconds
Started Sep 18 02:49:49 PM UTC 24
Finished Sep 18 03:29:29 PM UTC 24
Peak memory 298028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942338893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2942338893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all_with_rand_reset.1692160817
Short name T55
Test name
Test status
Simulation time 10552182053 ps
CPU time 240.02 seconds
Started Sep 18 02:48:11 PM UTC 24
Finished Sep 18 02:52:15 PM UTC 24
Peak memory 281428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1692160817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.al
ert_handler_stress_all_with_rand_reset.1692160817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.2778320480
Short name T383
Test name
Test status
Simulation time 9340467 ps
CPU time 2.54 seconds
Started Sep 18 04:27:08 PM UTC 24
Finished Sep 18 04:27:12 PM UTC 24
Peak memory 248616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778320480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2778320480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.1535459429
Short name T316
Test name
Test status
Simulation time 25965342845 ps
CPU time 649.29 seconds
Started Sep 18 02:55:29 PM UTC 24
Finished Sep 18 03:06:26 PM UTC 24
Peak memory 260896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535459429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1535459429
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2505260916
Short name T200
Test name
Test status
Simulation time 5072042340 ps
CPU time 376.44 seconds
Started Sep 18 04:33:47 PM UTC 24
Finished Sep 18 04:40:09 PM UTC 24
Peak memory 277612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505260916 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.2505260916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.2895688067
Short name T363
Test name
Test status
Simulation time 693217478478 ps
CPU time 3404.73 seconds
Started Sep 18 02:48:25 PM UTC 24
Finished Sep 18 03:45:48 PM UTC 24
Peak memory 302052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895688067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2895688067
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.2355202285
Short name T143
Test name
Test status
Simulation time 48068614757 ps
CPU time 1462.61 seconds
Started Sep 18 02:48:33 PM UTC 24
Finished Sep 18 03:13:12 PM UTC 24
Peak memory 283228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355202285 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.2355202285
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.99899474
Short name T828
Test name
Test status
Simulation time 154719379600 ps
CPU time 1071.51 seconds
Started Sep 18 04:31:57 PM UTC 24
Finished Sep 18 04:50:01 PM UTC 24
Peak memory 277744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99899474 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow
_reg_errors_with_csr_rw.99899474
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.1810451534
Short name T95
Test name
Test status
Simulation time 4116874891 ps
CPU time 69.14 seconds
Started Sep 18 02:48:56 PM UTC 24
Finished Sep 18 02:50:06 PM UTC 24
Peak memory 266932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810451534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1810451534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.4049881726
Short name T61
Test name
Test status
Simulation time 10043045087 ps
CPU time 129.93 seconds
Started Sep 18 02:55:37 PM UTC 24
Finished Sep 18 02:57:50 PM UTC 24
Peak memory 266972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049881726 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.4049881726
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.3459696976
Short name T20
Test name
Test status
Simulation time 8933054666 ps
CPU time 356.81 seconds
Started Sep 18 02:48:22 PM UTC 24
Finished Sep 18 02:54:23 PM UTC 24
Peak memory 266976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459696976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3459696976
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2159014964
Short name T213
Test name
Test status
Simulation time 119770646256 ps
CPU time 977.38 seconds
Started Sep 18 04:25:35 PM UTC 24
Finished Sep 18 04:42:04 PM UTC 24
Peak memory 277676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159014964 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shado
w_reg_errors_with_csr_rw.2159014964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.878942353
Short name T173
Test name
Test status
Simulation time 348749443 ps
CPU time 9.64 seconds
Started Sep 18 04:23:00 PM UTC 24
Finished Sep 18 04:23:10 PM UTC 24
Peak memory 248476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878942353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.878942353
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.2275472246
Short name T49
Test name
Test status
Simulation time 1610129588 ps
CPU time 32.78 seconds
Started Sep 18 02:50:12 PM UTC 24
Finished Sep 18 02:50:46 PM UTC 24
Peak memory 292808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275472246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2275472246
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.1976592242
Short name T315
Test name
Test status
Simulation time 45624354834 ps
CPU time 448.26 seconds
Started Sep 18 02:59:10 PM UTC 24
Finished Sep 18 03:06:44 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976592242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1976592242
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.3580989840
Short name T45
Test name
Test status
Simulation time 280493186 ps
CPU time 39.64 seconds
Started Sep 18 02:48:56 PM UTC 24
Finished Sep 18 02:49:37 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580989840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3580989840
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2062764725
Short name T217
Test name
Test status
Simulation time 68508416311 ps
CPU time 578.17 seconds
Started Sep 18 04:31:34 PM UTC 24
Finished Sep 18 04:41:20 PM UTC 24
Peak memory 277536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062764725 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shad
ow_reg_errors_with_csr_rw.2062764725
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.1447422234
Short name T122
Test name
Test status
Simulation time 103831010430 ps
CPU time 1547.06 seconds
Started Sep 18 02:56:36 PM UTC 24
Finished Sep 18 03:22:41 PM UTC 24
Peak memory 276948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447422234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1447422234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.219301830
Short name T124
Test name
Test status
Simulation time 34127932387 ps
CPU time 2269.02 seconds
Started Sep 18 02:59:49 PM UTC 24
Finished Sep 18 03:38:05 PM UTC 24
Peak memory 300936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219301830 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.219301830
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.3708320943
Short name T269
Test name
Test status
Simulation time 74074581122 ps
CPU time 4323.55 seconds
Started Sep 18 02:50:57 PM UTC 24
Finished Sep 18 04:03:48 PM UTC 24
Peak memory 318432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708320943 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.3708320943
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1069841246
Short name T185
Test name
Test status
Simulation time 2331829622 ps
CPU time 150.49 seconds
Started Sep 18 04:30:04 PM UTC 24
Finished Sep 18 04:32:37 PM UTC 24
Peak memory 277740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069841246 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.1069841246
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.1651930601
Short name T221
Test name
Test status
Simulation time 10548362 ps
CPU time 2.54 seconds
Started Sep 18 04:22:57 PM UTC 24
Finished Sep 18 04:23:01 PM UTC 24
Peak memory 248484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651930601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1651930601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.1603762843
Short name T321
Test name
Test status
Simulation time 23732471714 ps
CPU time 551.29 seconds
Started Sep 18 03:19:16 PM UTC 24
Finished Sep 18 03:28:34 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603762843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1603762843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.2151845695
Short name T317
Test name
Test status
Simulation time 8317287461 ps
CPU time 351.53 seconds
Started Sep 18 02:54:14 PM UTC 24
Finished Sep 18 03:00:10 PM UTC 24
Peak memory 260832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151845695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2151845695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.904380798
Short name T291
Test name
Test status
Simulation time 43010977671 ps
CPU time 2477.09 seconds
Started Sep 18 03:38:11 PM UTC 24
Finished Sep 18 04:19:56 PM UTC 24
Peak memory 300000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904380798 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.904380798
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.3273097117
Short name T371
Test name
Test status
Simulation time 102953265193 ps
CPU time 1504.89 seconds
Started Sep 18 03:26:09 PM UTC 24
Finished Sep 18 03:51:31 PM UTC 24
Peak memory 283096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273097117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3273097117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.1730535469
Short name T135
Test name
Test status
Simulation time 86473406250 ps
CPU time 2318.8 seconds
Started Sep 18 03:23:00 PM UTC 24
Finished Sep 18 04:02:07 PM UTC 24
Peak memory 314340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730535469 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.1730535469
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1975813342
Short name T211
Test name
Test status
Simulation time 9010854634 ps
CPU time 411.05 seconds
Started Sep 18 04:34:15 PM UTC 24
Finished Sep 18 04:41:12 PM UTC 24
Peak memory 277536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975813342 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shad
ow_reg_errors_with_csr_rw.1975813342
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.769963457
Short name T346
Test name
Test status
Simulation time 27777411151 ps
CPU time 1928.82 seconds
Started Sep 18 02:47:59 PM UTC 24
Finished Sep 18 03:20:31 PM UTC 24
Peak memory 300000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769963457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.769963457
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.4196652888
Short name T224
Test name
Test status
Simulation time 204650369 ps
CPU time 2.94 seconds
Started Sep 18 04:30:39 PM UTC 24
Finished Sep 18 04:30:43 PM UTC 24
Peak memory 248484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196652888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.4196652888
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.55647871
Short name T167
Test name
Test status
Simulation time 8169783820 ps
CPU time 87.24 seconds
Started Sep 18 04:26:02 PM UTC 24
Finished Sep 18 04:27:31 PM UTC 24
Peak memory 248612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55647871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.55647871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.2374584683
Short name T263
Test name
Test status
Simulation time 19081613638 ps
CPU time 1250.14 seconds
Started Sep 18 03:26:11 PM UTC 24
Finished Sep 18 03:47:16 PM UTC 24
Peak memory 299476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374584683 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.2374584683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1931125780
Short name T192
Test name
Test status
Simulation time 17978561740 ps
CPU time 827.63 seconds
Started Sep 18 04:22:11 PM UTC 24
Finished Sep 18 04:36:09 PM UTC 24
Peak memory 283756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931125780 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shado
w_reg_errors_with_csr_rw.1931125780
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.4125315545
Short name T370
Test name
Test status
Simulation time 65934032445 ps
CPU time 2108.62 seconds
Started Sep 18 03:29:29 PM UTC 24
Finished Sep 18 04:05:01 PM UTC 24
Peak memory 296176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125315545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.4125315545
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.1616273548
Short name T339
Test name
Test status
Simulation time 288127108859 ps
CPU time 2660.75 seconds
Started Sep 18 03:49:24 PM UTC 24
Finished Sep 18 04:34:15 PM UTC 24
Peak memory 302316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616273548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1616273548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.1708455226
Short name T575
Test name
Test status
Simulation time 12787106849 ps
CPU time 648.93 seconds
Started Sep 18 03:49:05 PM UTC 24
Finished Sep 18 04:00:01 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708455226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1708455226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.3722618966
Short name T273
Test name
Test status
Simulation time 56628966006 ps
CPU time 2070.51 seconds
Started Sep 18 03:56:44 PM UTC 24
Finished Sep 18 04:31:39 PM UTC 24
Peak memory 297500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722618966 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.3722618966
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.617377865
Short name T289
Test name
Test status
Simulation time 68643936979 ps
CPU time 1482.99 seconds
Started Sep 18 04:05:15 PM UTC 24
Finished Sep 18 04:30:16 PM UTC 24
Peak memory 299548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617377865 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.617377865
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.318343555
Short name T58
Test name
Test status
Simulation time 1533423081 ps
CPU time 57.4 seconds
Started Sep 18 02:52:53 PM UTC 24
Finished Sep 18 02:53:52 PM UTC 24
Peak memory 266572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318343555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.318343555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all_with_rand_reset.3392332197
Short name T110
Test name
Test status
Simulation time 3882350408 ps
CPU time 517.58 seconds
Started Sep 18 03:19:48 PM UTC 24
Finished Sep 18 03:28:32 PM UTC 24
Peak memory 283224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3392332197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.a
lert_handler_stress_all_with_rand_reset.3392332197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.1155320429
Short name T14
Test name
Test status
Simulation time 210942862 ps
CPU time 7.22 seconds
Started Sep 18 02:48:11 PM UTC 24
Finished Sep 18 02:48:19 PM UTC 24
Peak memory 260968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155320429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1155320429
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3914055718
Short name T204
Test name
Test status
Simulation time 17781027855 ps
CPU time 697.42 seconds
Started Sep 18 04:26:52 PM UTC 24
Finished Sep 18 04:38:39 PM UTC 24
Peak memory 277536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914055718 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado
w_reg_errors_with_csr_rw.3914055718
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.560827715
Short name T266
Test name
Test status
Simulation time 1748340417 ps
CPU time 72.87 seconds
Started Sep 18 03:22:22 PM UTC 24
Finished Sep 18 03:23:37 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560827715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.560827715
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.2716771916
Short name T27
Test name
Test status
Simulation time 219852358 ps
CPU time 6.02 seconds
Started Sep 18 02:48:36 PM UTC 24
Finished Sep 18 02:48:43 PM UTC 24
Peak memory 260772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716771916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2716771916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.3344867385
Short name T89
Test name
Test status
Simulation time 123031697 ps
CPU time 4.93 seconds
Started Sep 18 02:49:19 PM UTC 24
Finished Sep 18 02:49:25 PM UTC 24
Peak memory 260772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344867385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3344867385
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.420141491
Short name T244
Test name
Test status
Simulation time 94854102 ps
CPU time 4.34 seconds
Started Sep 18 03:06:04 PM UTC 24
Finished Sep 18 03:06:09 PM UTC 24
Peak memory 260704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420141491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.420141491
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.1433460006
Short name T782
Test name
Test status
Simulation time 6863372 ps
CPU time 1.78 seconds
Started Sep 18 04:34:05 PM UTC 24
Finished Sep 18 04:34:08 PM UTC 24
Peak memory 246792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433460006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1433460006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.3876510390
Short name T299
Test name
Test status
Simulation time 22795747887 ps
CPU time 1448.97 seconds
Started Sep 18 03:01:40 PM UTC 24
Finished Sep 18 03:26:07 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876510390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3876510390
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.1066208988
Short name T281
Test name
Test status
Simulation time 24367206287 ps
CPU time 2291.73 seconds
Started Sep 18 04:13:59 PM UTC 24
Finished Sep 18 04:52:39 PM UTC 24
Peak memory 316388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066208988 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.1066208988
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.624442369
Short name T57
Test name
Test status
Simulation time 1669223899 ps
CPU time 38.14 seconds
Started Sep 18 02:52:10 PM UTC 24
Finished Sep 18 02:52:50 PM UTC 24
Peak memory 266652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624442369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.624442369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3879621243
Short name T189
Test name
Test status
Simulation time 1736606233 ps
CPU time 116.87 seconds
Started Sep 18 04:31:36 PM UTC 24
Finished Sep 18 04:33:35 PM UTC 24
Peak memory 277476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879621243 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.3879621243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2927398364
Short name T195
Test name
Test status
Simulation time 2290968411 ps
CPU time 196.63 seconds
Started Sep 18 04:34:54 PM UTC 24
Finished Sep 18 04:38:13 PM UTC 24
Peak memory 277740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927398364 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.2927398364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2475455191
Short name T225
Test name
Test status
Simulation time 4368689111 ps
CPU time 94.12 seconds
Started Sep 18 04:29:19 PM UTC 24
Finished Sep 18 04:30:55 PM UTC 24
Peak memory 250800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475455191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2475455191
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3367400699
Short name T199
Test name
Test status
Simulation time 9215832250 ps
CPU time 386.95 seconds
Started Sep 18 04:29:28 PM UTC 24
Finished Sep 18 04:36:01 PM UTC 24
Peak memory 277540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367400699 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shado
w_reg_errors_with_csr_rw.3367400699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.771048026
Short name T236
Test name
Test status
Simulation time 85397428 ps
CPU time 9.09 seconds
Started Sep 18 04:30:07 PM UTC 24
Finished Sep 18 04:30:18 PM UTC 24
Peak memory 248480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771048026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.771048026
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.2118265059
Short name T306
Test name
Test status
Simulation time 107381866556 ps
CPU time 1821.95 seconds
Started Sep 18 02:48:05 PM UTC 24
Finished Sep 18 03:18:49 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118265059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2118265059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.4193372912
Short name T341
Test name
Test status
Simulation time 213687482130 ps
CPU time 3573.51 seconds
Started Sep 18 02:48:10 PM UTC 24
Finished Sep 18 03:48:24 PM UTC 24
Peak memory 302124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193372912 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.4193372912
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.2345702475
Short name T98
Test name
Test status
Simulation time 332942618 ps
CPU time 10.24 seconds
Started Sep 18 02:56:22 PM UTC 24
Finished Sep 18 02:56:33 PM UTC 24
Peak memory 260500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345702475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2345702475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.1628917269
Short name T295
Test name
Test status
Simulation time 12845150897 ps
CPU time 917.45 seconds
Started Sep 18 02:59:17 PM UTC 24
Finished Sep 18 03:14:46 PM UTC 24
Peak memory 283164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628917269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1628917269
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.2680337208
Short name T267
Test name
Test status
Simulation time 53834371521 ps
CPU time 3208.53 seconds
Started Sep 18 03:02:04 PM UTC 24
Finished Sep 18 03:56:07 PM UTC 24
Peak memory 312292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680337208 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.2680337208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.4250086479
Short name T132
Test name
Test status
Simulation time 35138908384 ps
CPU time 2375.29 seconds
Started Sep 18 03:09:43 PM UTC 24
Finished Sep 18 03:49:45 PM UTC 24
Peak memory 302052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250086479 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.4250086479
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.1320667174
Short name T348
Test name
Test status
Simulation time 99806280858 ps
CPU time 2168.12 seconds
Started Sep 18 03:15:03 PM UTC 24
Finished Sep 18 03:51:38 PM UTC 24
Peak memory 314340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320667174 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.1320667174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.1687659376
Short name T367
Test name
Test status
Simulation time 180204933283 ps
CPU time 2753.2 seconds
Started Sep 18 03:16:33 PM UTC 24
Finished Sep 18 04:02:56 PM UTC 24
Peak memory 302052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687659376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1687659376
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.2016873178
Short name T277
Test name
Test status
Simulation time 240276213611 ps
CPU time 3147.39 seconds
Started Sep 18 03:21:31 PM UTC 24
Finished Sep 18 04:14:33 PM UTC 24
Peak memory 312292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016873178 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.2016873178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.3010366004
Short name T149
Test name
Test status
Simulation time 15302215441 ps
CPU time 1785.72 seconds
Started Sep 18 03:45:43 PM UTC 24
Finished Sep 18 04:15:50 PM UTC 24
Peak memory 318436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010366004 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.3010366004
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.1886826553
Short name T338
Test name
Test status
Simulation time 4801428641 ps
CPU time 209.83 seconds
Started Sep 18 03:52:44 PM UTC 24
Finished Sep 18 03:56:17 PM UTC 24
Peak memory 260568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886826553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1886826553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.3158933684
Short name T272
Test name
Test status
Simulation time 3917138799 ps
CPU time 75.55 seconds
Started Sep 18 03:56:02 PM UTC 24
Finished Sep 18 03:57:20 PM UTC 24
Peak memory 266708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158933684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3158933684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all_with_rand_reset.1953607739
Short name T286
Test name
Test status
Simulation time 3831822392 ps
CPU time 479.81 seconds
Started Sep 18 03:58:20 PM UTC 24
Finished Sep 18 04:06:26 PM UTC 24
Peak memory 283152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1953607739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.a
lert_handler_stress_all_with_rand_reset.1953607739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.1123646963
Short name T53
Test name
Test status
Simulation time 1011335429 ps
CPU time 62.27 seconds
Started Sep 18 02:50:31 PM UTC 24
Finished Sep 18 02:51:35 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123646963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1123646963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.3186098590
Short name T276
Test name
Test status
Simulation time 290854147 ps
CPU time 31.32 seconds
Started Sep 18 04:08:25 PM UTC 24
Finished Sep 18 04:08:58 PM UTC 24
Peak memory 260692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186098590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3186098590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.3566290025
Short name T275
Test name
Test status
Simulation time 238406659 ps
CPU time 24.96 seconds
Started Sep 18 04:12:55 PM UTC 24
Finished Sep 18 04:13:21 PM UTC 24
Peak memory 260756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566290025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3566290025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.1449295500
Short name T360
Test name
Test status
Simulation time 29324328016 ps
CPU time 1925.92 seconds
Started Sep 18 04:20:44 PM UTC 24
Finished Sep 18 04:53:12 PM UTC 24
Peak memory 295460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449295500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1449295500
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3300850220
Short name T196
Test name
Test status
Simulation time 4566707624 ps
CPU time 230.83 seconds
Started Sep 18 04:32:41 PM UTC 24
Finished Sep 18 04:36:36 PM UTC 24
Peak memory 277540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300850220 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.3300850220
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3596614552
Short name T228
Test name
Test status
Simulation time 988988586 ps
CPU time 46.9 seconds
Started Sep 18 04:33:10 PM UTC 24
Finished Sep 18 04:33:59 PM UTC 24
Peak memory 258716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596614552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3596614552
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2824671163
Short name T202
Test name
Test status
Simulation time 1951877051 ps
CPU time 178.45 seconds
Started Sep 18 04:33:05 PM UTC 24
Finished Sep 18 04:36:07 PM UTC 24
Peak memory 267308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824671163 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.2824671163
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1687522348
Short name T227
Test name
Test status
Simulation time 183099881 ps
CPU time 4.26 seconds
Started Sep 18 04:31:22 PM UTC 24
Finished Sep 18 04:31:28 PM UTC 24
Peak memory 250596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687522348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1687522348
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3772706655
Short name T223
Test name
Test status
Simulation time 4288186273 ps
CPU time 51.16 seconds
Started Sep 18 04:30:56 PM UTC 24
Finished Sep 18 04:31:49 PM UTC 24
Peak memory 250596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772706655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3772706655
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.2022920249
Short name T2
Test name
Test status
Simulation time 447891678 ps
CPU time 16.02 seconds
Started Sep 18 02:47:53 PM UTC 24
Finished Sep 18 02:48:10 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022920249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2022920249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4047118153
Short name T180
Test name
Test status
Simulation time 822056815 ps
CPU time 168.58 seconds
Started Sep 18 04:22:13 PM UTC 24
Finished Sep 18 04:25:05 PM UTC 24
Peak memory 277472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047118153 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.4047118153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2221754454
Short name T226
Test name
Test status
Simulation time 78115835 ps
CPU time 7.09 seconds
Started Sep 18 04:32:48 PM UTC 24
Finished Sep 18 04:32:57 PM UTC 24
Peak memory 248548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221754454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2221754454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.685392631
Short name T220
Test name
Test status
Simulation time 211684708 ps
CPU time 6.44 seconds
Started Sep 18 04:25:48 PM UTC 24
Finished Sep 18 04:25:55 PM UTC 24
Peak memory 248476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685392631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.685392631
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.731741024
Short name T218
Test name
Test status
Simulation time 34368653 ps
CPU time 3.66 seconds
Started Sep 18 04:22:54 PM UTC 24
Finished Sep 18 04:22:59 PM UTC 24
Peak memory 248548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731741024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.731741024
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3555388744
Short name T234
Test name
Test status
Simulation time 2090307519 ps
CPU time 93.08 seconds
Started Sep 18 04:32:01 PM UTC 24
Finished Sep 18 04:33:36 PM UTC 24
Peak memory 250724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555388744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3555388744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3765031336
Short name T229
Test name
Test status
Simulation time 612896566 ps
CPU time 34.44 seconds
Started Sep 18 04:32:24 PM UTC 24
Finished Sep 18 04:33:00 PM UTC 24
Peak memory 250596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765031336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3765031336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2035525428
Short name T231
Test name
Test status
Simulation time 2144871061 ps
CPU time 109.73 seconds
Started Sep 18 04:34:24 PM UTC 24
Finished Sep 18 04:36:16 PM UTC 24
Peak memory 258724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035525428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2035525428
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.206588357
Short name T232
Test name
Test status
Simulation time 454253662 ps
CPU time 53.92 seconds
Started Sep 18 04:27:07 PM UTC 24
Finished Sep 18 04:28:02 PM UTC 24
Peak memory 248480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206588357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.206588357
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.3760489233
Short name T42
Test name
Test status
Simulation time 1989702628 ps
CPU time 57.84 seconds
Started Sep 18 04:18:01 PM UTC 24
Finished Sep 18 04:19:01 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760489233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3760489233
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1927373074
Short name T172
Test name
Test status
Simulation time 6504897336 ps
CPU time 338.14 seconds
Started Sep 18 04:23:03 PM UTC 24
Finished Sep 18 04:28:46 PM UTC 24
Peak memory 250792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927373074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1927373074
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3173655610
Short name T755
Test name
Test status
Simulation time 9189855838 ps
CPU time 553.33 seconds
Started Sep 18 04:23:02 PM UTC 24
Finished Sep 18 04:32:22 PM UTC 24
Peak memory 250788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173655610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3173655610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2848223015
Short name T163
Test name
Test status
Simulation time 50164232 ps
CPU time 12.2 seconds
Started Sep 18 04:22:58 PM UTC 24
Finished Sep 18 04:23:11 PM UTC 24
Peak memory 260768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848223015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2848223015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.825225823
Short name T233
Test name
Test status
Simulation time 194618367 ps
CPU time 27.67 seconds
Started Sep 18 04:23:11 PM UTC 24
Finished Sep 18 04:23:41 PM UTC 24
Peak memory 260828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825225823 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_r
w_with_rand_reset.825225823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2648436468
Short name T174
Test name
Test status
Simulation time 1079614742 ps
CPU time 18.7 seconds
Started Sep 18 04:23:11 PM UTC 24
Finished Sep 18 04:23:31 PM UTC 24
Peak memory 258984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648436468 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.2648436468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.3277989942
Short name T257
Test name
Test status
Simulation time 289371935 ps
CPU time 31.04 seconds
Started Sep 18 04:22:24 PM UTC 24
Finished Sep 18 04:22:57 PM UTC 24
Peak memory 260892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277989942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3277989942
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.492985409
Short name T166
Test name
Test status
Simulation time 6797684551 ps
CPU time 121.36 seconds
Started Sep 18 04:24:51 PM UTC 24
Finished Sep 18 04:26:55 PM UTC 24
Peak memory 250588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492985409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.492985409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.319888870
Short name T771
Test name
Test status
Simulation time 5777483547 ps
CPU time 515.98 seconds
Started Sep 18 04:24:49 PM UTC 24
Finished Sep 18 04:33:33 PM UTC 24
Peak memory 248540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319888870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.319888870
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2940288168
Short name T177
Test name
Test status
Simulation time 192533962 ps
CPU time 16.37 seconds
Started Sep 18 04:24:23 PM UTC 24
Finished Sep 18 04:24:41 PM UTC 24
Peak memory 260840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940288168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2940288168
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.572001633
Short name T390
Test name
Test status
Simulation time 89270092 ps
CPU time 8.95 seconds
Started Sep 18 04:25:24 PM UTC 24
Finished Sep 18 04:25:34 PM UTC 24
Peak memory 267240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572001633 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_r
w_with_rand_reset.572001633
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.1634018951
Short name T178
Test name
Test status
Simulation time 126696638 ps
CPU time 5.69 seconds
Started Sep 18 04:24:41 PM UTC 24
Finished Sep 18 04:24:48 PM UTC 24
Peak memory 250728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634018951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1634018951
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.1614143423
Short name T222
Test name
Test status
Simulation time 17607150 ps
CPU time 2.39 seconds
Started Sep 18 04:24:19 PM UTC 24
Finished Sep 18 04:24:22 PM UTC 24
Peak memory 246364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614143423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1614143423
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3282718892
Short name T164
Test name
Test status
Simulation time 1393053956 ps
CPU time 37.91 seconds
Started Sep 18 04:25:06 PM UTC 24
Finished Sep 18 04:25:45 PM UTC 24
Peak memory 258716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282718892 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.3282718892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1124587648
Short name T179
Test name
Test status
Simulation time 757315457 ps
CPU time 75.49 seconds
Started Sep 18 04:23:32 PM UTC 24
Finished Sep 18 04:24:50 PM UTC 24
Peak memory 277548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124587648 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.1124587648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.36421574
Short name T255
Test name
Test status
Simulation time 264599207 ps
CPU time 29.98 seconds
Started Sep 18 04:23:42 PM UTC 24
Finished Sep 18 04:24:13 PM UTC 24
Peak memory 264940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36421574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.36421574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2924574311
Short name T745
Test name
Test status
Simulation time 130504497 ps
CPU time 8.24 seconds
Started Sep 18 04:31:29 PM UTC 24
Finished Sep 18 04:31:38 PM UTC 24
Peak memory 266972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924574311 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem
_rw_with_rand_reset.2924574311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.1397481219
Short name T727
Test name
Test status
Simulation time 34298660 ps
CPU time 7.09 seconds
Started Sep 18 04:31:24 PM UTC 24
Finished Sep 18 04:31:33 PM UTC 24
Peak memory 248544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397481219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1397481219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.3615648205
Short name T743
Test name
Test status
Simulation time 20467253 ps
CPU time 1.66 seconds
Started Sep 18 04:31:24 PM UTC 24
Finished Sep 18 04:31:27 PM UTC 24
Peak memory 246920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615648205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3615648205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.931061826
Short name T748
Test name
Test status
Simulation time 281657368 ps
CPU time 28.66 seconds
Started Sep 18 04:31:27 PM UTC 24
Finished Sep 18 04:31:57 PM UTC 24
Peak memory 260764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931061826 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.931061826
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2100761751
Short name T188
Test name
Test status
Simulation time 3254865890 ps
CPU time 105.76 seconds
Started Sep 18 04:31:16 PM UTC 24
Finished Sep 18 04:33:04 PM UTC 24
Peak memory 277540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100761751 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.2100761751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1593116287
Short name T208
Test name
Test status
Simulation time 26898838407 ps
CPU time 486.77 seconds
Started Sep 18 04:31:08 PM UTC 24
Finished Sep 18 04:39:21 PM UTC 24
Peak memory 277540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593116287 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad
ow_reg_errors_with_csr_rw.1593116287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.2500931280
Short name T744
Test name
Test status
Simulation time 282818732 ps
CPU time 15.92 seconds
Started Sep 18 04:31:17 PM UTC 24
Finished Sep 18 04:31:35 PM UTC 24
Peak memory 267240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500931280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2500931280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3317578419
Short name T750
Test name
Test status
Simulation time 213938151 ps
CPU time 8.02 seconds
Started Sep 18 04:31:53 PM UTC 24
Finished Sep 18 04:32:03 PM UTC 24
Peak memory 250588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317578419 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem
_rw_with_rand_reset.3317578419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.2830449448
Short name T747
Test name
Test status
Simulation time 20737734 ps
CPU time 4.65 seconds
Started Sep 18 04:31:50 PM UTC 24
Finished Sep 18 04:31:55 PM UTC 24
Peak memory 250596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830449448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2830449448
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.1442281209
Short name T746
Test name
Test status
Simulation time 6705197 ps
CPU time 2.33 seconds
Started Sep 18 04:31:45 PM UTC 24
Finished Sep 18 04:31:49 PM UTC 24
Peak memory 248616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442281209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1442281209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.310141879
Short name T751
Test name
Test status
Simulation time 87406019 ps
CPU time 19.74 seconds
Started Sep 18 04:31:50 PM UTC 24
Finished Sep 18 04:32:11 PM UTC 24
Peak memory 250596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310141879 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.310141879
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.719811458
Short name T749
Test name
Test status
Simulation time 75730194 ps
CPU time 17.98 seconds
Started Sep 18 04:31:39 PM UTC 24
Finished Sep 18 04:31:58 PM UTC 24
Peak memory 260828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719811458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.719811458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.288142045
Short name T235
Test name
Test status
Simulation time 8966929475 ps
CPU time 48.53 seconds
Started Sep 18 04:31:41 PM UTC 24
Finished Sep 18 04:32:32 PM UTC 24
Peak memory 250660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288142045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.288142045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.19906377
Short name T756
Test name
Test status
Simulation time 271337823 ps
CPU time 15.79 seconds
Started Sep 18 04:32:15 PM UTC 24
Finished Sep 18 04:32:32 PM UTC 24
Peak memory 250660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19906377 -assert nop
ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem_r
w_with_rand_reset.19906377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.4161722560
Short name T753
Test name
Test status
Simulation time 61488297 ps
CPU time 8.15 seconds
Started Sep 18 04:32:07 PM UTC 24
Finished Sep 18 04:32:16 PM UTC 24
Peak memory 248468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161722560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.4161722560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.1051448383
Short name T384
Test name
Test status
Simulation time 9138437 ps
CPU time 2.48 seconds
Started Sep 18 04:32:03 PM UTC 24
Finished Sep 18 04:32:07 PM UTC 24
Peak memory 248616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051448383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1051448383
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3391019951
Short name T759
Test name
Test status
Simulation time 509390893 ps
CPU time 26.94 seconds
Started Sep 18 04:32:11 PM UTC 24
Finished Sep 18 04:32:40 PM UTC 24
Peak memory 258716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391019951 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.3391019951
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3585067430
Short name T193
Test name
Test status
Simulation time 6232661413 ps
CPU time 197.71 seconds
Started Sep 18 04:31:59 PM UTC 24
Finished Sep 18 04:35:20 PM UTC 24
Peak memory 277612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585067430 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.3585067430
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.1750016143
Short name T754
Test name
Test status
Simulation time 204100096 ps
CPU time 21.4 seconds
Started Sep 18 04:31:59 PM UTC 24
Finished Sep 18 04:32:21 PM UTC 24
Peak memory 261032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750016143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1750016143
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.912976801
Short name T761
Test name
Test status
Simulation time 37845140 ps
CPU time 8.93 seconds
Started Sep 18 04:32:38 PM UTC 24
Finished Sep 18 04:32:47 PM UTC 24
Peak memory 267044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912976801 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem_
rw_with_rand_reset.912976801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.2928729251
Short name T758
Test name
Test status
Simulation time 174811941 ps
CPU time 5.06 seconds
Started Sep 18 04:32:33 PM UTC 24
Finished Sep 18 04:32:39 PM UTC 24
Peak memory 248480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928729251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2928729251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.873873559
Short name T757
Test name
Test status
Simulation time 7230153 ps
CPU time 2.39 seconds
Started Sep 18 04:32:32 PM UTC 24
Finished Sep 18 04:32:36 PM UTC 24
Peak memory 248676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873873559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.873873559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4082878207
Short name T766
Test name
Test status
Simulation time 171331426 ps
CPU time 34.37 seconds
Started Sep 18 04:32:36 PM UTC 24
Finished Sep 18 04:33:12 PM UTC 24
Peak memory 258712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082878207 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.4082878207
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2217570555
Short name T190
Test name
Test status
Simulation time 8952565837 ps
CPU time 200.43 seconds
Started Sep 18 04:32:18 PM UTC 24
Finished Sep 18 04:35:41 PM UTC 24
Peak memory 277540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217570555 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.2217570555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2538501338
Short name T216
Test name
Test status
Simulation time 27611276959 ps
CPU time 500.41 seconds
Started Sep 18 04:32:18 PM UTC 24
Finished Sep 18 04:40:44 PM UTC 24
Peak memory 277536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538501338 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shad
ow_reg_errors_with_csr_rw.2538501338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.2037256043
Short name T762
Test name
Test status
Simulation time 496304839 ps
CPU time 25.44 seconds
Started Sep 18 04:32:23 PM UTC 24
Finished Sep 18 04:32:49 PM UTC 24
Peak memory 263080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037256043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2037256043
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2592861204
Short name T767
Test name
Test status
Simulation time 54798898 ps
CPU time 14.13 seconds
Started Sep 18 04:33:01 PM UTC 24
Finished Sep 18 04:33:16 PM UTC 24
Peak memory 267044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592861204 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem
_rw_with_rand_reset.2592861204
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.566408798
Short name T765
Test name
Test status
Simulation time 394952383 ps
CPU time 12.42 seconds
Started Sep 18 04:32:55 PM UTC 24
Finished Sep 18 04:33:09 PM UTC 24
Peak memory 248548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566408798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.566408798
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.941143238
Short name T763
Test name
Test status
Simulation time 7510282 ps
CPU time 2.33 seconds
Started Sep 18 04:32:50 PM UTC 24
Finished Sep 18 04:32:54 PM UTC 24
Peak memory 248488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941143238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.941143238
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4005071313
Short name T772
Test name
Test status
Simulation time 525659816 ps
CPU time 33.83 seconds
Started Sep 18 04:32:58 PM UTC 24
Finished Sep 18 04:33:33 PM UTC 24
Peak memory 258724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005071313 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.4005071313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2476238172
Short name T209
Test name
Test status
Simulation time 153745328054 ps
CPU time 1324.78 seconds
Started Sep 18 04:32:41 PM UTC 24
Finished Sep 18 04:55:03 PM UTC 24
Peak memory 280312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476238172 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shad
ow_reg_errors_with_csr_rw.2476238172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.3754044290
Short name T764
Test name
Test status
Simulation time 89085918 ps
CPU time 17.12 seconds
Started Sep 18 04:32:47 PM UTC 24
Finished Sep 18 04:33:06 PM UTC 24
Peak memory 260904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754044290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3754044290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3512107285
Short name T773
Test name
Test status
Simulation time 245093685 ps
CPU time 10.41 seconds
Started Sep 18 04:33:23 PM UTC 24
Finished Sep 18 04:33:34 PM UTC 24
Peak memory 250588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512107285 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem
_rw_with_rand_reset.3512107285
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.948249295
Short name T770
Test name
Test status
Simulation time 36311960 ps
CPU time 5.65 seconds
Started Sep 18 04:33:17 PM UTC 24
Finished Sep 18 04:33:24 PM UTC 24
Peak memory 248548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948249295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.948249295
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.3770477084
Short name T768
Test name
Test status
Simulation time 23852804 ps
CPU time 2.33 seconds
Started Sep 18 04:33:13 PM UTC 24
Finished Sep 18 04:33:17 PM UTC 24
Peak memory 248416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770477084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3770477084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3259775058
Short name T774
Test name
Test status
Simulation time 90524830 ps
CPU time 17.22 seconds
Started Sep 18 04:33:17 PM UTC 24
Finished Sep 18 04:33:36 PM UTC 24
Peak memory 250520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259775058 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.3259775058
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3979640763
Short name T214
Test name
Test status
Simulation time 24895662145 ps
CPU time 1109.26 seconds
Started Sep 18 04:33:02 PM UTC 24
Finished Sep 18 04:51:45 PM UTC 24
Peak memory 277740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979640763 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shad
ow_reg_errors_with_csr_rw.3979640763
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.1783516268
Short name T769
Test name
Test status
Simulation time 90793927 ps
CPU time 12.84 seconds
Started Sep 18 04:33:07 PM UTC 24
Finished Sep 18 04:33:21 PM UTC 24
Peak memory 267112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783516268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1783516268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.505298852
Short name T780
Test name
Test status
Simulation time 202447681 ps
CPU time 22.23 seconds
Started Sep 18 04:33:41 PM UTC 24
Finished Sep 18 04:34:04 PM UTC 24
Peak memory 267044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505298852 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem_
rw_with_rand_reset.505298852
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.3793048175
Short name T777
Test name
Test status
Simulation time 60924869 ps
CPU time 8.78 seconds
Started Sep 18 04:33:36 PM UTC 24
Finished Sep 18 04:33:46 PM UTC 24
Peak memory 248468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793048175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3793048175
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.236540435
Short name T775
Test name
Test status
Simulation time 8484138 ps
CPU time 2.34 seconds
Started Sep 18 04:33:36 PM UTC 24
Finished Sep 18 04:33:40 PM UTC 24
Peak memory 246440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236540435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.236540435
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.4289363103
Short name T778
Test name
Test status
Simulation time 87776116 ps
CPU time 17.7 seconds
Started Sep 18 04:33:38 PM UTC 24
Finished Sep 18 04:33:56 PM UTC 24
Peak memory 250524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289363103 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.4289363103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3808861467
Short name T205
Test name
Test status
Simulation time 8371771376 ps
CPU time 349.93 seconds
Started Sep 18 04:33:25 PM UTC 24
Finished Sep 18 04:39:20 PM UTC 24
Peak memory 283820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808861467 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad
ow_reg_errors_with_csr_rw.3808861467
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.216150244
Short name T776
Test name
Test status
Simulation time 456529512 ps
CPU time 10.1 seconds
Started Sep 18 04:33:34 PM UTC 24
Finished Sep 18 04:33:45 PM UTC 24
Peak memory 265124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216150244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.216150244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2801185609
Short name T292
Test name
Test status
Simulation time 2480460407 ps
CPU time 88.81 seconds
Started Sep 18 04:33:35 PM UTC 24
Finished Sep 18 04:35:06 PM UTC 24
Peak memory 250660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801185609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2801185609
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1074960090
Short name T784
Test name
Test status
Simulation time 409162017 ps
CPU time 12.15 seconds
Started Sep 18 04:34:09 PM UTC 24
Finished Sep 18 04:34:23 PM UTC 24
Peak memory 250724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074960090 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem
_rw_with_rand_reset.1074960090
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.3383558655
Short name T783
Test name
Test status
Simulation time 293528297 ps
CPU time 7.35 seconds
Started Sep 18 04:34:05 PM UTC 24
Finished Sep 18 04:34:14 PM UTC 24
Peak memory 248544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383558655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3383558655
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2079049866
Short name T785
Test name
Test status
Simulation time 357318124 ps
CPU time 16.7 seconds
Started Sep 18 04:34:07 PM UTC 24
Finished Sep 18 04:34:24 PM UTC 24
Peak memory 258980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079049866 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.2079049866
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2951277788
Short name T201
Test name
Test status
Simulation time 8631213103 ps
CPU time 354.21 seconds
Started Sep 18 04:33:46 PM UTC 24
Finished Sep 18 04:39:45 PM UTC 24
Peak memory 277740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951277788 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad
ow_reg_errors_with_csr_rw.2951277788
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.3106248814
Short name T781
Test name
Test status
Simulation time 253419466 ps
CPU time 7.29 seconds
Started Sep 18 04:33:57 PM UTC 24
Finished Sep 18 04:34:06 PM UTC 24
Peak memory 265004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106248814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3106248814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3317096558
Short name T779
Test name
Test status
Simulation time 97587889 ps
CPU time 4.1 seconds
Started Sep 18 04:33:59 PM UTC 24
Finished Sep 18 04:34:04 PM UTC 24
Peak memory 248676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317096558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3317096558
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4228205807
Short name T789
Test name
Test status
Simulation time 65673525 ps
CPU time 17.18 seconds
Started Sep 18 04:34:34 PM UTC 24
Finished Sep 18 04:34:53 PM UTC 24
Peak memory 266972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228205807 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem
_rw_with_rand_reset.4228205807
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.3048921544
Short name T788
Test name
Test status
Simulation time 51607945 ps
CPU time 7.05 seconds
Started Sep 18 04:34:29 PM UTC 24
Finished Sep 18 04:34:38 PM UTC 24
Peak memory 248736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048921544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3048921544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.732067736
Short name T786
Test name
Test status
Simulation time 9782766 ps
CPU time 2.14 seconds
Started Sep 18 04:34:25 PM UTC 24
Finished Sep 18 04:34:28 PM UTC 24
Peak memory 248416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732067736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.732067736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4203356867
Short name T793
Test name
Test status
Simulation time 678229650 ps
CPU time 73.02 seconds
Started Sep 18 04:34:31 PM UTC 24
Finished Sep 18 04:35:46 PM UTC 24
Peak memory 258916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203356867 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.4203356867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1605371006
Short name T194
Test name
Test status
Simulation time 1112221511 ps
CPU time 91.16 seconds
Started Sep 18 04:34:18 PM UTC 24
Finished Sep 18 04:35:51 PM UTC 24
Peak memory 277476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605371006 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.1605371006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.1305738379
Short name T787
Test name
Test status
Simulation time 43581197 ps
CPU time 9.82 seconds
Started Sep 18 04:34:19 PM UTC 24
Finished Sep 18 04:34:30 PM UTC 24
Peak memory 260832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305738379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1305738379
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2711559471
Short name T797
Test name
Test status
Simulation time 411214166 ps
CPU time 13.28 seconds
Started Sep 18 04:35:42 PM UTC 24
Finished Sep 18 04:35:57 PM UTC 24
Peak memory 250588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711559471 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem
_rw_with_rand_reset.2711559471
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.3014271598
Short name T792
Test name
Test status
Simulation time 315411357 ps
CPU time 8.54 seconds
Started Sep 18 04:35:32 PM UTC 24
Finished Sep 18 04:35:42 PM UTC 24
Peak memory 248672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014271598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3014271598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.2163460711
Short name T791
Test name
Test status
Simulation time 14759585 ps
CPU time 2.81 seconds
Started Sep 18 04:35:27 PM UTC 24
Finished Sep 18 04:35:31 PM UTC 24
Peak memory 248488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163460711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2163460711
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3081633521
Short name T826
Test name
Test status
Simulation time 531354218 ps
CPU time 40.08 seconds
Started Sep 18 04:35:42 PM UTC 24
Finished Sep 18 04:36:24 PM UTC 24
Peak memory 258712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081633521 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.3081633521
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.677417706
Short name T393
Test name
Test status
Simulation time 17946409372 ps
CPU time 634.59 seconds
Started Sep 18 04:34:38 PM UTC 24
Finished Sep 18 04:45:22 PM UTC 24
Peak memory 277540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677417706 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shado
w_reg_errors_with_csr_rw.677417706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.3363883523
Short name T790
Test name
Test status
Simulation time 83879163 ps
CPU time 18.36 seconds
Started Sep 18 04:35:07 PM UTC 24
Finished Sep 18 04:35:26 PM UTC 24
Peak memory 260840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363883523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3363883523
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1880378427
Short name T806
Test name
Test status
Simulation time 446782343 ps
CPU time 47.14 seconds
Started Sep 18 04:35:21 PM UTC 24
Finished Sep 18 04:36:10 PM UTC 24
Peak memory 250524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880378427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1880378427
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3576765621
Short name T752
Test name
Test status
Simulation time 4104195577 ps
CPU time 362.39 seconds
Started Sep 18 04:26:07 PM UTC 24
Finished Sep 18 04:32:15 PM UTC 24
Peak memory 250792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576765621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3576765621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1953491456
Short name T165
Test name
Test status
Simulation time 201682151 ps
CPU time 5.72 seconds
Started Sep 18 04:26:00 PM UTC 24
Finished Sep 18 04:26:06 PM UTC 24
Peak memory 260764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953491456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1953491456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2812454309
Short name T391
Test name
Test status
Simulation time 60151049 ps
CPU time 14.61 seconds
Started Sep 18 04:26:51 PM UTC 24
Finished Sep 18 04:27:07 PM UTC 24
Peak memory 267044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812454309 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_
rw_with_rand_reset.2812454309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.4175635756
Short name T181
Test name
Test status
Simulation time 115206270 ps
CPU time 9.31 seconds
Started Sep 18 04:26:01 PM UTC 24
Finished Sep 18 04:26:11 PM UTC 24
Peak memory 248468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175635756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4175635756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.1570815604
Short name T251
Test name
Test status
Simulation time 9629092 ps
CPU time 2.55 seconds
Started Sep 18 04:25:56 PM UTC 24
Finished Sep 18 04:25:59 PM UTC 24
Peak memory 248412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570815604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1570815604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1257833456
Short name T175
Test name
Test status
Simulation time 176207088 ps
CPU time 37.54 seconds
Started Sep 18 04:26:12 PM UTC 24
Finished Sep 18 04:26:51 PM UTC 24
Peak memory 258716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257833456 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.1257833456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.2881260129
Short name T717
Test name
Test status
Simulation time 110005844 ps
CPU time 13.55 seconds
Started Sep 18 04:25:46 PM UTC 24
Finished Sep 18 04:26:01 PM UTC 24
Peak memory 260904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881260129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2881260129
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.1998424094
Short name T794
Test name
Test status
Simulation time 12105363 ps
CPU time 2.21 seconds
Started Sep 18 04:35:47 PM UTC 24
Finished Sep 18 04:35:51 PM UTC 24
Peak memory 248416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998424094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1998424094
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.3612751547
Short name T796
Test name
Test status
Simulation time 8486423 ps
CPU time 2.36 seconds
Started Sep 18 04:35:52 PM UTC 24
Finished Sep 18 04:35:55 PM UTC 24
Peak memory 248616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612751547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3612751547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.2832593798
Short name T795
Test name
Test status
Simulation time 51871386 ps
CPU time 2.17 seconds
Started Sep 18 04:35:52 PM UTC 24
Finished Sep 18 04:35:55 PM UTC 24
Peak memory 248416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832593798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2832593798
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1052027927
Short name T798
Test name
Test status
Simulation time 44382228 ps
CPU time 2.11 seconds
Started Sep 18 04:35:56 PM UTC 24
Finished Sep 18 04:35:59 PM UTC 24
Peak memory 248616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052027927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1052027927
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2727293222
Short name T799
Test name
Test status
Simulation time 6655079 ps
CPU time 2.24 seconds
Started Sep 18 04:35:56 PM UTC 24
Finished Sep 18 04:35:59 PM UTC 24
Peak memory 248416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727293222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2727293222
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.1799448491
Short name T800
Test name
Test status
Simulation time 11377533 ps
CPU time 2.13 seconds
Started Sep 18 04:35:56 PM UTC 24
Finished Sep 18 04:35:59 PM UTC 24
Peak memory 248416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799448491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1799448491
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.2321671644
Short name T801
Test name
Test status
Simulation time 11759973 ps
CPU time 2.61 seconds
Started Sep 18 04:35:58 PM UTC 24
Finished Sep 18 04:36:02 PM UTC 24
Peak memory 248416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321671644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2321671644
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.2741447827
Short name T803
Test name
Test status
Simulation time 10853273 ps
CPU time 2.02 seconds
Started Sep 18 04:36:00 PM UTC 24
Finished Sep 18 04:36:06 PM UTC 24
Peak memory 248488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741447827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2741447827
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2963826006
Short name T802
Test name
Test status
Simulation time 7173092 ps
CPU time 1.65 seconds
Started Sep 18 04:36:00 PM UTC 24
Finished Sep 18 04:36:06 PM UTC 24
Peak memory 244812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963826006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2963826006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2842108830
Short name T804
Test name
Test status
Simulation time 40354019 ps
CPU time 2.23 seconds
Started Sep 18 04:36:00 PM UTC 24
Finished Sep 18 04:36:07 PM UTC 24
Peak memory 248492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842108830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2842108830
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3316214459
Short name T738
Test name
Test status
Simulation time 1135528793 ps
CPU time 209.44 seconds
Started Sep 18 04:27:34 PM UTC 24
Finished Sep 18 04:31:06 PM UTC 24
Peak memory 250600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316214459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3316214459
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.646327475
Short name T827
Test name
Test status
Simulation time 34242412454 ps
CPU time 526.65 seconds
Started Sep 18 04:27:31 PM UTC 24
Finished Sep 18 04:36:24 PM UTC 24
Peak memory 248740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646327475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.646327475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.756832023
Short name T256
Test name
Test status
Simulation time 505013519 ps
CPU time 15.24 seconds
Started Sep 18 04:27:12 PM UTC 24
Finished Sep 18 04:27:29 PM UTC 24
Peak memory 260964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756832023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.756832023
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3922718755
Short name T389
Test name
Test status
Simulation time 52267686 ps
CPU time 12.73 seconds
Started Sep 18 04:27:41 PM UTC 24
Finished Sep 18 04:27:55 PM UTC 24
Peak memory 252636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922718755 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_
rw_with_rand_reset.3922718755
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.3052120376
Short name T168
Test name
Test status
Simulation time 120788737 ps
CPU time 8.79 seconds
Started Sep 18 04:27:29 PM UTC 24
Finished Sep 18 04:27:39 PM UTC 24
Peak memory 248468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052120376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3052120376
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.4019606939
Short name T171
Test name
Test status
Simulation time 537196303 ps
CPU time 65.37 seconds
Started Sep 18 04:27:34 PM UTC 24
Finished Sep 18 04:28:41 PM UTC 24
Peak memory 258920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019606939 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.4019606939
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3143296449
Short name T187
Test name
Test status
Simulation time 3808965249 ps
CPU time 299.88 seconds
Started Sep 18 04:26:56 PM UTC 24
Finished Sep 18 04:32:00 PM UTC 24
Peak memory 277536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143296449 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.3143296449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.3681881947
Short name T718
Test name
Test status
Simulation time 52780827 ps
CPU time 7.83 seconds
Started Sep 18 04:26:57 PM UTC 24
Finished Sep 18 04:27:06 PM UTC 24
Peak memory 260832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681881947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3681881947
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.2744600192
Short name T805
Test name
Test status
Simulation time 16278266 ps
CPU time 1.51 seconds
Started Sep 18 04:36:02 PM UTC 24
Finished Sep 18 04:36:07 PM UTC 24
Peak memory 246860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744600192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2744600192
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2328218824
Short name T807
Test name
Test status
Simulation time 12177347 ps
CPU time 1.78 seconds
Started Sep 18 04:36:07 PM UTC 24
Finished Sep 18 04:36:10 PM UTC 24
Peak memory 246860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328218824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2328218824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.3331888120
Short name T808
Test name
Test status
Simulation time 7971806 ps
CPU time 1.97 seconds
Started Sep 18 04:36:08 PM UTC 24
Finished Sep 18 04:36:11 PM UTC 24
Peak memory 246860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331888120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3331888120
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.920341107
Short name T809
Test name
Test status
Simulation time 14640145 ps
CPU time 2.08 seconds
Started Sep 18 04:36:09 PM UTC 24
Finished Sep 18 04:36:12 PM UTC 24
Peak memory 248484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920341107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.920341107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3727179097
Short name T810
Test name
Test status
Simulation time 34683456 ps
CPU time 2.15 seconds
Started Sep 18 04:36:09 PM UTC 24
Finished Sep 18 04:36:13 PM UTC 24
Peak memory 248416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727179097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3727179097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.3757578822
Short name T811
Test name
Test status
Simulation time 16290343 ps
CPU time 2.04 seconds
Started Sep 18 04:36:09 PM UTC 24
Finished Sep 18 04:36:13 PM UTC 24
Peak memory 248488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757578822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3757578822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.484555424
Short name T813
Test name
Test status
Simulation time 7913191 ps
CPU time 2.28 seconds
Started Sep 18 04:36:09 PM UTC 24
Finished Sep 18 04:36:13 PM UTC 24
Peak memory 246440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484555424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.484555424
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.4200004484
Short name T812
Test name
Test status
Simulation time 10686375 ps
CPU time 2.01 seconds
Started Sep 18 04:36:09 PM UTC 24
Finished Sep 18 04:36:13 PM UTC 24
Peak memory 244812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200004484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.4200004484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.3546991965
Short name T816
Test name
Test status
Simulation time 14924671 ps
CPU time 2.52 seconds
Started Sep 18 04:36:11 PM UTC 24
Finished Sep 18 04:36:16 PM UTC 24
Peak memory 248488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546991965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3546991965
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.285889780
Short name T814
Test name
Test status
Simulation time 18915837 ps
CPU time 2.24 seconds
Started Sep 18 04:36:11 PM UTC 24
Finished Sep 18 04:36:15 PM UTC 24
Peak memory 246440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285889780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.285889780
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1747900581
Short name T724
Test name
Test status
Simulation time 1086306112 ps
CPU time 87.71 seconds
Started Sep 18 04:28:28 PM UTC 24
Finished Sep 18 04:29:58 PM UTC 24
Peak memory 250728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747900581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1747900581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1617579370
Short name T760
Test name
Test status
Simulation time 6801989592 ps
CPU time 254.37 seconds
Started Sep 18 04:28:27 PM UTC 24
Finished Sep 18 04:32:46 PM UTC 24
Peak memory 248616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617579370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1617579370
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.246303753
Short name T169
Test name
Test status
Simulation time 49384170 ps
CPU time 9.2 seconds
Started Sep 18 04:28:16 PM UTC 24
Finished Sep 18 04:28:26 PM UTC 24
Peak memory 250596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246303753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.246303753
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1987853845
Short name T394
Test name
Test status
Simulation time 494300596 ps
CPU time 21.3 seconds
Started Sep 18 04:28:47 PM UTC 24
Finished Sep 18 04:29:10 PM UTC 24
Peak memory 262876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987853845 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_
rw_with_rand_reset.1987853845
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.1257672962
Short name T170
Test name
Test status
Simulation time 35706032 ps
CPU time 9.62 seconds
Started Sep 18 04:28:17 PM UTC 24
Finished Sep 18 04:28:27 PM UTC 24
Peak memory 248472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257672962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1257672962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.282820226
Short name T387
Test name
Test status
Simulation time 6331939 ps
CPU time 2.26 seconds
Started Sep 18 04:28:11 PM UTC 24
Finished Sep 18 04:28:15 PM UTC 24
Peak memory 246440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282820226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.282820226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.856813710
Short name T176
Test name
Test status
Simulation time 1028233468 ps
CPU time 34.77 seconds
Started Sep 18 04:28:42 PM UTC 24
Finished Sep 18 04:29:18 PM UTC 24
Peak memory 258784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856813710 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.856813710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1064540580
Short name T183
Test name
Test status
Simulation time 3812535680 ps
CPU time 143.41 seconds
Started Sep 18 04:27:57 PM UTC 24
Finished Sep 18 04:30:23 PM UTC 24
Peak memory 277612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064540580 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.1064540580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3527952076
Short name T197
Test name
Test status
Simulation time 29260010615 ps
CPU time 498.73 seconds
Started Sep 18 04:27:57 PM UTC 24
Finished Sep 18 04:36:22 PM UTC 24
Peak memory 281632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527952076 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shado
w_reg_errors_with_csr_rw.3527952076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.757522240
Short name T719
Test name
Test status
Simulation time 31038223 ps
CPU time 6.06 seconds
Started Sep 18 04:28:03 PM UTC 24
Finished Sep 18 04:28:10 PM UTC 24
Peak memory 261036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757522240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.757522240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3876909795
Short name T237
Test name
Test status
Simulation time 79122447 ps
CPU time 4.4 seconds
Started Sep 18 04:28:10 PM UTC 24
Finished Sep 18 04:28:16 PM UTC 24
Peak memory 248484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876909795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3876909795
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.588005765
Short name T815
Test name
Test status
Simulation time 10307957 ps
CPU time 2.19 seconds
Started Sep 18 04:36:11 PM UTC 24
Finished Sep 18 04:36:15 PM UTC 24
Peak memory 248616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588005765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.588005765
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.2090924251
Short name T817
Test name
Test status
Simulation time 26768574 ps
CPU time 3.32 seconds
Started Sep 18 04:36:11 PM UTC 24
Finished Sep 18 04:36:17 PM UTC 24
Peak memory 246568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090924251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2090924251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.1285253176
Short name T818
Test name
Test status
Simulation time 12354568 ps
CPU time 1.98 seconds
Started Sep 18 04:36:13 PM UTC 24
Finished Sep 18 04:36:17 PM UTC 24
Peak memory 246792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285253176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1285253176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.1161157662
Short name T819
Test name
Test status
Simulation time 6529880 ps
CPU time 2.17 seconds
Started Sep 18 04:36:14 PM UTC 24
Finished Sep 18 04:36:17 PM UTC 24
Peak memory 246368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161157662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1161157662
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.1862423645
Short name T820
Test name
Test status
Simulation time 10401131 ps
CPU time 2.11 seconds
Started Sep 18 04:36:15 PM UTC 24
Finished Sep 18 04:36:18 PM UTC 24
Peak memory 248416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862423645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1862423645
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.1980899412
Short name T821
Test name
Test status
Simulation time 8216053 ps
CPU time 2.18 seconds
Started Sep 18 04:36:15 PM UTC 24
Finished Sep 18 04:36:18 PM UTC 24
Peak memory 248420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980899412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1980899412
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.3692405451
Short name T822
Test name
Test status
Simulation time 7953730 ps
CPU time 2.28 seconds
Started Sep 18 04:36:15 PM UTC 24
Finished Sep 18 04:36:18 PM UTC 24
Peak memory 248680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692405451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3692405451
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.2801752084
Short name T825
Test name
Test status
Simulation time 10554633 ps
CPU time 2.24 seconds
Started Sep 18 04:36:17 PM UTC 24
Finished Sep 18 04:36:20 PM UTC 24
Peak memory 248404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801752084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2801752084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.1156236476
Short name T824
Test name
Test status
Simulation time 8045477 ps
CPU time 2.17 seconds
Started Sep 18 04:36:17 PM UTC 24
Finished Sep 18 04:36:20 PM UTC 24
Peak memory 248680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156236476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1156236476
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.3110764943
Short name T823
Test name
Test status
Simulation time 9713008 ps
CPU time 1.57 seconds
Started Sep 18 04:36:17 PM UTC 24
Finished Sep 18 04:36:19 PM UTC 24
Peak memory 246764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110764943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3110764943
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2883287150
Short name T258
Test name
Test status
Simulation time 173583508 ps
CPU time 10.11 seconds
Started Sep 18 04:29:28 PM UTC 24
Finished Sep 18 04:29:39 PM UTC 24
Peak memory 250588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883287150 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_
rw_with_rand_reset.2883287150
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.2465170430
Short name T721
Test name
Test status
Simulation time 97835466 ps
CPU time 13.94 seconds
Started Sep 18 04:29:24 PM UTC 24
Finished Sep 18 04:29:39 PM UTC 24
Peak memory 248468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465170430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2465170430
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.71015805
Short name T385
Test name
Test status
Simulation time 12411174 ps
CPU time 2.15 seconds
Started Sep 18 04:29:20 PM UTC 24
Finished Sep 18 04:29:23 PM UTC 24
Peak memory 246568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71015805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.71015805
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1166706209
Short name T722
Test name
Test status
Simulation time 90556453 ps
CPU time 20.32 seconds
Started Sep 18 04:29:27 PM UTC 24
Finished Sep 18 04:29:48 PM UTC 24
Peak memory 258792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166706209 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.1166706209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2464573015
Short name T184
Test name
Test status
Simulation time 1130296748 ps
CPU time 129.61 seconds
Started Sep 18 04:29:11 PM UTC 24
Finished Sep 18 04:31:23 PM UTC 24
Peak memory 279596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464573015 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.2464573015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1630829806
Short name T206
Test name
Test status
Simulation time 6381726794 ps
CPU time 576.95 seconds
Started Sep 18 04:29:07 PM UTC 24
Finished Sep 18 04:38:52 PM UTC 24
Peak memory 281708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630829806 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shado
w_reg_errors_with_csr_rw.1630829806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.231017151
Short name T720
Test name
Test status
Simulation time 89231871 ps
CPU time 14.08 seconds
Started Sep 18 04:29:16 PM UTC 24
Finished Sep 18 04:29:31 PM UTC 24
Peak memory 260904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231017151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.231017151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3000955749
Short name T392
Test name
Test status
Simulation time 1117353027 ps
CPU time 9.94 seconds
Started Sep 18 04:29:54 PM UTC 24
Finished Sep 18 04:30:05 PM UTC 24
Peak memory 250788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000955749 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_
rw_with_rand_reset.3000955749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.2522184039
Short name T725
Test name
Test status
Simulation time 123190872 ps
CPU time 14.9 seconds
Started Sep 18 04:29:50 PM UTC 24
Finished Sep 18 04:30:06 PM UTC 24
Peak memory 250724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522184039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2522184039
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.1685327883
Short name T386
Test name
Test status
Simulation time 9863676 ps
CPU time 2.39 seconds
Started Sep 18 04:29:48 PM UTC 24
Finished Sep 18 04:29:51 PM UTC 24
Peak memory 248488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685327883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1685327883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.739197155
Short name T729
Test name
Test status
Simulation time 334038005 ps
CPU time 41.43 seconds
Started Sep 18 04:29:53 PM UTC 24
Finished Sep 18 04:30:37 PM UTC 24
Peak memory 258912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739197155 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.739197155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3196047153
Short name T203
Test name
Test status
Simulation time 6961351894 ps
CPU time 161.8 seconds
Started Sep 18 04:29:31 PM UTC 24
Finished Sep 18 04:32:16 PM UTC 24
Peak memory 277540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196047153 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.3196047153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.3415894694
Short name T723
Test name
Test status
Simulation time 312294551 ps
CPU time 11.34 seconds
Started Sep 18 04:29:40 PM UTC 24
Finished Sep 18 04:29:53 PM UTC 24
Peak memory 260900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415894694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3415894694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2325049580
Short name T230
Test name
Test status
Simulation time 44062153 ps
CPU time 5.23 seconds
Started Sep 18 04:29:40 PM UTC 24
Finished Sep 18 04:29:47 PM UTC 24
Peak memory 250608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325049580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2325049580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.508393001
Short name T730
Test name
Test status
Simulation time 153751194 ps
CPU time 18.53 seconds
Started Sep 18 04:30:22 PM UTC 24
Finished Sep 18 04:30:42 PM UTC 24
Peak memory 264924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508393001 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_r
w_with_rand_reset.508393001
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.869805091
Short name T728
Test name
Test status
Simulation time 121988117 ps
CPU time 6.49 seconds
Started Sep 18 04:30:19 PM UTC 24
Finished Sep 18 04:30:27 PM UTC 24
Peak memory 250596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869805091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.869805091
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.1973699496
Short name T388
Test name
Test status
Simulation time 38918276 ps
CPU time 1.99 seconds
Started Sep 18 04:30:18 PM UTC 24
Finished Sep 18 04:30:21 PM UTC 24
Peak memory 246792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973699496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1973699496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.126179033
Short name T736
Test name
Test status
Simulation time 510902620 ps
CPU time 43.83 seconds
Started Sep 18 04:30:19 PM UTC 24
Finished Sep 18 04:31:04 PM UTC 24
Peak memory 261024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126179033 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.126179033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3917497250
Short name T215
Test name
Test status
Simulation time 18654290383 ps
CPU time 902.41 seconds
Started Sep 18 04:29:59 PM UTC 24
Finished Sep 18 04:45:12 PM UTC 24
Peak memory 283680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917497250 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado
w_reg_errors_with_csr_rw.3917497250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.2611644744
Short name T726
Test name
Test status
Simulation time 221258188 ps
CPU time 10.9 seconds
Started Sep 18 04:30:06 PM UTC 24
Finished Sep 18 04:30:18 PM UTC 24
Peak memory 261032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611644744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2611644744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1070385336
Short name T733
Test name
Test status
Simulation time 275690220 ps
CPU time 7.24 seconds
Started Sep 18 04:30:44 PM UTC 24
Finished Sep 18 04:30:52 PM UTC 24
Peak memory 250588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070385336 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_
rw_with_rand_reset.1070385336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.2194242754
Short name T734
Test name
Test status
Simulation time 128601106 ps
CPU time 14.17 seconds
Started Sep 18 04:30:40 PM UTC 24
Finished Sep 18 04:30:55 PM UTC 24
Peak memory 248468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194242754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2194242754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.724702605
Short name T731
Test name
Test status
Simulation time 16554528 ps
CPU time 2.06 seconds
Started Sep 18 04:30:39 PM UTC 24
Finished Sep 18 04:30:42 PM UTC 24
Peak memory 246512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724702605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.724702605
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3996730981
Short name T741
Test name
Test status
Simulation time 868949100 ps
CPU time 36.9 seconds
Started Sep 18 04:30:43 PM UTC 24
Finished Sep 18 04:31:21 PM UTC 24
Peak memory 258716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996730981 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.3996730981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1465146124
Short name T198
Test name
Test status
Simulation time 3054291257 ps
CPU time 227.28 seconds
Started Sep 18 04:30:27 PM UTC 24
Finished Sep 18 04:34:18 PM UTC 24
Peak memory 277676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465146124 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.1465146124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2270717695
Short name T207
Test name
Test status
Simulation time 5240424296 ps
CPU time 687.74 seconds
Started Sep 18 04:30:24 PM UTC 24
Finished Sep 18 04:42:02 PM UTC 24
Peak memory 283680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270717695 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shado
w_reg_errors_with_csr_rw.2270717695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.2061426428
Short name T732
Test name
Test status
Simulation time 161471610 ps
CPU time 10.82 seconds
Started Sep 18 04:30:35 PM UTC 24
Finished Sep 18 04:30:47 PM UTC 24
Peak memory 264924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061426428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2061426428
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.320981633
Short name T740
Test name
Test status
Simulation time 367646789 ps
CPU time 8.26 seconds
Started Sep 18 04:31:07 PM UTC 24
Finished Sep 18 04:31:16 PM UTC 24
Peak memory 260900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320981633 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_r
w_with_rand_reset.320981633
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.3173140460
Short name T739
Test name
Test status
Simulation time 1445662225 ps
CPU time 13.74 seconds
Started Sep 18 04:31:00 PM UTC 24
Finished Sep 18 04:31:15 PM UTC 24
Peak memory 248544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173140460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3173140460
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.2663480516
Short name T735
Test name
Test status
Simulation time 12490664 ps
CPU time 2.24 seconds
Started Sep 18 04:30:56 PM UTC 24
Finished Sep 18 04:30:59 PM UTC 24
Peak memory 248488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663480516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2663480516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3825293377
Short name T742
Test name
Test status
Simulation time 170010245 ps
CPU time 16.77 seconds
Started Sep 18 04:31:06 PM UTC 24
Finished Sep 18 04:31:24 PM UTC 24
Peak memory 258716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825293377 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.3825293377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2665697942
Short name T186
Test name
Test status
Simulation time 3874319592 ps
CPU time 130.04 seconds
Started Sep 18 04:30:48 PM UTC 24
Finished Sep 18 04:33:01 PM UTC 24
Peak memory 277536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665697942 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.2665697942
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.1207686419
Short name T737
Test name
Test status
Simulation time 183444241 ps
CPU time 11.8 seconds
Started Sep 18 04:30:53 PM UTC 24
Finished Sep 18 04:31:06 PM UTC 24
Peak memory 262948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207686419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1207686419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.569827175
Short name T94
Test name
Test status
Simulation time 2104794968 ps
CPU time 106.85 seconds
Started Sep 18 02:47:56 PM UTC 24
Finished Sep 18 02:49:45 PM UTC 24
Peak memory 266580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569827175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.569827175
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.2719742086
Short name T1
Test name
Test status
Simulation time 72161120 ps
CPU time 8.07 seconds
Started Sep 18 02:47:56 PM UTC 24
Finished Sep 18 02:48:05 PM UTC 24
Peak memory 250516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719742086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2719742086
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.3394503482
Short name T18
Test name
Test status
Simulation time 18009222941 ps
CPU time 174.21 seconds
Started Sep 18 02:48:01 PM UTC 24
Finished Sep 18 02:50:58 PM UTC 24
Peak memory 266976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394503482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3394503482
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.115050248
Short name T3
Test name
Test status
Simulation time 216541559 ps
CPU time 16.23 seconds
Started Sep 18 02:47:53 PM UTC 24
Finished Sep 18 02:48:10 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115050248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.115050248
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.1160662841
Short name T5
Test name
Test status
Simulation time 176779709 ps
CPU time 16.66 seconds
Started Sep 18 02:48:13 PM UTC 24
Finished Sep 18 02:48:30 PM UTC 24
Peak memory 294784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160662841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1160662841
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.13310408
Short name T10
Test name
Test status
Simulation time 494066257 ps
CPU time 21.9 seconds
Started Sep 18 02:47:51 PM UTC 24
Finished Sep 18 02:48:14 PM UTC 24
Peak memory 260508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13310408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.13310408
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/0.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.2511076440
Short name T319
Test name
Test status
Simulation time 143376651023 ps
CPU time 2204.54 seconds
Started Sep 18 02:48:21 PM UTC 24
Finished Sep 18 03:25:34 PM UTC 24
Peak memory 295912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511076440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2511076440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.1199869287
Short name T7
Test name
Test status
Simulation time 384154975 ps
CPU time 24.12 seconds
Started Sep 18 02:48:31 PM UTC 24
Finished Sep 18 02:48:56 PM UTC 24
Peak memory 260436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199869287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1199869287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.1963279152
Short name T44
Test name
Test status
Simulation time 409639761 ps
CPU time 56.86 seconds
Started Sep 18 02:48:19 PM UTC 24
Finished Sep 18 02:49:17 PM UTC 24
Peak memory 266676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963279152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1963279152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.3236377765
Short name T16
Test name
Test status
Simulation time 152092941 ps
CPU time 6.39 seconds
Started Sep 18 02:48:18 PM UTC 24
Finished Sep 18 02:48:26 PM UTC 24
Peak memory 260428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236377765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3236377765
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.2520712983
Short name T304
Test name
Test status
Simulation time 42163559400 ps
CPU time 1577.52 seconds
Started Sep 18 02:48:27 PM UTC 24
Finished Sep 18 03:15:03 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520712983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2520712983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.536798534
Short name T11
Test name
Test status
Simulation time 196717261 ps
CPU time 8.62 seconds
Started Sep 18 02:48:14 PM UTC 24
Finished Sep 18 02:48:24 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536798534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.536798534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.1230740775
Short name T15
Test name
Test status
Simulation time 4053168548 ps
CPU time 56.72 seconds
Started Sep 18 02:48:15 PM UTC 24
Finished Sep 18 02:49:13 PM UTC 24
Peak memory 260496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230740775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1230740775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.3084631602
Short name T6
Test name
Test status
Simulation time 238147044 ps
CPU time 13.05 seconds
Started Sep 18 02:48:41 PM UTC 24
Finished Sep 18 02:48:56 PM UTC 24
Peak memory 292808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084631602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3084631602
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.97726801
Short name T28
Test name
Test status
Simulation time 1747781307 ps
CPU time 40.43 seconds
Started Sep 18 02:48:13 PM UTC 24
Finished Sep 18 02:48:54 PM UTC 24
Peak memory 266844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97726801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.97726801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/1.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.504303813
Short name T240
Test name
Test status
Simulation time 377050275 ps
CPU time 4.52 seconds
Started Sep 18 02:57:02 PM UTC 24
Finished Sep 18 02:57:08 PM UTC 24
Peak memory 260712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504303813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.504303813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.1073674949
Short name T312
Test name
Test status
Simulation time 25442976631 ps
CPU time 622.37 seconds
Started Sep 18 02:56:22 PM UTC 24
Finished Sep 18 03:06:52 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073674949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1073674949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.741228807
Short name T399
Test name
Test status
Simulation time 569683741 ps
CPU time 18.96 seconds
Started Sep 18 02:56:54 PM UTC 24
Finished Sep 18 02:57:14 PM UTC 24
Peak memory 260124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741228807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.741228807
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.1554976519
Short name T414
Test name
Test status
Simulation time 3413271070 ps
CPU time 284.32 seconds
Started Sep 18 02:56:20 PM UTC 24
Finished Sep 18 03:01:08 PM UTC 24
Peak memory 266740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554976519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1554976519
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.2090762916
Short name T99
Test name
Test status
Simulation time 597814616 ps
CPU time 17.56 seconds
Started Sep 18 02:56:17 PM UTC 24
Finished Sep 18 02:56:35 PM UTC 24
Peak memory 260692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090762916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2090762916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.3608668269
Short name T311
Test name
Test status
Simulation time 10885535983 ps
CPU time 216.93 seconds
Started Sep 18 02:56:34 PM UTC 24
Finished Sep 18 03:00:14 PM UTC 24
Peak memory 260828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608668269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3608668269
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.3417540731
Short name T38
Test name
Test status
Simulation time 207624635 ps
CPU time 26.02 seconds
Started Sep 18 02:55:51 PM UTC 24
Finished Sep 18 02:56:18 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417540731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3417540731
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.2866845160
Short name T139
Test name
Test status
Simulation time 1095388609 ps
CPU time 54.53 seconds
Started Sep 18 02:56:05 PM UTC 24
Finished Sep 18 02:57:01 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866845160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2866845160
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.2503786245
Short name T398
Test name
Test status
Simulation time 1999721858 ps
CPU time 63.36 seconds
Started Sep 18 02:55:48 PM UTC 24
Finished Sep 18 02:56:53 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503786245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2503786245
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.2887509012
Short name T141
Test name
Test status
Simulation time 68637437077 ps
CPU time 920.06 seconds
Started Sep 18 02:56:54 PM UTC 24
Finished Sep 18 03:12:25 PM UTC 24
Peak memory 299244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887509012 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.2887509012
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all_with_rand_reset.1320695661
Short name T115
Test name
Test status
Simulation time 3957879691 ps
CPU time 202.17 seconds
Started Sep 18 02:57:02 PM UTC 24
Finished Sep 18 03:00:28 PM UTC 24
Peak memory 277008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1320695661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.a
lert_handler_stress_all_with_rand_reset.1320695661
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.1363751357
Short name T241
Test name
Test status
Simulation time 439418243 ps
CPU time 3.98 seconds
Started Sep 18 02:58:14 PM UTC 24
Finished Sep 18 02:58:19 PM UTC 24
Peak memory 260700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363751357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1363751357
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.1985982209
Short name T455
Test name
Test status
Simulation time 25664388588 ps
CPU time 1635.42 seconds
Started Sep 18 02:57:40 PM UTC 24
Finished Sep 18 03:25:13 PM UTC 24
Peak memory 283172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985982209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1985982209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.2747053018
Short name T404
Test name
Test status
Simulation time 1961590265 ps
CPU time 23.82 seconds
Started Sep 18 02:58:13 PM UTC 24
Finished Sep 18 02:58:38 PM UTC 24
Peak memory 260512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747053018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2747053018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.1317960142
Short name T401
Test name
Test status
Simulation time 99004822 ps
CPU time 10.47 seconds
Started Sep 18 02:57:27 PM UTC 24
Finished Sep 18 02:57:39 PM UTC 24
Peak memory 262476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317960142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1317960142
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.363112161
Short name T140
Test name
Test status
Simulation time 4352935718 ps
CPU time 102.27 seconds
Started Sep 18 02:57:25 PM UTC 24
Finished Sep 18 02:59:09 PM UTC 24
Peak memory 266776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363112161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.363112161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.2287248018
Short name T352
Test name
Test status
Simulation time 69352609117 ps
CPU time 1682.62 seconds
Started Sep 18 02:57:51 PM UTC 24
Finished Sep 18 03:26:14 PM UTC 24
Peak memory 299476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287248018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2287248018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.61888783
Short name T309
Test name
Test status
Simulation time 5472667355 ps
CPU time 122.28 seconds
Started Sep 18 02:57:44 PM UTC 24
Finished Sep 18 02:59:48 PM UTC 24
Peak memory 260644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61888783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.61888783
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.3845488033
Short name T349
Test name
Test status
Simulation time 836686984 ps
CPU time 25.91 seconds
Started Sep 18 02:57:16 PM UTC 24
Finished Sep 18 02:57:43 PM UTC 24
Peak memory 266608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845488033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3845488033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.2257106744
Short name T62
Test name
Test status
Simulation time 2067057234 ps
CPU time 53.47 seconds
Started Sep 18 02:57:18 PM UTC 24
Finished Sep 18 02:58:13 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257106744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2257106744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.2110001558
Short name T253
Test name
Test status
Simulation time 411536609 ps
CPU time 36.48 seconds
Started Sep 18 02:57:36 PM UTC 24
Finished Sep 18 02:58:14 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110001558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2110001558
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.1408440298
Short name T400
Test name
Test status
Simulation time 143458274 ps
CPU time 14.58 seconds
Started Sep 18 02:57:08 PM UTC 24
Finished Sep 18 02:57:24 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408440298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1408440298
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.18746478
Short name T262
Test name
Test status
Simulation time 126929910117 ps
CPU time 2290.43 seconds
Started Sep 18 02:58:13 PM UTC 24
Finished Sep 18 03:36:50 PM UTC 24
Peak memory 299476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18746478 -assert nopostproc +UVM_TES
TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.18746478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all_with_rand_reset.73688957
Short name T33
Test name
Test status
Simulation time 2158913916 ps
CPU time 201.25 seconds
Started Sep 18 02:58:15 PM UTC 24
Finished Sep 18 03:01:40 PM UTC 24
Peak memory 277012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=73688957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.ale
rt_handler_stress_all_with_rand_reset.73688957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.1669222537
Short name T242
Test name
Test status
Simulation time 22526139 ps
CPU time 3.51 seconds
Started Sep 18 03:00:12 PM UTC 24
Finished Sep 18 03:00:16 PM UTC 24
Peak memory 260700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669222537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1669222537
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.3912823625
Short name T71
Test name
Test status
Simulation time 33790722351 ps
CPU time 2061.56 seconds
Started Sep 18 02:59:07 PM UTC 24
Finished Sep 18 03:33:50 PM UTC 24
Peak memory 299744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912823625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3912823625
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.1433732635
Short name T410
Test name
Test status
Simulation time 1276552945 ps
CPU time 38.7 seconds
Started Sep 18 02:59:36 PM UTC 24
Finished Sep 18 03:00:16 PM UTC 24
Peak memory 260704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433732635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1433732635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.322231249
Short name T409
Test name
Test status
Simulation time 605129452 ps
CPU time 36.22 seconds
Started Sep 18 02:58:52 PM UTC 24
Finished Sep 18 02:59:29 PM UTC 24
Peak memory 266580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322231249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.322231249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.3984965464
Short name T407
Test name
Test status
Simulation time 435005467 ps
CPU time 16.17 seconds
Started Sep 18 02:58:40 PM UTC 24
Finished Sep 18 02:58:57 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984965464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3984965464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.3540419454
Short name T446
Test name
Test status
Simulation time 11066302867 ps
CPU time 1267.29 seconds
Started Sep 18 02:59:31 PM UTC 24
Finished Sep 18 03:20:53 PM UTC 24
Peak memory 299548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540419454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3540419454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.1915651924
Short name T405
Test name
Test status
Simulation time 24633042 ps
CPU time 4.69 seconds
Started Sep 18 02:58:33 PM UTC 24
Finished Sep 18 02:58:39 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915651924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1915651924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.2364151717
Short name T406
Test name
Test status
Simulation time 62568671 ps
CPU time 11.19 seconds
Started Sep 18 02:58:38 PM UTC 24
Finished Sep 18 02:58:51 PM UTC 24
Peak memory 264600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364151717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2364151717
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.2131561149
Short name T408
Test name
Test status
Simulation time 215961282 ps
CPU time 6.84 seconds
Started Sep 18 02:58:58 PM UTC 24
Finished Sep 18 02:59:06 PM UTC 24
Peak memory 262744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131561149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2131561149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.2561639423
Short name T403
Test name
Test status
Simulation time 185771283 ps
CPU time 11.18 seconds
Started Sep 18 02:58:20 PM UTC 24
Finished Sep 18 02:58:33 PM UTC 24
Peak memory 262480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561639423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2561639423
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/12.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.2355658409
Short name T243
Test name
Test status
Simulation time 13153221 ps
CPU time 3.81 seconds
Started Sep 18 03:02:14 PM UTC 24
Finished Sep 18 03:02:18 PM UTC 24
Peak memory 260704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355658409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2355658409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.1184206349
Short name T462
Test name
Test status
Simulation time 24268494479 ps
CPU time 1533.91 seconds
Started Sep 18 03:00:45 PM UTC 24
Finished Sep 18 03:26:36 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184206349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1184206349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.1098575601
Short name T415
Test name
Test status
Simulation time 242445757 ps
CPU time 11.89 seconds
Started Sep 18 03:01:59 PM UTC 24
Finished Sep 18 03:02:12 PM UTC 24
Peak memory 260436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098575601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1098575601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.168965643
Short name T418
Test name
Test status
Simulation time 4758985190 ps
CPU time 188.56 seconds
Started Sep 18 03:00:39 PM UTC 24
Finished Sep 18 03:03:50 PM UTC 24
Peak memory 266776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168965643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.168965643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.4156858243
Short name T412
Test name
Test status
Simulation time 259853249 ps
CPU time 9.77 seconds
Started Sep 18 03:00:29 PM UTC 24
Finished Sep 18 03:00:40 PM UTC 24
Peak memory 260500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156858243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.4156858243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.2460486093
Short name T123
Test name
Test status
Simulation time 477241465936 ps
CPU time 1946.24 seconds
Started Sep 18 03:01:42 PM UTC 24
Finished Sep 18 03:34:30 PM UTC 24
Peak memory 297428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460486093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2460486093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.1293314514
Short name T308
Test name
Test status
Simulation time 44135704627 ps
CPU time 187.21 seconds
Started Sep 18 03:01:10 PM UTC 24
Finished Sep 18 03:04:20 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293314514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1293314514
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.2634373773
Short name T411
Test name
Test status
Simulation time 149475582 ps
CPU time 18.65 seconds
Started Sep 18 03:00:18 PM UTC 24
Finished Sep 18 03:00:38 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634373773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2634373773
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.3801696115
Short name T109
Test name
Test status
Simulation time 3786623813 ps
CPU time 86.55 seconds
Started Sep 18 03:00:29 PM UTC 24
Finished Sep 18 03:01:58 PM UTC 24
Peak memory 260496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801696115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3801696115
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.2398974728
Short name T252
Test name
Test status
Simulation time 5872656056 ps
CPU time 56.98 seconds
Started Sep 18 03:00:41 PM UTC 24
Finished Sep 18 03:01:39 PM UTC 24
Peak memory 266772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398974728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2398974728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.393933702
Short name T413
Test name
Test status
Simulation time 1242043618 ps
CPU time 25.97 seconds
Started Sep 18 03:00:17 PM UTC 24
Finished Sep 18 03:00:44 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393933702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.393933702
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all_with_rand_reset.1270175825
Short name T64
Test name
Test status
Simulation time 4921611172 ps
CPU time 319.59 seconds
Started Sep 18 03:02:20 PM UTC 24
Finished Sep 18 03:07:44 PM UTC 24
Peak memory 277072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1270175825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.a
lert_handler_stress_all_with_rand_reset.1270175825
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.4254965409
Short name T347
Test name
Test status
Simulation time 49377399336 ps
CPU time 1534.2 seconds
Started Sep 18 03:03:43 PM UTC 24
Finished Sep 18 03:29:36 PM UTC 24
Peak memory 277024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254965409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.4254965409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.3204496643
Short name T420
Test name
Test status
Simulation time 155231312 ps
CPU time 7.69 seconds
Started Sep 18 03:04:21 PM UTC 24
Finished Sep 18 03:04:30 PM UTC 24
Peak memory 260508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204496643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3204496643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.3799122240
Short name T343
Test name
Test status
Simulation time 8135652369 ps
CPU time 188.28 seconds
Started Sep 18 03:03:32 PM UTC 24
Finished Sep 18 03:06:44 PM UTC 24
Peak memory 266712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799122240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3799122240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.2844754885
Short name T417
Test name
Test status
Simulation time 725115809 ps
CPU time 14.19 seconds
Started Sep 18 03:03:16 PM UTC 24
Finished Sep 18 03:03:31 PM UTC 24
Peak memory 260424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844754885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2844754885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.3053957487
Short name T298
Test name
Test status
Simulation time 34171862994 ps
CPU time 996.06 seconds
Started Sep 18 03:04:05 PM UTC 24
Finished Sep 18 03:20:53 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053957487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3053957487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.1341044380
Short name T474
Test name
Test status
Simulation time 88833303807 ps
CPU time 1520.96 seconds
Started Sep 18 03:04:16 PM UTC 24
Finished Sep 18 03:29:55 PM UTC 24
Peak memory 283164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341044380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1341044380
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.306895728
Short name T36
Test name
Test status
Simulation time 3877302567 ps
CPU time 141.78 seconds
Started Sep 18 03:03:52 PM UTC 24
Finished Sep 18 03:06:16 PM UTC 24
Peak memory 260572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306895728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.306895728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.2289915631
Short name T63
Test name
Test status
Simulation time 644033068 ps
CPU time 16.16 seconds
Started Sep 18 03:02:58 PM UTC 24
Finished Sep 18 03:03:15 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289915631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2289915631
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.2865914377
Short name T419
Test name
Test status
Simulation time 5146623941 ps
CPU time 61.51 seconds
Started Sep 18 03:03:12 PM UTC 24
Finished Sep 18 03:04:15 PM UTC 24
Peak memory 266736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865914377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2865914377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.793196480
Short name T320
Test name
Test status
Simulation time 3247576464 ps
CPU time 21.57 seconds
Started Sep 18 03:03:41 PM UTC 24
Finished Sep 18 03:04:03 PM UTC 24
Peak memory 266872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793196480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.793196480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.3719693625
Short name T416
Test name
Test status
Simulation time 639054959 ps
CPU time 24.75 seconds
Started Sep 18 03:02:31 PM UTC 24
Finished Sep 18 03:02:57 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719693625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3719693625
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.3945828213
Short name T507
Test name
Test status
Simulation time 118876142162 ps
CPU time 2141.7 seconds
Started Sep 18 03:04:31 PM UTC 24
Finished Sep 18 03:40:37 PM UTC 24
Peak memory 299480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945828213 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.3945828213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/14.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.3708518144
Short name T245
Test name
Test status
Simulation time 113386962 ps
CPU time 4.72 seconds
Started Sep 18 03:07:55 PM UTC 24
Finished Sep 18 03:08:01 PM UTC 24
Peak memory 260712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708518144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3708518144
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.2201367320
Short name T364
Test name
Test status
Simulation time 64743109620 ps
CPU time 957.72 seconds
Started Sep 18 03:06:50 PM UTC 24
Finished Sep 18 03:22:59 PM UTC 24
Peak memory 283096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201367320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2201367320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.231039706
Short name T425
Test name
Test status
Simulation time 257638893 ps
CPU time 8.72 seconds
Started Sep 18 03:07:45 PM UTC 24
Finished Sep 18 03:07:55 PM UTC 24
Peak memory 260580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231039706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.231039706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.3065037560
Short name T426
Test name
Test status
Simulation time 3854626155 ps
CPU time 83.05 seconds
Started Sep 18 03:06:45 PM UTC 24
Finished Sep 18 03:08:10 PM UTC 24
Peak memory 266668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065037560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3065037560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.1700157945
Short name T422
Test name
Test status
Simulation time 85058440 ps
CPU time 7.2 seconds
Started Sep 18 03:06:41 PM UTC 24
Finished Sep 18 03:06:49 PM UTC 24
Peak memory 260760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700157945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1700157945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.3848552535
Short name T297
Test name
Test status
Simulation time 11998286297 ps
CPU time 748.49 seconds
Started Sep 18 03:07:10 PM UTC 24
Finished Sep 18 03:19:49 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848552535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3848552535
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.3396408915
Short name T483
Test name
Test status
Simulation time 14615379388 ps
CPU time 1516.8 seconds
Started Sep 18 03:07:19 PM UTC 24
Finished Sep 18 03:32:55 PM UTC 24
Peak memory 299612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396408915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3396408915
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.2142444871
Short name T323
Test name
Test status
Simulation time 83360186173 ps
CPU time 687.76 seconds
Started Sep 18 03:06:54 PM UTC 24
Finished Sep 18 03:18:30 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142444871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2142444871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.2276135956
Short name T423
Test name
Test status
Simulation time 289365291 ps
CPU time 40.32 seconds
Started Sep 18 03:06:27 PM UTC 24
Finished Sep 18 03:07:09 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276135956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2276135956
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.3108154697
Short name T424
Test name
Test status
Simulation time 1291825403 ps
CPU time 65.64 seconds
Started Sep 18 03:06:38 PM UTC 24
Finished Sep 18 03:07:46 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108154697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3108154697
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.3418097050
Short name T271
Test name
Test status
Simulation time 3090658153 ps
CPU time 75.55 seconds
Started Sep 18 03:06:45 PM UTC 24
Finished Sep 18 03:08:02 PM UTC 24
Peak memory 266708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418097050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3418097050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.64498767
Short name T421
Test name
Test status
Simulation time 738206269 ps
CPU time 20.25 seconds
Started Sep 18 03:06:16 PM UTC 24
Finished Sep 18 03:06:38 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64498767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.64498767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.15721836
Short name T153
Test name
Test status
Simulation time 20420615362 ps
CPU time 2048.81 seconds
Started Sep 18 03:07:47 PM UTC 24
Finished Sep 18 03:42:19 PM UTC 24
Peak memory 312284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15721836 -assert nopostproc +UVM_TES
TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.15721836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all_with_rand_reset.2386154510
Short name T66
Test name
Test status
Simulation time 2532051127 ps
CPU time 159.36 seconds
Started Sep 18 03:08:01 PM UTC 24
Finished Sep 18 03:10:43 PM UTC 24
Peak memory 277272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2386154510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.a
lert_handler_stress_all_with_rand_reset.2386154510
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.58202293
Short name T246
Test name
Test status
Simulation time 40059307 ps
CPU time 5.32 seconds
Started Sep 18 03:10:21 PM UTC 24
Finished Sep 18 03:10:28 PM UTC 24
Peak memory 260772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58202293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h
andler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_h
andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.58202293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.1698365941
Short name T499
Test name
Test status
Simulation time 25844329674 ps
CPU time 1747.63 seconds
Started Sep 18 03:08:57 PM UTC 24
Finished Sep 18 03:38:25 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698365941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1698365941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.3878093985
Short name T431
Test name
Test status
Simulation time 514742860 ps
CPU time 11.41 seconds
Started Sep 18 03:09:30 PM UTC 24
Finished Sep 18 03:09:42 PM UTC 24
Peak memory 260436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878093985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3878093985
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.1277582245
Short name T429
Test name
Test status
Simulation time 96073887 ps
CPU time 8.4 seconds
Started Sep 18 03:08:47 PM UTC 24
Finished Sep 18 03:08:56 PM UTC 24
Peak memory 266604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277582245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1277582245
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.3616519515
Short name T100
Test name
Test status
Simulation time 1216777336 ps
CPU time 44.07 seconds
Started Sep 18 03:08:43 PM UTC 24
Finished Sep 18 03:09:28 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616519515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3616519515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.2362556333
Short name T362
Test name
Test status
Simulation time 79859533556 ps
CPU time 1957.14 seconds
Started Sep 18 03:09:02 PM UTC 24
Finished Sep 18 03:42:03 PM UTC 24
Peak memory 299740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362556333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2362556333
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.737165668
Short name T151
Test name
Test status
Simulation time 37416470510 ps
CPU time 760.46 seconds
Started Sep 18 03:09:10 PM UTC 24
Finished Sep 18 03:22:00 PM UTC 24
Peak memory 283096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737165668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.737165668
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.3006316748
Short name T113
Test name
Test status
Simulation time 7344309368 ps
CPU time 298.42 seconds
Started Sep 18 03:09:00 PM UTC 24
Finished Sep 18 03:14:03 PM UTC 24
Peak memory 260568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006316748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3006316748
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.1361078235
Short name T427
Test name
Test status
Simulation time 892761110 ps
CPU time 23.48 seconds
Started Sep 18 03:08:10 PM UTC 24
Finished Sep 18 03:08:35 PM UTC 24
Peak memory 260436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361078235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1361078235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.2213892239
Short name T65
Test name
Test status
Simulation time 129134614 ps
CPU time 16.22 seconds
Started Sep 18 03:08:36 PM UTC 24
Finished Sep 18 03:08:53 PM UTC 24
Peak memory 260536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213892239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2213892239
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.1767166977
Short name T430
Test name
Test status
Simulation time 184620017 ps
CPU time 4.27 seconds
Started Sep 18 03:08:54 PM UTC 24
Finished Sep 18 03:08:59 PM UTC 24
Peak memory 250188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767166977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1767166977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.2604512500
Short name T428
Test name
Test status
Simulation time 1551801781 ps
CPU time 37.52 seconds
Started Sep 18 03:08:03 PM UTC 24
Finished Sep 18 03:08:42 PM UTC 24
Peak memory 266840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604512500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2604512500
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all_with_rand_reset.1360703073
Short name T67
Test name
Test status
Simulation time 2009547719 ps
CPU time 300.2 seconds
Started Sep 18 03:10:28 PM UTC 24
Finished Sep 18 03:15:33 PM UTC 24
Peak memory 283088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1360703073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.a
lert_handler_stress_all_with_rand_reset.1360703073
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.893490064
Short name T247
Test name
Test status
Simulation time 25408636 ps
CPU time 4.91 seconds
Started Sep 18 03:15:06 PM UTC 24
Finished Sep 18 03:15:11 PM UTC 24
Peak memory 260704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893490064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.893490064
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.3838591170
Short name T497
Test name
Test status
Simulation time 19087069909 ps
CPU time 1482.14 seconds
Started Sep 18 03:13:09 PM UTC 24
Finished Sep 18 03:38:09 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838591170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3838591170
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.1938237542
Short name T435
Test name
Test status
Simulation time 391697525 ps
CPU time 14.55 seconds
Started Sep 18 03:14:47 PM UTC 24
Finished Sep 18 03:15:03 PM UTC 24
Peak memory 260700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938237542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1938237542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.1827089829
Short name T108
Test name
Test status
Simulation time 2870863796 ps
CPU time 201.53 seconds
Started Sep 18 03:12:29 PM UTC 24
Finished Sep 18 03:15:54 PM UTC 24
Peak memory 266636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827089829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1827089829
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.941291881
Short name T142
Test name
Test status
Simulation time 211549428 ps
CPU time 11.33 seconds
Started Sep 18 03:12:19 PM UTC 24
Finished Sep 18 03:12:32 PM UTC 24
Peak memory 264528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941291881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.941291881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.732599338
Short name T378
Test name
Test status
Simulation time 47408152217 ps
CPU time 1717.77 seconds
Started Sep 18 03:13:31 PM UTC 24
Finished Sep 18 03:42:28 PM UTC 24
Peak memory 283288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732599338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.732599338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.3157407613
Short name T492
Test name
Test status
Simulation time 47342445394 ps
CPU time 1317.72 seconds
Started Sep 18 03:14:04 PM UTC 24
Finished Sep 18 03:36:17 PM UTC 24
Peak memory 299476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157407613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3157407613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.1644711293
Short name T329
Test name
Test status
Simulation time 52456856576 ps
CPU time 369.63 seconds
Started Sep 18 03:13:13 PM UTC 24
Finished Sep 18 03:19:28 PM UTC 24
Peak memory 260828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644711293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1644711293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.2645695645
Short name T433
Test name
Test status
Simulation time 971737244 ps
CPU time 28.12 seconds
Started Sep 18 03:10:58 PM UTC 24
Finished Sep 18 03:11:27 PM UTC 24
Peak memory 266840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645695645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2645695645
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.3510539057
Short name T434
Test name
Test status
Simulation time 780620945 ps
CPU time 49.02 seconds
Started Sep 18 03:11:28 PM UTC 24
Finished Sep 18 03:12:18 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510539057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3510539057
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.1508754768
Short name T101
Test name
Test status
Simulation time 395289070 ps
CPU time 33.79 seconds
Started Sep 18 03:12:33 PM UTC 24
Finished Sep 18 03:13:08 PM UTC 24
Peak memory 266572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508754768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1508754768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.3792426085
Short name T432
Test name
Test status
Simulation time 554046671 ps
CPU time 11.58 seconds
Started Sep 18 03:10:43 PM UTC 24
Finished Sep 18 03:10:57 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792426085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3792426085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/17.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.840275396
Short name T248
Test name
Test status
Simulation time 82399815 ps
CPU time 3.61 seconds
Started Sep 18 03:17:28 PM UTC 24
Finished Sep 18 03:17:33 PM UTC 24
Peak memory 260704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840275396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.840275396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.681874728
Short name T146
Test name
Test status
Simulation time 129061508204 ps
CPU time 2255.55 seconds
Started Sep 18 03:16:18 PM UTC 24
Finished Sep 18 03:54:21 PM UTC 24
Peak memory 302128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681874728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.681874728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.2094615731
Short name T439
Test name
Test status
Simulation time 323857382 ps
CPU time 14.84 seconds
Started Sep 18 03:17:13 PM UTC 24
Finished Sep 18 03:17:29 PM UTC 24
Peak memory 260440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094615731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2094615731
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.3813677593
Short name T260
Test name
Test status
Simulation time 820496086 ps
CPU time 81.27 seconds
Started Sep 18 03:16:04 PM UTC 24
Finished Sep 18 03:17:28 PM UTC 24
Peak memory 266572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813677593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3813677593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.2633175595
Short name T102
Test name
Test status
Simulation time 1959465759 ps
CPU time 35.81 seconds
Started Sep 18 03:15:55 PM UTC 24
Finished Sep 18 03:16:32 PM UTC 24
Peak memory 266900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633175595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2633175595
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.3032602823
Short name T144
Test name
Test status
Simulation time 13282968935 ps
CPU time 1308 seconds
Started Sep 18 03:16:40 PM UTC 24
Finished Sep 18 03:38:43 PM UTC 24
Peak memory 293404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032602823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3032602823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.727363429
Short name T114
Test name
Test status
Simulation time 14037438490 ps
CPU time 743.44 seconds
Started Sep 18 03:16:30 PM UTC 24
Finished Sep 18 03:29:03 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727363429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.727363429
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.1757083323
Short name T436
Test name
Test status
Simulation time 220772934 ps
CPU time 28.48 seconds
Started Sep 18 03:15:34 PM UTC 24
Finished Sep 18 03:16:03 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757083323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1757083323
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.2979589771
Short name T337
Test name
Test status
Simulation time 1349545790 ps
CPU time 34.03 seconds
Started Sep 18 03:15:42 PM UTC 24
Finished Sep 18 03:16:17 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979589771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2979589771
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.1850626302
Short name T438
Test name
Test status
Simulation time 128402235 ps
CPU time 21.69 seconds
Started Sep 18 03:16:16 PM UTC 24
Finished Sep 18 03:16:39 PM UTC 24
Peak memory 266644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850626302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1850626302
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.615037303
Short name T437
Test name
Test status
Simulation time 1019966781 ps
CPU time 74.02 seconds
Started Sep 18 03:15:14 PM UTC 24
Finished Sep 18 03:16:30 PM UTC 24
Peak memory 266572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615037303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.615037303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.1758009406
Short name T103
Test name
Test status
Simulation time 967586512 ps
CPU time 116.99 seconds
Started Sep 18 03:17:16 PM UTC 24
Finished Sep 18 03:19:15 PM UTC 24
Peak memory 266652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758009406 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.1758009406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.1209876822
Short name T249
Test name
Test status
Simulation time 56145078 ps
CPU time 4.74 seconds
Started Sep 18 03:19:42 PM UTC 24
Finished Sep 18 03:19:48 PM UTC 24
Peak memory 260968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209876822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1209876822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.1059694533
Short name T131
Test name
Test status
Simulation time 13702503631 ps
CPU time 1534.42 seconds
Started Sep 18 03:19:01 PM UTC 24
Finished Sep 18 03:44:53 PM UTC 24
Peak memory 299552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059694533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1059694533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.2714712989
Short name T444
Test name
Test status
Simulation time 371917390 ps
CPU time 28.18 seconds
Started Sep 18 03:19:37 PM UTC 24
Finished Sep 18 03:20:06 PM UTC 24
Peak memory 260508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714712989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2714712989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.4064172672
Short name T454
Test name
Test status
Simulation time 26659417461 ps
CPU time 343.06 seconds
Started Sep 18 03:18:50 PM UTC 24
Finished Sep 18 03:24:39 PM UTC 24
Peak memory 266804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064172672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.4064172672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.4238109520
Short name T104
Test name
Test status
Simulation time 2288043942 ps
CPU time 50.05 seconds
Started Sep 18 03:18:31 PM UTC 24
Finished Sep 18 03:19:23 PM UTC 24
Peak memory 266904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238109520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.4238109520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.4062928349
Short name T365
Test name
Test status
Simulation time 32662055641 ps
CPU time 2096.49 seconds
Started Sep 18 03:19:24 PM UTC 24
Finished Sep 18 03:54:45 PM UTC 24
Peak memory 297956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062928349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.4062928349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.3596463877
Short name T510
Test name
Test status
Simulation time 11673707172 ps
CPU time 1338.93 seconds
Started Sep 18 03:19:29 PM UTC 24
Finished Sep 18 03:42:03 PM UTC 24
Peak memory 299740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596463877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3596463877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.1210391502
Short name T442
Test name
Test status
Simulation time 2147762933 ps
CPU time 77.36 seconds
Started Sep 18 03:18:20 PM UTC 24
Finished Sep 18 03:19:39 PM UTC 24
Peak memory 266904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210391502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1210391502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.2695050981
Short name T441
Test name
Test status
Simulation time 1040387598 ps
CPU time 35.74 seconds
Started Sep 18 03:18:23 PM UTC 24
Finished Sep 18 03:19:00 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695050981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2695050981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.2152896307
Short name T443
Test name
Test status
Simulation time 701242018 ps
CPU time 43.89 seconds
Started Sep 18 03:18:56 PM UTC 24
Finished Sep 18 03:19:41 PM UTC 24
Peak memory 260692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152896307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2152896307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.1740689240
Short name T440
Test name
Test status
Simulation time 674099589 ps
CPU time 42.39 seconds
Started Sep 18 03:17:34 PM UTC 24
Finished Sep 18 03:18:18 PM UTC 24
Peak memory 266904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740689240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1740689240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.1891574583
Short name T550
Test name
Test status
Simulation time 29802629758 ps
CPU time 2041.62 seconds
Started Sep 18 03:19:40 PM UTC 24
Finished Sep 18 03:54:06 PM UTC 24
Peak memory 297956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891574583 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.1891574583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/19.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.668109680
Short name T8
Test name
Test status
Simulation time 1456203738 ps
CPU time 26.65 seconds
Started Sep 18 02:49:14 PM UTC 24
Finished Sep 18 02:49:45 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668109680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.668109680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.3741934127
Short name T13
Test name
Test status
Simulation time 958438096 ps
CPU time 25.31 seconds
Started Sep 18 02:48:55 PM UTC 24
Finished Sep 18 02:49:21 PM UTC 24
Peak memory 266572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741934127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3741934127
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.834008334
Short name T294
Test name
Test status
Simulation time 19236366842 ps
CPU time 1182.33 seconds
Started Sep 18 02:49:12 PM UTC 24
Finished Sep 18 03:09:08 PM UTC 24
Peak memory 283088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834008334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.834008334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.641461691
Short name T445
Test name
Test status
Simulation time 30736209513 ps
CPU time 1859.59 seconds
Started Sep 18 02:49:13 PM UTC 24
Finished Sep 18 03:20:33 PM UTC 24
Peak memory 299744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641461691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.641461691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.1662893327
Short name T21
Test name
Test status
Simulation time 23216529565 ps
CPU time 341.43 seconds
Started Sep 18 02:48:58 PM UTC 24
Finished Sep 18 02:54:44 PM UTC 24
Peak memory 266712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662893327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1662893327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.2661861466
Short name T52
Test name
Test status
Simulation time 1951116782 ps
CPU time 46.51 seconds
Started Sep 18 02:48:45 PM UTC 24
Finished Sep 18 02:49:33 PM UTC 24
Peak memory 266572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661861466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2661861466
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.2013014749
Short name T17
Test name
Test status
Simulation time 17178813 ps
CPU time 4.11 seconds
Started Sep 18 02:48:49 PM UTC 24
Finished Sep 18 02:48:54 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013014749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2013014749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.959710714
Short name T51
Test name
Test status
Simulation time 4053807861 ps
CPU time 26.5 seconds
Started Sep 18 02:48:43 PM UTC 24
Finished Sep 18 02:49:11 PM UTC 24
Peak memory 266712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959710714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.959710714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.878290918
Short name T356
Test name
Test status
Simulation time 62546462296 ps
CPU time 3692.63 seconds
Started Sep 18 02:49:19 PM UTC 24
Finished Sep 18 03:51:32 PM UTC 24
Peak memory 316388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878290918 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.878290918
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/2.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.1506503516
Short name T539
Test name
Test status
Simulation time 41874508366 ps
CPU time 1790.72 seconds
Started Sep 18 03:20:57 PM UTC 24
Finished Sep 18 03:51:08 PM UTC 24
Peak memory 283172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506503516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1506503516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.3000885556
Short name T459
Test name
Test status
Simulation time 3820992183 ps
CPU time 313.98 seconds
Started Sep 18 03:20:43 PM UTC 24
Finished Sep 18 03:26:01 PM UTC 24
Peak memory 262580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000885556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3000885556
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.2845276930
Short name T447
Test name
Test status
Simulation time 262572901 ps
CPU time 35.94 seconds
Started Sep 18 03:20:35 PM UTC 24
Finished Sep 18 03:21:13 PM UTC 24
Peak memory 260692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845276930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2845276930
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.406038382
Short name T366
Test name
Test status
Simulation time 21244546584 ps
CPU time 1310.06 seconds
Started Sep 18 03:21:17 PM UTC 24
Finished Sep 18 03:43:23 PM UTC 24
Peak memory 283160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406038382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.406038382
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.2974400845
Short name T503
Test name
Test status
Simulation time 67891516316 ps
CPU time 1055.53 seconds
Started Sep 18 03:21:24 PM UTC 24
Finished Sep 18 03:39:13 PM UTC 24
Peak memory 283164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974400845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2974400845
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.1512563288
Short name T322
Test name
Test status
Simulation time 16593103458 ps
CPU time 544.99 seconds
Started Sep 18 03:21:14 PM UTC 24
Finished Sep 18 03:30:26 PM UTC 24
Peak memory 260832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512563288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1512563288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.2536734874
Short name T68
Test name
Test status
Simulation time 1595820791 ps
CPU time 33.24 seconds
Started Sep 18 03:20:07 PM UTC 24
Finished Sep 18 03:20:42 PM UTC 24
Peak memory 266584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536734874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2536734874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.3882517782
Short name T350
Test name
Test status
Simulation time 1861946240 ps
CPU time 49.03 seconds
Started Sep 18 03:20:33 PM UTC 24
Finished Sep 18 03:21:23 PM UTC 24
Peak memory 266608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882517782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3882517782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.165005085
Short name T265
Test name
Test status
Simulation time 1036228888 ps
CPU time 82.26 seconds
Started Sep 18 03:20:57 PM UTC 24
Finished Sep 18 03:22:21 PM UTC 24
Peak memory 260436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165005085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.165005085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.33842024
Short name T448
Test name
Test status
Simulation time 1132268649 ps
CPU time 82.96 seconds
Started Sep 18 03:19:51 PM UTC 24
Finished Sep 18 03:21:16 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33842024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.33842024
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.4173442966
Short name T351
Test name
Test status
Simulation time 4130992382 ps
CPU time 288.35 seconds
Started Sep 18 03:21:39 PM UTC 24
Finished Sep 18 03:26:32 PM UTC 24
Peak memory 283224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4173442966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a
lert_handler_stress_all_with_rand_reset.4173442966
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.3914262711
Short name T522
Test name
Test status
Simulation time 24054312546 ps
CPU time 1416.87 seconds
Started Sep 18 03:22:27 PM UTC 24
Finished Sep 18 03:46:20 PM UTC 24
Peak memory 283364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914262711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3914262711
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.2898637936
Short name T467
Test name
Test status
Simulation time 5765196495 ps
CPU time 343.5 seconds
Started Sep 18 03:22:15 PM UTC 24
Finished Sep 18 03:28:03 PM UTC 24
Peak memory 266728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898637936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2898637936
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.1477924861
Short name T452
Test name
Test status
Simulation time 164264279 ps
CPU time 21.86 seconds
Started Sep 18 03:22:14 PM UTC 24
Finished Sep 18 03:22:37 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477924861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1477924861
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.3561380244
Short name T368
Test name
Test status
Simulation time 251670257807 ps
CPU time 2426.62 seconds
Started Sep 18 03:22:43 PM UTC 24
Finished Sep 18 04:03:37 PM UTC 24
Peak memory 295912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561380244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3561380244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.2950119709
Short name T578
Test name
Test status
Simulation time 80955413393 ps
CPU time 2231.12 seconds
Started Sep 18 03:22:47 PM UTC 24
Finished Sep 18 04:00:22 PM UTC 24
Peak memory 295908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950119709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2950119709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.2099697418
Short name T453
Test name
Test status
Simulation time 1976530954 ps
CPU time 41.2 seconds
Started Sep 18 03:22:04 PM UTC 24
Finished Sep 18 03:22:46 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099697418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2099697418
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.4082093906
Short name T451
Test name
Test status
Simulation time 84357724 ps
CPU time 9.14 seconds
Started Sep 18 03:22:04 PM UTC 24
Finished Sep 18 03:22:14 PM UTC 24
Peak memory 250224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082093906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.4082093906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.1979768480
Short name T450
Test name
Test status
Simulation time 727753655 ps
CPU time 17.84 seconds
Started Sep 18 03:21:54 PM UTC 24
Finished Sep 18 03:22:13 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979768480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1979768480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all_with_rand_reset.3285171426
Short name T154
Test name
Test status
Simulation time 2612613886 ps
CPU time 208.97 seconds
Started Sep 18 03:23:39 PM UTC 24
Finished Sep 18 03:27:11 PM UTC 24
Peak memory 283224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3285171426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.a
lert_handler_stress_all_with_rand_reset.3285171426
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.4076423632
Short name T572
Test name
Test status
Simulation time 30227195486 ps
CPU time 1996.69 seconds
Started Sep 18 03:25:53 PM UTC 24
Finished Sep 18 03:59:32 PM UTC 24
Peak memory 295908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076423632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.4076423632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.2853232951
Short name T342
Test name
Test status
Simulation time 1508408308 ps
CPU time 45.51 seconds
Started Sep 18 03:25:22 PM UTC 24
Finished Sep 18 03:26:09 PM UTC 24
Peak memory 266612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853232951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2853232951
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.1084408379
Short name T460
Test name
Test status
Simulation time 6466947815 ps
CPU time 46.59 seconds
Started Sep 18 03:25:22 PM UTC 24
Finished Sep 18 03:26:10 PM UTC 24
Peak memory 260632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084408379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1084408379
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.1597373388
Short name T147
Test name
Test status
Simulation time 102571530989 ps
CPU time 1296.91 seconds
Started Sep 18 03:26:10 PM UTC 24
Finished Sep 18 03:48:01 PM UTC 24
Peak memory 283356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597373388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1597373388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.2563228704
Short name T111
Test name
Test status
Simulation time 15234136341 ps
CPU time 473.81 seconds
Started Sep 18 03:26:03 PM UTC 24
Finished Sep 18 03:34:04 PM UTC 24
Peak memory 260828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563228704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2563228704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.1118177225
Short name T456
Test name
Test status
Simulation time 36071956 ps
CPU time 6.16 seconds
Started Sep 18 03:25:13 PM UTC 24
Finished Sep 18 03:25:20 PM UTC 24
Peak memory 262584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118177225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1118177225
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.2251416134
Short name T457
Test name
Test status
Simulation time 184008927 ps
CPU time 4.58 seconds
Started Sep 18 03:25:15 PM UTC 24
Finished Sep 18 03:25:21 PM UTC 24
Peak memory 250192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251416134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2251416134
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.2167485386
Short name T461
Test name
Test status
Simulation time 11419363526 ps
CPU time 43.61 seconds
Started Sep 18 03:25:36 PM UTC 24
Finished Sep 18 03:26:21 PM UTC 24
Peak memory 266772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167485386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2167485386
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.276996048
Short name T458
Test name
Test status
Simulation time 15315618853 ps
CPU time 70.17 seconds
Started Sep 18 03:24:40 PM UTC 24
Finished Sep 18 03:25:52 PM UTC 24
Peak memory 266968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276996048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.276996048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all_with_rand_reset.4132932689
Short name T70
Test name
Test status
Simulation time 9320742799 ps
CPU time 220.03 seconds
Started Sep 18 03:26:16 PM UTC 24
Finished Sep 18 03:30:00 PM UTC 24
Peak memory 277144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4132932689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.a
lert_handler_stress_all_with_rand_reset.4132932689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.4022549496
Short name T549
Test name
Test status
Simulation time 66575991184 ps
CPU time 1573.88 seconds
Started Sep 18 03:27:11 PM UTC 24
Finished Sep 18 03:53:46 PM UTC 24
Peak memory 299552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022549496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.4022549496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.530067292
Short name T473
Test name
Test status
Simulation time 12656699774 ps
CPU time 166.45 seconds
Started Sep 18 03:26:58 PM UTC 24
Finished Sep 18 03:29:47 PM UTC 24
Peak memory 266968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530067292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.530067292
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.737589504
Short name T274
Test name
Test status
Simulation time 197690773 ps
CPU time 25.98 seconds
Started Sep 18 03:26:55 PM UTC 24
Finished Sep 18 03:27:22 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737589504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.737589504
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.2256523303
Short name T374
Test name
Test status
Simulation time 72173180701 ps
CPU time 2102.52 seconds
Started Sep 18 03:27:21 PM UTC 24
Finished Sep 18 04:02:46 PM UTC 24
Peak memory 302128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256523303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2256523303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.3711067206
Short name T577
Test name
Test status
Simulation time 64014201358 ps
CPU time 1949.92 seconds
Started Sep 18 03:27:23 PM UTC 24
Finished Sep 18 04:00:16 PM UTC 24
Peak memory 281044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711067206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3711067206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.3251174350
Short name T330
Test name
Test status
Simulation time 32101724023 ps
CPU time 277.15 seconds
Started Sep 18 03:27:19 PM UTC 24
Finished Sep 18 03:32:00 PM UTC 24
Peak memory 267040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251174350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3251174350
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.2518325060
Short name T464
Test name
Test status
Simulation time 248995567 ps
CPU time 23.32 seconds
Started Sep 18 03:26:33 PM UTC 24
Finished Sep 18 03:26:57 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518325060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2518325060
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.1389579017
Short name T129
Test name
Test status
Simulation time 239972339 ps
CPU time 25.21 seconds
Started Sep 18 03:26:38 PM UTC 24
Finished Sep 18 03:27:04 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389579017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1389579017
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.639215170
Short name T466
Test name
Test status
Simulation time 744274248 ps
CPU time 40.48 seconds
Started Sep 18 03:27:05 PM UTC 24
Finished Sep 18 03:27:47 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639215170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.639215170
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.2417516138
Short name T463
Test name
Test status
Simulation time 1808834279 ps
CPU time 30.75 seconds
Started Sep 18 03:26:22 PM UTC 24
Finished Sep 18 03:26:54 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417516138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2417516138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.1561812799
Short name T659
Test name
Test status
Simulation time 74668645064 ps
CPU time 3029.13 seconds
Started Sep 18 03:27:48 PM UTC 24
Finished Sep 18 04:18:53 PM UTC 24
Peak memory 318508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561812799 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.1561812799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/23.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.812418156
Short name T559
Test name
Test status
Simulation time 51566592721 ps
CPU time 1637.97 seconds
Started Sep 18 03:29:04 PM UTC 24
Finished Sep 18 03:56:42 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812418156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.812418156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.3951477887
Short name T480
Test name
Test status
Simulation time 11831932438 ps
CPU time 150.17 seconds
Started Sep 18 03:28:46 PM UTC 24
Finished Sep 18 03:31:19 PM UTC 24
Peak memory 266700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951477887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3951477887
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.3792873841
Short name T470
Test name
Test status
Simulation time 303781402 ps
CPU time 9.21 seconds
Started Sep 18 03:28:35 PM UTC 24
Finished Sep 18 03:28:45 PM UTC 24
Peak memory 266644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792873841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3792873841
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.3671406567
Short name T540
Test name
Test status
Simulation time 10992287817 ps
CPU time 1309.63 seconds
Started Sep 18 03:29:31 PM UTC 24
Finished Sep 18 03:51:36 PM UTC 24
Peak memory 299676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671406567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3671406567
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.523657198
Short name T324
Test name
Test status
Simulation time 7027480944 ps
CPU time 312.42 seconds
Started Sep 18 03:29:14 PM UTC 24
Finished Sep 18 03:34:31 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523657198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.523657198
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.4120556197
Short name T471
Test name
Test status
Simulation time 408311230 ps
CPU time 45.91 seconds
Started Sep 18 03:28:25 PM UTC 24
Finished Sep 18 03:29:13 PM UTC 24
Peak memory 266840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120556197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.4120556197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.3335384377
Short name T119
Test name
Test status
Simulation time 923195823 ps
CPU time 28.11 seconds
Started Sep 18 03:28:34 PM UTC 24
Finished Sep 18 03:29:03 PM UTC 24
Peak memory 266840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335384377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3335384377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.193469732
Short name T472
Test name
Test status
Simulation time 185014170 ps
CPU time 22.09 seconds
Started Sep 18 03:29:04 PM UTC 24
Finished Sep 18 03:29:28 PM UTC 24
Peak memory 266872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193469732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.193469732
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.768983745
Short name T469
Test name
Test status
Simulation time 269683771 ps
CPU time 10.48 seconds
Started Sep 18 03:28:13 PM UTC 24
Finished Sep 18 03:28:25 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768983745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.768983745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.2906836103
Short name T618
Test name
Test status
Simulation time 45142007133 ps
CPU time 2255.51 seconds
Started Sep 18 03:29:32 PM UTC 24
Finished Sep 18 04:07:33 PM UTC 24
Peak memory 302124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906836103 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.2906836103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/24.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.4081925785
Short name T598
Test name
Test status
Simulation time 53069721398 ps
CPU time 2009.49 seconds
Started Sep 18 03:30:21 PM UTC 24
Finished Sep 18 04:04:16 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081925785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4081925785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.2363001276
Short name T485
Test name
Test status
Simulation time 3977717370 ps
CPU time 175.49 seconds
Started Sep 18 03:30:10 PM UTC 24
Finished Sep 18 03:33:08 PM UTC 24
Peak memory 266740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363001276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2363001276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.800116098
Short name T475
Test name
Test status
Simulation time 54698218 ps
CPU time 7.12 seconds
Started Sep 18 03:30:01 PM UTC 24
Finished Sep 18 03:30:09 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800116098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.800116098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.1006019538
Short name T369
Test name
Test status
Simulation time 105426973261 ps
CPU time 1478.54 seconds
Started Sep 18 03:30:43 PM UTC 24
Finished Sep 18 03:55:38 PM UTC 24
Peak memory 278996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006019538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1006019538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.4179809145
Short name T548
Test name
Test status
Simulation time 25819553276 ps
CPU time 1310.83 seconds
Started Sep 18 03:31:07 PM UTC 24
Finished Sep 18 03:53:14 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179809145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.4179809145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.4045086903
Short name T327
Test name
Test status
Simulation time 31121197939 ps
CPU time 243.15 seconds
Started Sep 18 03:30:26 PM UTC 24
Finished Sep 18 03:34:33 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045086903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.4045086903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.1160459189
Short name T476
Test name
Test status
Simulation time 1128742924 ps
CPU time 28.85 seconds
Started Sep 18 03:29:49 PM UTC 24
Finished Sep 18 03:30:19 PM UTC 24
Peak memory 266616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160459189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1160459189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.2643048640
Short name T478
Test name
Test status
Simulation time 589815910 ps
CPU time 43.93 seconds
Started Sep 18 03:29:57 PM UTC 24
Finished Sep 18 03:30:42 PM UTC 24
Peak memory 260536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643048640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2643048640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.2403093859
Short name T481
Test name
Test status
Simulation time 594261348 ps
CPU time 59.8 seconds
Started Sep 18 03:30:20 PM UTC 24
Finished Sep 18 03:31:21 PM UTC 24
Peak memory 266904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403093859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2403093859
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.2250602224
Short name T477
Test name
Test status
Simulation time 1204949316 ps
CPU time 31.55 seconds
Started Sep 18 03:29:47 PM UTC 24
Finished Sep 18 03:30:20 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250602224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2250602224
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.2853869495
Short name T535
Test name
Test status
Simulation time 53039419682 ps
CPU time 1106.93 seconds
Started Sep 18 03:31:20 PM UTC 24
Finished Sep 18 03:50:00 PM UTC 24
Peak memory 295380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853869495 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.2853869495
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/25.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.301847034
Short name T620
Test name
Test status
Simulation time 114481801204 ps
CPU time 2063.56 seconds
Started Sep 18 03:32:59 PM UTC 24
Finished Sep 18 04:07:46 PM UTC 24
Peak memory 302384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301847034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.301847034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.2177047976
Short name T490
Test name
Test status
Simulation time 10539773367 ps
CPU time 159.43 seconds
Started Sep 18 03:32:45 PM UTC 24
Finished Sep 18 03:35:27 PM UTC 24
Peak memory 266996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177047976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2177047976
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.3139780962
Short name T486
Test name
Test status
Simulation time 5871869509 ps
CPU time 42.22 seconds
Started Sep 18 03:32:30 PM UTC 24
Finished Sep 18 03:33:14 PM UTC 24
Peak memory 266704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139780962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3139780962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.4240982503
Short name T672
Test name
Test status
Simulation time 179118141945 ps
CPU time 2906.39 seconds
Started Sep 18 03:33:09 PM UTC 24
Finished Sep 18 04:22:08 PM UTC 24
Peak memory 297960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240982503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4240982503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.3457393204
Short name T145
Test name
Test status
Simulation time 6108944677 ps
CPU time 641.83 seconds
Started Sep 18 03:33:14 PM UTC 24
Finished Sep 18 03:44:04 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457393204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3457393204
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.3341531962
Short name T326
Test name
Test status
Simulation time 12551898597 ps
CPU time 486.94 seconds
Started Sep 18 03:33:09 PM UTC 24
Finished Sep 18 03:41:22 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341531962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3341531962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.2960434228
Short name T482
Test name
Test status
Simulation time 330319025 ps
CPU time 8.15 seconds
Started Sep 18 03:32:09 PM UTC 24
Finished Sep 18 03:32:18 PM UTC 24
Peak memory 250200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960434228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2960434228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.3682961623
Short name T120
Test name
Test status
Simulation time 1683602669 ps
CPU time 46.92 seconds
Started Sep 18 03:32:19 PM UTC 24
Finished Sep 18 03:33:08 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682961623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3682961623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.2609808176
Short name T357
Test name
Test status
Simulation time 702883412 ps
CPU time 41.14 seconds
Started Sep 18 03:32:02 PM UTC 24
Finished Sep 18 03:32:44 PM UTC 24
Peak memory 266584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609808176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2609808176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.1744020837
Short name T117
Test name
Test status
Simulation time 12533488331 ps
CPU time 1312.91 seconds
Started Sep 18 03:33:14 PM UTC 24
Finished Sep 18 03:55:22 PM UTC 24
Peak memory 299548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744020837 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.1744020837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.932893458
Short name T613
Test name
Test status
Simulation time 514520624411 ps
CPU time 1908.15 seconds
Started Sep 18 03:34:34 PM UTC 24
Finished Sep 18 04:06:42 PM UTC 24
Peak memory 299552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932893458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.932893458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.3580719544
Short name T498
Test name
Test status
Simulation time 3081865403 ps
CPU time 214.82 seconds
Started Sep 18 03:34:32 PM UTC 24
Finished Sep 18 03:38:10 PM UTC 24
Peak memory 266740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580719544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3580719544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.1585479210
Short name T489
Test name
Test status
Simulation time 544915540 ps
CPU time 48.38 seconds
Started Sep 18 03:34:22 PM UTC 24
Finished Sep 18 03:35:12 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585479210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1585479210
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.2608383085
Short name T372
Test name
Test status
Simulation time 6201842370 ps
CPU time 650.9 seconds
Started Sep 18 03:34:42 PM UTC 24
Finished Sep 18 03:45:42 PM UTC 24
Peak memory 283096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608383085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2608383085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.3896092788
Short name T562
Test name
Test status
Simulation time 11872851098 ps
CPU time 1291.96 seconds
Started Sep 18 03:35:13 PM UTC 24
Finished Sep 18 03:57:01 PM UTC 24
Peak memory 299548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896092788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3896092788
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.1314200267
Short name T328
Test name
Test status
Simulation time 18244316188 ps
CPU time 306.24 seconds
Started Sep 18 03:34:38 PM UTC 24
Finished Sep 18 03:39:48 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314200267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1314200267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.947910568
Short name T487
Test name
Test status
Simulation time 678139248 ps
CPU time 14.77 seconds
Started Sep 18 03:34:05 PM UTC 24
Finished Sep 18 03:34:21 PM UTC 24
Peak memory 260428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947910568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.947910568
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.3159919189
Short name T72
Test name
Test status
Simulation time 1134647200 ps
CPU time 92.53 seconds
Started Sep 18 03:34:08 PM UTC 24
Finished Sep 18 03:35:42 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159919189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3159919189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.3305603662
Short name T491
Test name
Test status
Simulation time 1151183018 ps
CPU time 86.36 seconds
Started Sep 18 03:34:32 PM UTC 24
Finished Sep 18 03:36:00 PM UTC 24
Peak memory 266836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305603662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3305603662
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.1523540626
Short name T488
Test name
Test status
Simulation time 7525819542 ps
CPU time 42.91 seconds
Started Sep 18 03:33:53 PM UTC 24
Finished Sep 18 03:34:37 PM UTC 24
Peak memory 266704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523540626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1523540626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.1793077772
Short name T566
Test name
Test status
Simulation time 59707114541 ps
CPU time 1327.79 seconds
Started Sep 18 03:35:28 PM UTC 24
Finished Sep 18 03:57:51 PM UTC 24
Peak memory 297500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793077772 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.1793077772
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/27.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.2493394847
Short name T662
Test name
Test status
Simulation time 43119661002 ps
CPU time 2520.65 seconds
Started Sep 18 03:37:34 PM UTC 24
Finished Sep 18 04:20:03 PM UTC 24
Peak memory 302056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493394847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2493394847
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.3076160889
Short name T514
Test name
Test status
Simulation time 4882152042 ps
CPU time 337.92 seconds
Started Sep 18 03:37:19 PM UTC 24
Finished Sep 18 03:43:02 PM UTC 24
Peak memory 266700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076160889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3076160889
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.1889889885
Short name T502
Test name
Test status
Simulation time 1242887752 ps
CPU time 101.34 seconds
Started Sep 18 03:37:13 PM UTC 24
Finished Sep 18 03:38:56 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889889885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1889889885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.1063662695
Short name T376
Test name
Test status
Simulation time 77047016575 ps
CPU time 1016.1 seconds
Started Sep 18 03:37:55 PM UTC 24
Finished Sep 18 03:55:03 PM UTC 24
Peak memory 295456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063662695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1063662695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.175383921
Short name T588
Test name
Test status
Simulation time 53820127437 ps
CPU time 1415.27 seconds
Started Sep 18 03:38:07 PM UTC 24
Finished Sep 18 04:01:58 PM UTC 24
Peak memory 293404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175383921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.175383921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.3952453224
Short name T333
Test name
Test status
Simulation time 45852450055 ps
CPU time 468.34 seconds
Started Sep 18 03:37:51 PM UTC 24
Finished Sep 18 03:45:46 PM UTC 24
Peak memory 260828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952453224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3952453224
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.1434972568
Short name T495
Test name
Test status
Simulation time 3794909449 ps
CPU time 72.18 seconds
Started Sep 18 03:36:20 PM UTC 24
Finished Sep 18 03:37:34 PM UTC 24
Peak memory 260496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434972568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1434972568
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.3996165718
Short name T494
Test name
Test status
Simulation time 3617482427 ps
CPU time 24.09 seconds
Started Sep 18 03:36:53 PM UTC 24
Finished Sep 18 03:37:18 PM UTC 24
Peak memory 260760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996165718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3996165718
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.1979149838
Short name T496
Test name
Test status
Simulation time 664720096 ps
CPU time 26.65 seconds
Started Sep 18 03:37:22 PM UTC 24
Finished Sep 18 03:37:50 PM UTC 24
Peak memory 260500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979149838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1979149838
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.3929284829
Short name T493
Test name
Test status
Simulation time 4112485897 ps
CPU time 69.44 seconds
Started Sep 18 03:36:01 PM UTC 24
Finished Sep 18 03:37:12 PM UTC 24
Peak memory 266712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929284829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3929284829
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all_with_rand_reset.3521360087
Short name T508
Test name
Test status
Simulation time 1275121812 ps
CPU time 174.35 seconds
Started Sep 18 03:38:11 PM UTC 24
Finished Sep 18 03:41:08 PM UTC 24
Peak memory 283352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3521360087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.a
lert_handler_stress_all_with_rand_reset.3521360087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.3486808641
Short name T599
Test name
Test status
Simulation time 24813241717 ps
CPU time 1487.49 seconds
Started Sep 18 03:39:15 PM UTC 24
Finished Sep 18 04:04:19 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486808641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3486808641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.2508610803
Short name T506
Test name
Test status
Simulation time 1234538011 ps
CPU time 50.85 seconds
Started Sep 18 03:38:57 PM UTC 24
Finished Sep 18 03:39:49 PM UTC 24
Peak memory 266676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508610803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2508610803
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.1156446290
Short name T505
Test name
Test status
Simulation time 1365152525 ps
CPU time 38.12 seconds
Started Sep 18 03:38:54 PM UTC 24
Finished Sep 18 03:39:33 PM UTC 24
Peak memory 260424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156446290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1156446290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.3454221070
Short name T375
Test name
Test status
Simulation time 37125237464 ps
CPU time 1160.14 seconds
Started Sep 18 03:39:49 PM UTC 24
Finished Sep 18 03:59:22 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454221070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3454221070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.2565043234
Short name T586
Test name
Test status
Simulation time 76614563032 ps
CPU time 1280.12 seconds
Started Sep 18 03:39:50 PM UTC 24
Finished Sep 18 04:01:26 PM UTC 24
Peak memory 299476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565043234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2565043234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.3326594564
Short name T336
Test name
Test status
Simulation time 18248056197 ps
CPU time 428.45 seconds
Started Sep 18 03:39:35 PM UTC 24
Finished Sep 18 03:46:49 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326594564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3326594564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.1788985075
Short name T501
Test name
Test status
Simulation time 43023838 ps
CPU time 5.92 seconds
Started Sep 18 03:38:45 PM UTC 24
Finished Sep 18 03:38:52 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788985075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1788985075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.2999272275
Short name T504
Test name
Test status
Simulation time 193135727 ps
CPU time 26.66 seconds
Started Sep 18 03:38:47 PM UTC 24
Finished Sep 18 03:39:15 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999272275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2999272275
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.3270819126
Short name T279
Test name
Test status
Simulation time 586421551 ps
CPU time 49.64 seconds
Started Sep 18 03:39:15 PM UTC 24
Finished Sep 18 03:40:07 PM UTC 24
Peak memory 266644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270819126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3270819126
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.2115919070
Short name T500
Test name
Test status
Simulation time 166995164 ps
CPU time 17.77 seconds
Started Sep 18 03:38:27 PM UTC 24
Finished Sep 18 03:38:46 PM UTC 24
Peak memory 264792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115919070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2115919070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.3630034219
Short name T552
Test name
Test status
Simulation time 12097837840 ps
CPU time 837.61 seconds
Started Sep 18 03:40:08 PM UTC 24
Finished Sep 18 03:54:16 PM UTC 24
Peak memory 281308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630034219 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.3630034219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/29.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.4275733835
Short name T75
Test name
Test status
Simulation time 59841678 ps
CPU time 3.39 seconds
Started Sep 18 02:50:11 PM UTC 24
Finished Sep 18 02:50:15 PM UTC 24
Peak memory 260700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275733835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4275733835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.3763258805
Short name T532
Test name
Test status
Simulation time 227917043278 ps
CPU time 3520.14 seconds
Started Sep 18 02:49:45 PM UTC 24
Finished Sep 18 03:49:06 PM UTC 24
Peak memory 302052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763258805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3763258805
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.3883579746
Short name T22
Test name
Test status
Simulation time 93013516 ps
CPU time 10.33 seconds
Started Sep 18 02:49:59 PM UTC 24
Finished Sep 18 02:50:11 PM UTC 24
Peak memory 260428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883579746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3883579746
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.398246026
Short name T56
Test name
Test status
Simulation time 5918559224 ps
CPU time 181.3 seconds
Started Sep 18 02:49:44 PM UTC 24
Finished Sep 18 02:52:48 PM UTC 24
Peak memory 266776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398246026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.398246026
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.179938215
Short name T73
Test name
Test status
Simulation time 438943830 ps
CPU time 34.12 seconds
Started Sep 18 02:49:38 PM UTC 24
Finished Sep 18 02:50:13 PM UTC 24
Peak memory 260460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179938215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.179938215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.2987380754
Short name T379
Test name
Test status
Simulation time 29470364256 ps
CPU time 1719.5 seconds
Started Sep 18 02:49:54 PM UTC 24
Finished Sep 18 03:18:54 PM UTC 24
Peak memory 283360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987380754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2987380754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.1135140736
Short name T136
Test name
Test status
Simulation time 7647020223 ps
CPU time 373.96 seconds
Started Sep 18 02:49:45 PM UTC 24
Finished Sep 18 02:56:04 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135140736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1135140736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.3560417790
Short name T34
Test name
Test status
Simulation time 260438877 ps
CPU time 37.38 seconds
Started Sep 18 02:49:33 PM UTC 24
Finished Sep 18 02:50:11 PM UTC 24
Peak memory 260500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560417790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3560417790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.2411919804
Short name T31
Test name
Test status
Simulation time 1017683078 ps
CPU time 33.88 seconds
Started Sep 18 02:49:34 PM UTC 24
Finished Sep 18 02:50:09 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411919804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2411919804
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.2304655432
Short name T74
Test name
Test status
Simulation time 642324177 ps
CPU time 27.07 seconds
Started Sep 18 02:49:45 PM UTC 24
Finished Sep 18 02:50:14 PM UTC 24
Peak memory 266840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304655432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2304655432
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.3792367692
Short name T77
Test name
Test status
Simulation time 1112875670 ps
CPU time 86.66 seconds
Started Sep 18 02:49:25 PM UTC 24
Finished Sep 18 02:50:56 PM UTC 24
Peak memory 266836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792367692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3792367692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.3999872112
Short name T150
Test name
Test status
Simulation time 431635081891 ps
CPU time 2609.21 seconds
Started Sep 18 02:50:07 PM UTC 24
Finished Sep 18 03:34:05 PM UTC 24
Peak memory 318436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999872112 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.3999872112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.3879430042
Short name T554
Test name
Test status
Simulation time 39326283895 ps
CPU time 752.3 seconds
Started Sep 18 03:42:22 PM UTC 24
Finished Sep 18 03:55:04 PM UTC 24
Peak memory 279008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879430042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3879430042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.398835037
Short name T518
Test name
Test status
Simulation time 7391409758 ps
CPU time 176.6 seconds
Started Sep 18 03:42:07 PM UTC 24
Finished Sep 18 03:45:07 PM UTC 24
Peak memory 266968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398835037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.398835037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.2708641192
Short name T512
Test name
Test status
Simulation time 290514647 ps
CPU time 27.84 seconds
Started Sep 18 03:42:07 PM UTC 24
Finished Sep 18 03:42:37 PM UTC 24
Peak memory 266644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708641192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2708641192
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.2020711779
Short name T622
Test name
Test status
Simulation time 112454621630 ps
CPU time 1504.8 seconds
Started Sep 18 03:42:37 PM UTC 24
Finished Sep 18 04:07:59 PM UTC 24
Peak memory 299552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020711779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2020711779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.2614464557
Short name T602
Test name
Test status
Simulation time 26790569983 ps
CPU time 1315.77 seconds
Started Sep 18 03:42:39 PM UTC 24
Finished Sep 18 04:04:51 PM UTC 24
Peak memory 297696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614464557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2614464557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.2737291143
Short name T334
Test name
Test status
Simulation time 11338321863 ps
CPU time 479.85 seconds
Started Sep 18 03:42:30 PM UTC 24
Finished Sep 18 03:50:36 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737291143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2737291143
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.3072067337
Short name T509
Test name
Test status
Simulation time 226145810 ps
CPU time 22.57 seconds
Started Sep 18 03:41:23 PM UTC 24
Finished Sep 18 03:41:47 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072067337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3072067337
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.2790375816
Short name T130
Test name
Test status
Simulation time 1007562561 ps
CPU time 48.52 seconds
Started Sep 18 03:41:49 PM UTC 24
Finished Sep 18 03:42:39 PM UTC 24
Peak memory 260536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790375816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2790375816
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.131312371
Short name T513
Test name
Test status
Simulation time 2982691922 ps
CPU time 47.77 seconds
Started Sep 18 03:42:09 PM UTC 24
Finished Sep 18 03:42:59 PM UTC 24
Peak memory 260600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131312371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.131312371
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.2722615352
Short name T511
Test name
Test status
Simulation time 1438473089 ps
CPU time 57.72 seconds
Started Sep 18 03:41:09 PM UTC 24
Finished Sep 18 03:42:08 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722615352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2722615352
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.682674066
Short name T706
Test name
Test status
Simulation time 687105339508 ps
CPU time 3786.24 seconds
Started Sep 18 03:43:00 PM UTC 24
Finished Sep 18 04:46:47 PM UTC 24
Peak memory 302124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682674066 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.682674066
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.1191935013
Short name T128
Test name
Test status
Simulation time 2569100189 ps
CPU time 312.84 seconds
Started Sep 18 03:43:03 PM UTC 24
Finished Sep 18 03:48:20 PM UTC 24
Peak memory 277080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1191935013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.a
lert_handler_stress_all_with_rand_reset.1191935013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.1369759961
Short name T596
Test name
Test status
Simulation time 10379906535 ps
CPU time 1102.95 seconds
Started Sep 18 03:44:56 PM UTC 24
Finished Sep 18 04:03:33 PM UTC 24
Peak memory 293408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369759961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1369759961
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.1329329681
Short name T261
Test name
Test status
Simulation time 1672825230 ps
CPU time 108.76 seconds
Started Sep 18 03:44:31 PM UTC 24
Finished Sep 18 03:46:22 PM UTC 24
Peak memory 266868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329329681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1329329681
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.1671767205
Short name T519
Test name
Test status
Simulation time 1433357641 ps
CPU time 39.74 seconds
Started Sep 18 03:44:26 PM UTC 24
Finished Sep 18 03:45:07 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671767205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1671767205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.1617308115
Short name T634
Test name
Test status
Simulation time 28303976580 ps
CPU time 1556.36 seconds
Started Sep 18 03:45:08 PM UTC 24
Finished Sep 18 04:11:22 PM UTC 24
Peak memory 277024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617308115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1617308115
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.1388077341
Short name T565
Test name
Test status
Simulation time 36063390458 ps
CPU time 720.67 seconds
Started Sep 18 03:45:27 PM UTC 24
Finished Sep 18 03:57:37 PM UTC 24
Peak memory 283356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388077341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1388077341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.3524648074
Short name T534
Test name
Test status
Simulation time 12078611286 ps
CPU time 274.48 seconds
Started Sep 18 03:45:08 PM UTC 24
Finished Sep 18 03:49:46 PM UTC 24
Peak memory 266712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524648074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3524648074
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.3857003046
Short name T517
Test name
Test status
Simulation time 608909385 ps
CPU time 50.36 seconds
Started Sep 18 03:43:53 PM UTC 24
Finished Sep 18 03:44:45 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857003046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3857003046
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.2032296152
Short name T112
Test name
Test status
Simulation time 234183338 ps
CPU time 18.33 seconds
Started Sep 18 03:44:06 PM UTC 24
Finished Sep 18 03:44:26 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032296152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2032296152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.2353391933
Short name T520
Test name
Test status
Simulation time 1196030306 ps
CPU time 38.55 seconds
Started Sep 18 03:44:46 PM UTC 24
Finished Sep 18 03:45:26 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353391933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2353391933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.2638555736
Short name T515
Test name
Test status
Simulation time 271456506 ps
CPU time 26.18 seconds
Started Sep 18 03:43:25 PM UTC 24
Finished Sep 18 03:43:53 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638555736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2638555736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all_with_rand_reset.547343673
Short name T254
Test name
Test status
Simulation time 12384591845 ps
CPU time 242.09 seconds
Started Sep 18 03:45:47 PM UTC 24
Finished Sep 18 03:49:52 PM UTC 24
Peak memory 277144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=547343673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.al
ert_handler_stress_all_with_rand_reset.547343673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.548250655
Short name T671
Test name
Test status
Simulation time 64983586417 ps
CPU time 2104.14 seconds
Started Sep 18 03:46:40 PM UTC 24
Finished Sep 18 04:22:07 PM UTC 24
Peak memory 302052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548250655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.548250655
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.2472903345
Short name T524
Test name
Test status
Simulation time 487656208 ps
CPU time 15.41 seconds
Started Sep 18 03:46:23 PM UTC 24
Finished Sep 18 03:46:39 PM UTC 24
Peak memory 266868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472903345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2472903345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.3012632033
Short name T526
Test name
Test status
Simulation time 7871988758 ps
CPU time 75.69 seconds
Started Sep 18 03:46:23 PM UTC 24
Finished Sep 18 03:47:40 PM UTC 24
Peak memory 260632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012632033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3012632033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.2565613208
Short name T688
Test name
Test status
Simulation time 68375656514 ps
CPU time 2551.13 seconds
Started Sep 18 03:47:00 PM UTC 24
Finished Sep 18 04:30:01 PM UTC 24
Peak memory 302056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565613208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2565613208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.2644450330
Short name T325
Test name
Test status
Simulation time 15983096774 ps
CPU time 150.4 seconds
Started Sep 18 03:46:50 PM UTC 24
Finished Sep 18 03:49:23 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644450330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2644450330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.2332136393
Short name T523
Test name
Test status
Simulation time 388881591 ps
CPU time 34.72 seconds
Started Sep 18 03:46:03 PM UTC 24
Finished Sep 18 03:46:39 PM UTC 24
Peak memory 260464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332136393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2332136393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.2872788782
Short name T525
Test name
Test status
Simulation time 2281040362 ps
CPU time 50.18 seconds
Started Sep 18 03:46:16 PM UTC 24
Finished Sep 18 03:47:08 PM UTC 24
Peak memory 260496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872788782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2872788782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.2248748723
Short name T155
Test name
Test status
Simulation time 470833689 ps
CPU time 18.59 seconds
Started Sep 18 03:46:40 PM UTC 24
Finished Sep 18 03:47:00 PM UTC 24
Peak memory 260428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248748723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2248748723
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.1740548864
Short name T521
Test name
Test status
Simulation time 60509087 ps
CPU time 9.71 seconds
Started Sep 18 03:45:51 PM UTC 24
Finished Sep 18 03:46:02 PM UTC 24
Peak memory 266840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740548864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1740548864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.1160205540
Short name T527
Test name
Test status
Simulation time 335863163 ps
CPU time 40.7 seconds
Started Sep 18 03:47:19 PM UTC 24
Finished Sep 18 03:48:01 PM UTC 24
Peak memory 266580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160205540 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.1160205540
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.4070057663
Short name T701
Test name
Test status
Simulation time 54900285236 ps
CPU time 3216.02 seconds
Started Sep 18 03:49:05 PM UTC 24
Finished Sep 18 04:43:16 PM UTC 24
Peak memory 302056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070057663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4070057663
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.848692839
Short name T544
Test name
Test status
Simulation time 16994021526 ps
CPU time 252.41 seconds
Started Sep 18 03:48:26 PM UTC 24
Finished Sep 18 03:52:42 PM UTC 24
Peak memory 266704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848692839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.848692839
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.4196059380
Short name T531
Test name
Test status
Simulation time 1973054199 ps
CPU time 41.21 seconds
Started Sep 18 03:48:21 PM UTC 24
Finished Sep 18 03:49:04 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196059380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.4196059380
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.268236957
Short name T650
Test name
Test status
Simulation time 67898324476 ps
CPU time 1556.41 seconds
Started Sep 18 03:49:09 PM UTC 24
Finished Sep 18 04:15:23 PM UTC 24
Peak memory 299472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268236957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.268236957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.366139018
Short name T528
Test name
Test status
Simulation time 284506084 ps
CPU time 12.96 seconds
Started Sep 18 03:48:04 PM UTC 24
Finished Sep 18 03:48:18 PM UTC 24
Peak memory 264600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366139018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.366139018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.1277804700
Short name T529
Test name
Test status
Simulation time 62346565 ps
CPU time 11.17 seconds
Started Sep 18 03:48:19 PM UTC 24
Finished Sep 18 03:48:31 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277804700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1277804700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.1830021636
Short name T533
Test name
Test status
Simulation time 3175977839 ps
CPU time 68.7 seconds
Started Sep 18 03:48:32 PM UTC 24
Finished Sep 18 03:49:43 PM UTC 24
Peak memory 260496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830021636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1830021636
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.4146029299
Short name T530
Test name
Test status
Simulation time 4051218805 ps
CPU time 57.88 seconds
Started Sep 18 03:48:04 PM UTC 24
Finished Sep 18 03:49:03 PM UTC 24
Peak memory 266968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146029299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4146029299
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.902579897
Short name T358
Test name
Test status
Simulation time 32654129205 ps
CPU time 2341.98 seconds
Started Sep 18 03:49:44 PM UTC 24
Finished Sep 18 04:29:13 PM UTC 24
Peak memory 302052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902579897 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.902579897
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all_with_rand_reset.1178789711
Short name T574
Test name
Test status
Simulation time 4937922770 ps
CPU time 605.16 seconds
Started Sep 18 03:49:47 PM UTC 24
Finished Sep 18 04:00:00 PM UTC 24
Peak memory 283288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1178789711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.a
lert_handler_stress_all_with_rand_reset.1178789711
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.3788123277
Short name T642
Test name
Test status
Simulation time 116547577316 ps
CPU time 1333.94 seconds
Started Sep 18 03:50:38 PM UTC 24
Finished Sep 18 04:13:07 PM UTC 24
Peak memory 279328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788123277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3788123277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.1601112336
Short name T547
Test name
Test status
Simulation time 18011792233 ps
CPU time 159.79 seconds
Started Sep 18 03:50:29 PM UTC 24
Finished Sep 18 03:53:11 PM UTC 24
Peak memory 266708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601112336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1601112336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.1899625064
Short name T538
Test name
Test status
Simulation time 682077477 ps
CPU time 43.39 seconds
Started Sep 18 03:50:03 PM UTC 24
Finished Sep 18 03:50:48 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899625064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1899625064
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.1912092375
Short name T609
Test name
Test status
Simulation time 40107611288 ps
CPU time 913.63 seconds
Started Sep 18 03:50:48 PM UTC 24
Finished Sep 18 04:06:13 PM UTC 24
Peak memory 283360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912092375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1912092375
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.1940449452
Short name T685
Test name
Test status
Simulation time 144242328723 ps
CPU time 2155.55 seconds
Started Sep 18 03:51:10 PM UTC 24
Finished Sep 18 04:27:31 PM UTC 24
Peak memory 302052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940449452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1940449452
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.1486518967
Short name T332
Test name
Test status
Simulation time 5857917372 ps
CPU time 232.52 seconds
Started Sep 18 03:50:39 PM UTC 24
Finished Sep 18 03:54:35 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486518967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1486518967
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.3856906356
Short name T536
Test name
Test status
Simulation time 2114846416 ps
CPU time 42.32 seconds
Started Sep 18 03:49:53 PM UTC 24
Finished Sep 18 03:50:37 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856906356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3856906356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.2062131172
Short name T148
Test name
Test status
Simulation time 5082206207 ps
CPU time 26.93 seconds
Started Sep 18 03:50:00 PM UTC 24
Finished Sep 18 03:50:28 PM UTC 24
Peak memory 260560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062131172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2062131172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.1812521896
Short name T264
Test name
Test status
Simulation time 236071539 ps
CPU time 38.34 seconds
Started Sep 18 03:50:37 PM UTC 24
Finished Sep 18 03:51:17 PM UTC 24
Peak memory 266572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812521896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1812521896
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.2477137898
Short name T537
Test name
Test status
Simulation time 552701883 ps
CPU time 48.79 seconds
Started Sep 18 03:49:48 PM UTC 24
Finished Sep 18 03:50:38 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477137898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2477137898
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.2363475643
Short name T684
Test name
Test status
Simulation time 22873675100 ps
CPU time 2143.79 seconds
Started Sep 18 03:51:18 PM UTC 24
Finished Sep 18 04:27:26 PM UTC 24
Peak memory 318508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363475643 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.2363475643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all_with_rand_reset.4061647833
Short name T121
Test name
Test status
Simulation time 1873669594 ps
CPU time 187.12 seconds
Started Sep 18 03:51:35 PM UTC 24
Finished Sep 18 03:54:46 PM UTC 24
Peak memory 276944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4061647833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.a
lert_handler_stress_all_with_rand_reset.4061647833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.633523131
Short name T677
Test name
Test status
Simulation time 113188702526 ps
CPU time 1816.82 seconds
Started Sep 18 03:52:22 PM UTC 24
Finished Sep 18 04:23:00 PM UTC 24
Peak memory 299808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633523131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.633523131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.1542626761
Short name T543
Test name
Test status
Simulation time 445590973 ps
CPU time 7.91 seconds
Started Sep 18 03:52:12 PM UTC 24
Finished Sep 18 03:52:21 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542626761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1542626761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.166565635
Short name T545
Test name
Test status
Simulation time 1050914979 ps
CPU time 42.88 seconds
Started Sep 18 03:52:04 PM UTC 24
Finished Sep 18 03:52:48 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166565635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.166565635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.65484879
Short name T636
Test name
Test status
Simulation time 41688370834 ps
CPU time 1118.93 seconds
Started Sep 18 03:52:49 PM UTC 24
Finished Sep 18 04:11:43 PM UTC 24
Peak memory 293404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65484879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.65484879
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.2002808637
Short name T661
Test name
Test status
Simulation time 50111381222 ps
CPU time 1568.44 seconds
Started Sep 18 03:52:56 PM UTC 24
Finished Sep 18 04:19:24 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002808637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2002808637
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.707769300
Short name T541
Test name
Test status
Simulation time 264732388 ps
CPU time 22.57 seconds
Started Sep 18 03:51:40 PM UTC 24
Finished Sep 18 03:52:03 PM UTC 24
Peak memory 260500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707769300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.707769300
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.191299506
Short name T133
Test name
Test status
Simulation time 740696957 ps
CPU time 27.31 seconds
Started Sep 18 03:51:43 PM UTC 24
Finished Sep 18 03:52:12 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191299506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.191299506
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.1213040625
Short name T546
Test name
Test status
Simulation time 811633000 ps
CPU time 36.49 seconds
Started Sep 18 03:52:17 PM UTC 24
Finished Sep 18 03:52:55 PM UTC 24
Peak memory 260756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213040625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1213040625
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.86279246
Short name T542
Test name
Test status
Simulation time 893519734 ps
CPU time 38.6 seconds
Started Sep 18 03:51:36 PM UTC 24
Finished Sep 18 03:52:16 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86279246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.86279246
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.3425225108
Short name T698
Test name
Test status
Simulation time 87740512824 ps
CPU time 2877.58 seconds
Started Sep 18 03:53:12 PM UTC 24
Finished Sep 18 04:41:42 PM UTC 24
Peak memory 302124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425225108 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.3425225108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/35.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.4267721432
Short name T646
Test name
Test status
Simulation time 18669829568 ps
CPU time 1166.27 seconds
Started Sep 18 03:54:49 PM UTC 24
Finished Sep 18 04:14:29 PM UTC 24
Peak memory 279076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267721432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.4267721432
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.4112466797
Short name T570
Test name
Test status
Simulation time 7829020875 ps
CPU time 231.88 seconds
Started Sep 18 03:54:23 PM UTC 24
Finished Sep 18 03:58:19 PM UTC 24
Peak memory 266732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112466797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4112466797
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.1516333560
Short name T555
Test name
Test status
Simulation time 1192612635 ps
CPU time 68.14 seconds
Started Sep 18 03:54:18 PM UTC 24
Finished Sep 18 03:55:27 PM UTC 24
Peak memory 260692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516333560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1516333560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.4005560478
Short name T704
Test name
Test status
Simulation time 94736402888 ps
CPU time 2978.21 seconds
Started Sep 18 03:54:49 PM UTC 24
Finished Sep 18 04:45:02 PM UTC 24
Peak memory 302056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005560478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4005560478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.2767865429
Short name T654
Test name
Test status
Simulation time 10289613801 ps
CPU time 1314.58 seconds
Started Sep 18 03:54:49 PM UTC 24
Finished Sep 18 04:16:59 PM UTC 24
Peak memory 299476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767865429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2767865429
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.1518582487
Short name T583
Test name
Test status
Simulation time 33289658745 ps
CPU time 372.42 seconds
Started Sep 18 03:54:49 PM UTC 24
Finished Sep 18 04:01:06 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518582487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1518582487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.2993496513
Short name T553
Test name
Test status
Simulation time 2830031368 ps
CPU time 36.62 seconds
Started Sep 18 03:54:08 PM UTC 24
Finished Sep 18 03:54:46 PM UTC 24
Peak memory 266640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993496513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2993496513
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.2677845917
Short name T345
Test name
Test status
Simulation time 254962166 ps
CPU time 34.8 seconds
Started Sep 18 03:54:11 PM UTC 24
Finished Sep 18 03:54:47 PM UTC 24
Peak memory 266608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677845917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2677845917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.2829497138
Short name T268
Test name
Test status
Simulation time 176750405 ps
CPU time 14.85 seconds
Started Sep 18 03:54:36 PM UTC 24
Finished Sep 18 03:54:52 PM UTC 24
Peak memory 260692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829497138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2829497138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.3395871665
Short name T551
Test name
Test status
Simulation time 2556692914 ps
CPU time 21.06 seconds
Started Sep 18 03:53:48 PM UTC 24
Finished Sep 18 03:54:11 PM UTC 24
Peak memory 266904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395871665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3395871665
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.1620339929
Short name T600
Test name
Test status
Simulation time 41810709903 ps
CPU time 575.74 seconds
Started Sep 18 03:54:53 PM UTC 24
Finished Sep 18 04:04:36 PM UTC 24
Peak memory 277212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620339929 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.1620339929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all_with_rand_reset.2626453575
Short name T134
Test name
Test status
Simulation time 6325729096 ps
CPU time 269.13 seconds
Started Sep 18 03:55:05 PM UTC 24
Finished Sep 18 03:59:38 PM UTC 24
Peak memory 279120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2626453575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.a
lert_handler_stress_all_with_rand_reset.2626453575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.35203812
Short name T696
Test name
Test status
Simulation time 99109718335 ps
CPU time 2542.1 seconds
Started Sep 18 03:56:06 PM UTC 24
Finished Sep 18 04:38:55 PM UTC 24
Peak memory 300004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35203812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/a
lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.35203812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.1734496989
Short name T561
Test name
Test status
Simulation time 586708519 ps
CPU time 65.67 seconds
Started Sep 18 03:55:50 PM UTC 24
Finished Sep 18 03:56:58 PM UTC 24
Peak memory 266588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734496989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1734496989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.3578323479
Short name T556
Test name
Test status
Simulation time 162630920 ps
CPU time 7.92 seconds
Started Sep 18 03:55:40 PM UTC 24
Finished Sep 18 03:55:49 PM UTC 24
Peak memory 260692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578323479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3578323479
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.3017395405
Short name T373
Test name
Test status
Simulation time 156944631953 ps
CPU time 1817.13 seconds
Started Sep 18 03:56:17 PM UTC 24
Finished Sep 18 04:26:54 PM UTC 24
Peak memory 283100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017395405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3017395405
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.1453936411
Short name T707
Test name
Test status
Simulation time 190118447737 ps
CPU time 2981.91 seconds
Started Sep 18 03:56:33 PM UTC 24
Finished Sep 18 04:46:49 PM UTC 24
Peak memory 302060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453936411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1453936411
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.2458736235
Short name T585
Test name
Test status
Simulation time 38068725735 ps
CPU time 308.26 seconds
Started Sep 18 03:56:10 PM UTC 24
Finished Sep 18 04:01:22 PM UTC 24
Peak memory 266780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458736235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2458736235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.528672417
Short name T557
Test name
Test status
Simulation time 1240889470 ps
CPU time 35.08 seconds
Started Sep 18 03:55:25 PM UTC 24
Finished Sep 18 03:56:01 PM UTC 24
Peak memory 260500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528672417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.528672417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.4212493263
Short name T560
Test name
Test status
Simulation time 5788264369 ps
CPU time 73.01 seconds
Started Sep 18 03:55:28 PM UTC 24
Finished Sep 18 03:56:43 PM UTC 24
Peak memory 266808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212493263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.4212493263
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.3976867739
Short name T558
Test name
Test status
Simulation time 2893866778 ps
CPU time 58.2 seconds
Started Sep 18 03:55:05 PM UTC 24
Finished Sep 18 03:56:05 PM UTC 24
Peak memory 266712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976867739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3976867739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all_with_rand_reset.932043943
Short name T610
Test name
Test status
Simulation time 18616207399 ps
CPU time 562.5 seconds
Started Sep 18 03:56:44 PM UTC 24
Finished Sep 18 04:06:14 PM UTC 24
Peak memory 293452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=932043943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.al
ert_handler_stress_all_with_rand_reset.932043943
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.1602358916
Short name T700
Test name
Test status
Simulation time 99685754089 ps
CPU time 2698.41 seconds
Started Sep 18 03:57:38 PM UTC 24
Finished Sep 18 04:43:06 PM UTC 24
Peak memory 302052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602358916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1602358916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.1629379035
Short name T571
Test name
Test status
Simulation time 2112673027 ps
CPU time 105.41 seconds
Started Sep 18 03:57:10 PM UTC 24
Finished Sep 18 03:58:58 PM UTC 24
Peak memory 266604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629379035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1629379035
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.3303517035
Short name T569
Test name
Test status
Simulation time 2798119517 ps
CPU time 53.27 seconds
Started Sep 18 03:57:07 PM UTC 24
Finished Sep 18 03:58:02 PM UTC 24
Peak memory 266712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303517035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3303517035
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.2573290164
Short name T648
Test name
Test status
Simulation time 99170910435 ps
CPU time 1030.81 seconds
Started Sep 18 03:57:53 PM UTC 24
Finished Sep 18 04:15:16 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573290164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2573290164
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.1027966638
Short name T675
Test name
Test status
Simulation time 57233173405 ps
CPU time 1475.96 seconds
Started Sep 18 03:57:58 PM UTC 24
Finished Sep 18 04:22:51 PM UTC 24
Peak memory 299548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027966638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1027966638
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.2135174925
Short name T576
Test name
Test status
Simulation time 13490897929 ps
CPU time 140.28 seconds
Started Sep 18 03:57:53 PM UTC 24
Finished Sep 18 04:00:16 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135174925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2135174925
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.38987654
Short name T563
Test name
Test status
Simulation time 490847595 ps
CPU time 6.51 seconds
Started Sep 18 03:56:59 PM UTC 24
Finished Sep 18 03:57:06 PM UTC 24
Peak memory 260536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38987654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran
dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.38987654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.2179233419
Short name T567
Test name
Test status
Simulation time 1546711285 ps
CPU time 45.9 seconds
Started Sep 18 03:57:04 PM UTC 24
Finished Sep 18 03:57:51 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179233419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2179233419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.1164180118
Short name T568
Test name
Test status
Simulation time 1333854740 ps
CPU time 35.2 seconds
Started Sep 18 03:57:21 PM UTC 24
Finished Sep 18 03:57:58 PM UTC 24
Peak memory 260500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164180118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1164180118
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.563600694
Short name T564
Test name
Test status
Simulation time 406590622 ps
CPU time 15.95 seconds
Started Sep 18 03:56:52 PM UTC 24
Finished Sep 18 03:57:09 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563600694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.563600694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.1067150847
Short name T283
Test name
Test status
Simulation time 54866076885 ps
CPU time 868.43 seconds
Started Sep 18 03:58:02 PM UTC 24
Finished Sep 18 04:12:42 PM UTC 24
Peak memory 277212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067150847 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.1067150847
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/38.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.1398145086
Short name T673
Test name
Test status
Simulation time 68592099883 ps
CPU time 1308.43 seconds
Started Sep 18 04:00:06 PM UTC 24
Finished Sep 18 04:22:09 PM UTC 24
Peak memory 293472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398145086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1398145086
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.4225641078
Short name T590
Test name
Test status
Simulation time 13202280778 ps
CPU time 158.06 seconds
Started Sep 18 03:59:43 PM UTC 24
Finished Sep 18 04:02:24 PM UTC 24
Peak memory 266804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225641078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.4225641078
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.1130790009
Short name T579
Test name
Test status
Simulation time 789286669 ps
CPU time 42 seconds
Started Sep 18 03:59:39 PM UTC 24
Finished Sep 18 04:00:22 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130790009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1130790009
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.3231333148
Short name T380
Test name
Test status
Simulation time 31515200847 ps
CPU time 1793.51 seconds
Started Sep 18 04:00:18 PM UTC 24
Finished Sep 18 04:30:33 PM UTC 24
Peak memory 299740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231333148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3231333148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.2706816011
Short name T694
Test name
Test status
Simulation time 160394924941 ps
CPU time 2112.85 seconds
Started Sep 18 04:00:25 PM UTC 24
Finished Sep 18 04:36:03 PM UTC 24
Peak memory 300004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706816011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2706816011
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.4005458574
Short name T589
Test name
Test status
Simulation time 12094943628 ps
CPU time 100.25 seconds
Started Sep 18 04:00:18 PM UTC 24
Finished Sep 18 04:02:00 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005458574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.4005458574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.898499049
Short name T581
Test name
Test status
Simulation time 796456716 ps
CPU time 61.85 seconds
Started Sep 18 03:59:24 PM UTC 24
Finished Sep 18 04:00:27 PM UTC 24
Peak memory 266572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898499049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.898499049
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.1289569443
Short name T573
Test name
Test status
Simulation time 50015675 ps
CPU time 6.91 seconds
Started Sep 18 03:59:34 PM UTC 24
Finished Sep 18 03:59:42 PM UTC 24
Peak memory 250456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289569443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1289569443
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.121268692
Short name T282
Test name
Test status
Simulation time 920161721 ps
CPU time 75.85 seconds
Started Sep 18 04:00:01 PM UTC 24
Finished Sep 18 04:01:23 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121268692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.121268692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.1529064075
Short name T580
Test name
Test status
Simulation time 19696088858 ps
CPU time 85.62 seconds
Started Sep 18 03:58:59 PM UTC 24
Finished Sep 18 04:00:27 PM UTC 24
Peak memory 266968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529064075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1529064075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.206451570
Short name T353
Test name
Test status
Simulation time 34793126592 ps
CPU time 1719.11 seconds
Started Sep 18 04:00:25 PM UTC 24
Finished Sep 18 04:29:24 PM UTC 24
Peak memory 309712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206451570 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.206451570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all_with_rand_reset.3701617790
Short name T287
Test name
Test status
Simulation time 5799373900 ps
CPU time 245.52 seconds
Started Sep 18 04:00:28 PM UTC 24
Finished Sep 18 04:04:37 PM UTC 24
Peak memory 277072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3701617790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.a
lert_handler_stress_all_with_rand_reset.3701617790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.3822841087
Short name T78
Test name
Test status
Simulation time 35910599 ps
CPU time 5.03 seconds
Started Sep 18 02:50:59 PM UTC 24
Finished Sep 18 02:51:05 PM UTC 24
Peak memory 260772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822841087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3822841087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.3186376682
Short name T449
Test name
Test status
Simulation time 29179774261 ps
CPU time 1831.74 seconds
Started Sep 18 02:50:35 PM UTC 24
Finished Sep 18 03:21:30 PM UTC 24
Peak memory 283360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186376682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3186376682
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.2192306601
Short name T23
Test name
Test status
Simulation time 911755398 ps
CPU time 19.94 seconds
Started Sep 18 02:50:57 PM UTC 24
Finished Sep 18 02:51:18 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192306601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2192306601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.3425833391
Short name T162
Test name
Test status
Simulation time 1513149364 ps
CPU time 152.82 seconds
Started Sep 18 02:50:26 PM UTC 24
Finished Sep 18 02:53:01 PM UTC 24
Peak memory 266604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425833391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3425833391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.3176578909
Short name T40
Test name
Test status
Simulation time 958548515 ps
CPU time 40.78 seconds
Started Sep 18 02:50:26 PM UTC 24
Finished Sep 18 02:51:08 PM UTC 24
Peak memory 260428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176578909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3176578909
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.3953334984
Short name T361
Test name
Test status
Simulation time 34815605990 ps
CPU time 2165.35 seconds
Started Sep 18 02:50:46 PM UTC 24
Finished Sep 18 03:27:16 PM UTC 24
Peak memory 293332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953334984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3953334984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.3214634163
Short name T377
Test name
Test status
Simulation time 11143413165 ps
CPU time 686.09 seconds
Started Sep 18 02:50:55 PM UTC 24
Finished Sep 18 03:02:29 PM UTC 24
Peak memory 283424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214634163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3214634163
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.1296987216
Short name T19
Test name
Test status
Simulation time 15863153338 ps
CPU time 149.41 seconds
Started Sep 18 02:50:40 PM UTC 24
Finished Sep 18 02:53:12 PM UTC 24
Peak memory 266784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296987216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1296987216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.4154078211
Short name T39
Test name
Test status
Simulation time 388345145 ps
CPU time 39.23 seconds
Started Sep 18 02:50:15 PM UTC 24
Finished Sep 18 02:50:56 PM UTC 24
Peak memory 266836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154078211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.4154078211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.119931153
Short name T41
Test name
Test status
Simulation time 354468579 ps
CPU time 17.6 seconds
Started Sep 18 02:50:16 PM UTC 24
Finished Sep 18 02:50:35 PM UTC 24
Peak memory 264600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119931153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.119931153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.3922294048
Short name T50
Test name
Test status
Simulation time 598729286 ps
CPU time 15.54 seconds
Started Sep 18 02:51:06 PM UTC 24
Finished Sep 18 02:51:23 PM UTC 24
Peak memory 292736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922294048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3922294048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.2054144258
Short name T76
Test name
Test status
Simulation time 575525183 ps
CPU time 38.05 seconds
Started Sep 18 02:50:14 PM UTC 24
Finished Sep 18 02:50:53 PM UTC 24
Peak memory 266644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054144258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2054144258
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all_with_rand_reset.1684003947
Short name T48
Test name
Test status
Simulation time 17565615301 ps
CPU time 242.32 seconds
Started Sep 18 02:51:06 PM UTC 24
Finished Sep 18 02:55:12 PM UTC 24
Peak memory 279188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1684003947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.al
ert_handler_stress_all_with_rand_reset.1684003947
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.2409691680
Short name T678
Test name
Test status
Simulation time 77941787730 ps
CPU time 1288.28 seconds
Started Sep 18 04:01:29 PM UTC 24
Finished Sep 18 04:23:12 PM UTC 24
Peak memory 277024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409691680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2409691680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.3948402089
Short name T608
Test name
Test status
Simulation time 14958784205 ps
CPU time 241.96 seconds
Started Sep 18 04:01:23 PM UTC 24
Finished Sep 18 04:05:28 PM UTC 24
Peak memory 266700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948402089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3948402089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.554203346
Short name T591
Test name
Test status
Simulation time 3859645073 ps
CPU time 76.39 seconds
Started Sep 18 04:01:13 PM UTC 24
Finished Sep 18 04:02:31 PM UTC 24
Peak memory 260760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554203346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.554203346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.635254260
Short name T660
Test name
Test status
Simulation time 17433917846 ps
CPU time 1018.41 seconds
Started Sep 18 04:01:56 PM UTC 24
Finished Sep 18 04:19:06 PM UTC 24
Peak memory 283416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635254260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.635254260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.1870882407
Short name T702
Test name
Test status
Simulation time 42029276496 ps
CPU time 2497.02 seconds
Started Sep 18 04:02:00 PM UTC 24
Finished Sep 18 04:44:05 PM UTC 24
Peak memory 298032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870882407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1870882407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.3236617052
Short name T601
Test name
Test status
Simulation time 5115577320 ps
CPU time 170.91 seconds
Started Sep 18 04:01:47 PM UTC 24
Finished Sep 18 04:04:41 PM UTC 24
Peak memory 260640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236617052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3236617052
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.2522149270
Short name T587
Test name
Test status
Simulation time 964971414 ps
CPU time 47.91 seconds
Started Sep 18 04:00:56 PM UTC 24
Finished Sep 18 04:01:46 PM UTC 24
Peak memory 260536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522149270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2522149270
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.3941970757
Short name T584
Test name
Test status
Simulation time 172330938 ps
CPU time 3.96 seconds
Started Sep 18 04:01:07 PM UTC 24
Finished Sep 18 04:01:11 PM UTC 24
Peak memory 250200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941970757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3941970757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.1670141111
Short name T290
Test name
Test status
Simulation time 620033405 ps
CPU time 29.85 seconds
Started Sep 18 04:01:24 PM UTC 24
Finished Sep 18 04:01:55 PM UTC 24
Peak memory 260428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670141111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1670141111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.263319111
Short name T582
Test name
Test status
Simulation time 817869120 ps
CPU time 25.63 seconds
Started Sep 18 04:00:28 PM UTC 24
Finished Sep 18 04:00:55 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263319111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.263319111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.261344070
Short name T270
Test name
Test status
Simulation time 34934818330 ps
CPU time 2059.83 seconds
Started Sep 18 04:02:01 PM UTC 24
Finished Sep 18 04:36:46 PM UTC 24
Peak memory 299740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261344070 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.261344070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/40.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.1383010449
Short name T710
Test name
Test status
Simulation time 172735919656 ps
CPU time 2708.89 seconds
Started Sep 18 04:03:08 PM UTC 24
Finished Sep 18 04:48:47 PM UTC 24
Peak memory 302056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383010449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1383010449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.2554381564
Short name T619
Test name
Test status
Simulation time 63331666987 ps
CPU time 275.4 seconds
Started Sep 18 04:02:59 PM UTC 24
Finished Sep 18 04:07:39 PM UTC 24
Peak memory 266804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554381564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2554381564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.3677990754
Short name T595
Test name
Test status
Simulation time 328410004 ps
CPU time 23.18 seconds
Started Sep 18 04:02:59 PM UTC 24
Finished Sep 18 04:03:24 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677990754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3677990754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.729273006
Short name T382
Test name
Test status
Simulation time 164813877772 ps
CPU time 2185.77 seconds
Started Sep 18 04:03:35 PM UTC 24
Finished Sep 18 04:40:26 PM UTC 24
Peak memory 298024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729273006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.729273006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.2717706806
Short name T697
Test name
Test status
Simulation time 38165911823 ps
CPU time 2221.87 seconds
Started Sep 18 04:03:39 PM UTC 24
Finished Sep 18 04:41:06 PM UTC 24
Peak memory 299480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717706806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2717706806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.2558434163
Short name T629
Test name
Test status
Simulation time 14990495711 ps
CPU time 393.52 seconds
Started Sep 18 04:03:25 PM UTC 24
Finished Sep 18 04:10:03 PM UTC 24
Peak memory 260828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558434163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2558434163
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.2743668792
Short name T593
Test name
Test status
Simulation time 437478887 ps
CPU time 32.05 seconds
Started Sep 18 04:02:32 PM UTC 24
Finished Sep 18 04:03:06 PM UTC 24
Peak memory 266840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743668792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2743668792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.839922178
Short name T592
Test name
Test status
Simulation time 38116302 ps
CPU time 5.87 seconds
Started Sep 18 04:02:49 PM UTC 24
Finished Sep 18 04:02:56 PM UTC 24
Peak memory 250456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839922178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.839922178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.2474105841
Short name T597
Test name
Test status
Simulation time 1536840522 ps
CPU time 36.92 seconds
Started Sep 18 04:03:06 PM UTC 24
Finished Sep 18 04:03:45 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474105841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2474105841
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.1262571700
Short name T594
Test name
Test status
Simulation time 2247567947 ps
CPU time 41.63 seconds
Started Sep 18 04:02:24 PM UTC 24
Finished Sep 18 04:03:07 PM UTC 24
Peak memory 260568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262571700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1262571700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.4065502494
Short name T695
Test name
Test status
Simulation time 32747240445 ps
CPU time 2084.13 seconds
Started Sep 18 04:03:45 PM UTC 24
Finished Sep 18 04:38:53 PM UTC 24
Peak memory 293332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065502494 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.4065502494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all_with_rand_reset.946526466
Short name T156
Test name
Test status
Simulation time 3847198141 ps
CPU time 443.75 seconds
Started Sep 18 04:03:51 PM UTC 24
Finished Sep 18 04:11:21 PM UTC 24
Peak memory 279056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=946526466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.al
ert_handler_stress_all_with_rand_reset.946526466
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.421801137
Short name T669
Test name
Test status
Simulation time 16878722816 ps
CPU time 975.56 seconds
Started Sep 18 04:04:54 PM UTC 24
Finished Sep 18 04:21:22 PM UTC 24
Peak memory 281120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421801137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.421801137
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.3840524463
Short name T626
Test name
Test status
Simulation time 3097530321 ps
CPU time 271.51 seconds
Started Sep 18 04:04:42 PM UTC 24
Finished Sep 18 04:09:18 PM UTC 24
Peak memory 266932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840524463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3840524463
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.211710512
Short name T603
Test name
Test status
Simulation time 461208589 ps
CPU time 13.15 seconds
Started Sep 18 04:04:38 PM UTC 24
Finished Sep 18 04:04:52 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211710512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.211710512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.1947930419
Short name T686
Test name
Test status
Simulation time 21804760001 ps
CPU time 1352.6 seconds
Started Sep 18 04:05:07 PM UTC 24
Finished Sep 18 04:27:55 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947930419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1947930419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.3602966528
Short name T655
Test name
Test status
Simulation time 18326516752 ps
CPU time 741.68 seconds
Started Sep 18 04:05:09 PM UTC 24
Finished Sep 18 04:17:40 PM UTC 24
Peak memory 283164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602966528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3602966528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.2824078215
Short name T625
Test name
Test status
Simulation time 25924241103 ps
CPU time 219.69 seconds
Started Sep 18 04:05:03 PM UTC 24
Finished Sep 18 04:08:47 PM UTC 24
Peak memory 266972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824078215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2824078215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.4090852775
Short name T607
Test name
Test status
Simulation time 2122913273 ps
CPU time 57.85 seconds
Started Sep 18 04:04:21 PM UTC 24
Finished Sep 18 04:05:21 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090852775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4090852775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.453681806
Short name T606
Test name
Test status
Simulation time 469595673 ps
CPU time 36.16 seconds
Started Sep 18 04:04:37 PM UTC 24
Finished Sep 18 04:05:14 PM UTC 24
Peak memory 260728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453681806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.453681806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.1411762553
Short name T605
Test name
Test status
Simulation time 87946643 ps
CPU time 14.28 seconds
Started Sep 18 04:04:53 PM UTC 24
Finished Sep 18 04:05:08 PM UTC 24
Peak memory 260500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411762553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1411762553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.3218088355
Short name T604
Test name
Test status
Simulation time 1375731330 ps
CPU time 46.34 seconds
Started Sep 18 04:04:18 PM UTC 24
Finished Sep 18 04:05:06 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218088355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3218088355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/42.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.3181590875
Short name T159
Test name
Test status
Simulation time 29151980908 ps
CPU time 1423.62 seconds
Started Sep 18 04:06:35 PM UTC 24
Finished Sep 18 04:30:36 PM UTC 24
Peak memory 299476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181590875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3181590875
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.948733450
Short name T617
Test name
Test status
Simulation time 643813046 ps
CPU time 50.88 seconds
Started Sep 18 04:06:27 PM UTC 24
Finished Sep 18 04:07:20 PM UTC 24
Peak memory 266580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948733450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.948733450
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.2456474260
Short name T616
Test name
Test status
Simulation time 310612615 ps
CPU time 41.09 seconds
Started Sep 18 04:06:16 PM UTC 24
Finished Sep 18 04:06:59 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456474260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2456474260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.2303960543
Short name T703
Test name
Test status
Simulation time 745318819948 ps
CPU time 2269.34 seconds
Started Sep 18 04:06:45 PM UTC 24
Finished Sep 18 04:45:01 PM UTC 24
Peak memory 302128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303960543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2303960543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.4090395153
Short name T652
Test name
Test status
Simulation time 15914101958 ps
CPU time 1323.69 seconds
Started Sep 18 04:06:57 PM UTC 24
Finished Sep 18 04:29:17 PM UTC 24
Peak memory 283360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090395153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.4090395153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.2357699707
Short name T611
Test name
Test status
Simulation time 451463613 ps
CPU time 55.66 seconds
Started Sep 18 04:05:29 PM UTC 24
Finished Sep 18 04:06:27 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357699707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2357699707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.4187327798
Short name T615
Test name
Test status
Simulation time 3106655311 ps
CPU time 40.22 seconds
Started Sep 18 04:06:15 PM UTC 24
Finished Sep 18 04:06:57 PM UTC 24
Peak memory 260568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187327798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4187327798
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.3082676874
Short name T614
Test name
Test status
Simulation time 119873453 ps
CPU time 13.37 seconds
Started Sep 18 04:06:28 PM UTC 24
Finished Sep 18 04:06:43 PM UTC 24
Peak memory 264524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082676874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3082676874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.2890200636
Short name T612
Test name
Test status
Simulation time 4491024597 ps
CPU time 70.62 seconds
Started Sep 18 04:05:22 PM UTC 24
Finished Sep 18 04:06:35 PM UTC 24
Peak memory 260584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890200636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2890200636
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.4114534061
Short name T284
Test name
Test status
Simulation time 37171908748 ps
CPU time 2385.64 seconds
Started Sep 18 04:07:00 PM UTC 24
Finished Sep 18 04:47:13 PM UTC 24
Peak memory 302316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114534061 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.4114534061
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.708885958
Short name T699
Test name
Test status
Simulation time 148717567864 ps
CPU time 2026.67 seconds
Started Sep 18 04:08:26 PM UTC 24
Finished Sep 18 04:42:38 PM UTC 24
Peak memory 299480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708885958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.708885958
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.1829393963
Short name T637
Test name
Test status
Simulation time 2153547336 ps
CPU time 225.94 seconds
Started Sep 18 04:08:02 PM UTC 24
Finished Sep 18 04:11:52 PM UTC 24
Peak memory 266636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829393963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1829393963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.3955080971
Short name T627
Test name
Test status
Simulation time 936995540 ps
CPU time 80.06 seconds
Started Sep 18 04:07:57 PM UTC 24
Finished Sep 18 04:09:19 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955080971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3955080971
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.1192735475
Short name T381
Test name
Test status
Simulation time 32465532310 ps
CPU time 1990.32 seconds
Started Sep 18 04:08:48 PM UTC 24
Finished Sep 18 04:42:21 PM UTC 24
Peak memory 283096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192735475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1192735475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.4071429800
Short name T715
Test name
Test status
Simulation time 163440750264 ps
CPU time 2822.93 seconds
Started Sep 18 04:08:59 PM UTC 24
Finished Sep 18 04:56:36 PM UTC 24
Peak memory 302124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071429800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.4071429800
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.889263777
Short name T628
Test name
Test status
Simulation time 22325000453 ps
CPU time 69.18 seconds
Started Sep 18 04:08:46 PM UTC 24
Finished Sep 18 04:09:57 PM UTC 24
Peak memory 260824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889263777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.889263777
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.3598980540
Short name T621
Test name
Test status
Simulation time 406468880 ps
CPU time 15.47 seconds
Started Sep 18 04:07:40 PM UTC 24
Finished Sep 18 04:07:56 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598980540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3598980540
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.3760931579
Short name T623
Test name
Test status
Simulation time 2309535380 ps
CPU time 35.15 seconds
Started Sep 18 04:07:48 PM UTC 24
Finished Sep 18 04:08:25 PM UTC 24
Peak memory 260496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760931579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3760931579
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.3187796757
Short name T624
Test name
Test status
Simulation time 678508940 ps
CPU time 49.13 seconds
Started Sep 18 04:07:35 PM UTC 24
Finished Sep 18 04:08:26 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187796757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3187796757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.1243787349
Short name T691
Test name
Test status
Simulation time 103833735224 ps
CPU time 1335.71 seconds
Started Sep 18 04:09:19 PM UTC 24
Finished Sep 18 04:31:51 PM UTC 24
Peak memory 299548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243787349 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.1243787349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all_with_rand_reset.3506428402
Short name T638
Test name
Test status
Simulation time 2044775387 ps
CPU time 154.06 seconds
Started Sep 18 04:09:20 PM UTC 24
Finished Sep 18 04:11:57 PM UTC 24
Peak memory 276944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3506428402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.a
lert_handler_stress_all_with_rand_reset.3506428402
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.3204643741
Short name T712
Test name
Test status
Simulation time 163585745206 ps
CPU time 2495.04 seconds
Started Sep 18 04:11:15 PM UTC 24
Finished Sep 18 04:53:20 PM UTC 24
Peak memory 302052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204643741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3204643741
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.2535614894
Short name T643
Test name
Test status
Simulation time 1373242565 ps
CPU time 157.73 seconds
Started Sep 18 04:10:37 PM UTC 24
Finished Sep 18 04:13:18 PM UTC 24
Peak memory 266612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535614894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2535614894
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.62917008
Short name T633
Test name
Test status
Simulation time 615896215 ps
CPU time 37.96 seconds
Started Sep 18 04:10:35 PM UTC 24
Finished Sep 18 04:11:15 PM UTC 24
Peak memory 266868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62917008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.62917008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.659679978
Short name T709
Test name
Test status
Simulation time 37182369758 ps
CPU time 2137.54 seconds
Started Sep 18 04:11:24 PM UTC 24
Finished Sep 18 04:47:26 PM UTC 24
Peak memory 297496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659679978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.659679978
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.1391415979
Short name T687
Test name
Test status
Simulation time 31607982067 ps
CPU time 982.67 seconds
Started Sep 18 04:11:33 PM UTC 24
Finished Sep 18 04:28:08 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391415979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1391415979
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.3343886076
Short name T667
Test name
Test status
Simulation time 19511166552 ps
CPU time 553.24 seconds
Started Sep 18 04:11:22 PM UTC 24
Finished Sep 18 04:20:43 PM UTC 24
Peak memory 266780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343886076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3343886076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.1069052242
Short name T632
Test name
Test status
Simulation time 726903977 ps
CPU time 65.22 seconds
Started Sep 18 04:10:04 PM UTC 24
Finished Sep 18 04:11:11 PM UTC 24
Peak memory 266840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069052242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1069052242
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.3666497300
Short name T355
Test name
Test status
Simulation time 304087102 ps
CPU time 16.57 seconds
Started Sep 18 04:10:19 PM UTC 24
Finished Sep 18 04:10:37 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666497300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3666497300
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.347192868
Short name T635
Test name
Test status
Simulation time 382526367 ps
CPU time 18.61 seconds
Started Sep 18 04:11:12 PM UTC 24
Finished Sep 18 04:11:32 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347192868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.347192868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.3669060783
Short name T631
Test name
Test status
Simulation time 1314563899 ps
CPU time 34.69 seconds
Started Sep 18 04:09:58 PM UTC 24
Finished Sep 18 04:10:34 PM UTC 24
Peak memory 266572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669060783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3669060783
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.3060679197
Short name T639
Test name
Test status
Simulation time 1347905239 ps
CPU time 40.74 seconds
Started Sep 18 04:11:45 PM UTC 24
Finished Sep 18 04:12:28 PM UTC 24
Peak memory 266652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060679197 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.3060679197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/45.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.2717250376
Short name T693
Test name
Test status
Simulation time 22318603365 ps
CPU time 1355.89 seconds
Started Sep 18 04:13:02 PM UTC 24
Finished Sep 18 04:35:54 PM UTC 24
Peak memory 277216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717250376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2717250376
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.3646905173
Short name T645
Test name
Test status
Simulation time 1153766242 ps
CPU time 91.99 seconds
Started Sep 18 04:12:48 PM UTC 24
Finished Sep 18 04:14:22 PM UTC 24
Peak memory 260724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646905173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3646905173
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.4246185215
Short name T644
Test name
Test status
Simulation time 738159879 ps
CPU time 73.39 seconds
Started Sep 18 04:12:43 PM UTC 24
Finished Sep 18 04:13:58 PM UTC 24
Peak memory 266576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246185215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4246185215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.395075098
Short name T683
Test name
Test status
Simulation time 28036946182 ps
CPU time 800.53 seconds
Started Sep 18 04:13:19 PM UTC 24
Finished Sep 18 04:26:49 PM UTC 24
Peak memory 283160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395075098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.395075098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.2079589863
Short name T354
Test name
Test status
Simulation time 135803029783 ps
CPU time 2333.31 seconds
Started Sep 18 04:13:22 PM UTC 24
Finished Sep 18 04:52:42 PM UTC 24
Peak memory 300076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079589863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2079589863
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.1455416181
Short name T676
Test name
Test status
Simulation time 42489104625 ps
CPU time 580.33 seconds
Started Sep 18 04:13:09 PM UTC 24
Finished Sep 18 04:22:57 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455416181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1455416181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.1781182232
Short name T640
Test name
Test status
Simulation time 3741721594 ps
CPU time 47.13 seconds
Started Sep 18 04:11:58 PM UTC 24
Finished Sep 18 04:12:47 PM UTC 24
Peak memory 266640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781182232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1781182232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.3570478750
Short name T157
Test name
Test status
Simulation time 5158753041 ps
CPU time 32.03 seconds
Started Sep 18 04:12:28 PM UTC 24
Finished Sep 18 04:13:01 PM UTC 24
Peak memory 260760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570478750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3570478750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.2045549171
Short name T641
Test name
Test status
Simulation time 4736100829 ps
CPU time 60.2 seconds
Started Sep 18 04:11:53 PM UTC 24
Finished Sep 18 04:12:55 PM UTC 24
Peak memory 266704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045549171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2045549171
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all_with_rand_reset.4213323716
Short name T651
Test name
Test status
Simulation time 3081781519 ps
CPU time 124.67 seconds
Started Sep 18 04:14:23 PM UTC 24
Finished Sep 18 04:16:30 PM UTC 24
Peak memory 277008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4213323716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.a
lert_handler_stress_all_with_rand_reset.4213323716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.216885950
Short name T716
Test name
Test status
Simulation time 232257085293 ps
CPU time 2635.44 seconds
Started Sep 18 04:15:19 PM UTC 24
Finished Sep 18 04:59:44 PM UTC 24
Peak memory 302064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216885950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.216885950
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.277694607
Short name T656
Test name
Test status
Simulation time 5464130945 ps
CPU time 151.42 seconds
Started Sep 18 04:15:11 PM UTC 24
Finished Sep 18 04:17:45 PM UTC 24
Peak memory 266704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277694607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.277694607
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.3631309933
Short name T653
Test name
Test status
Simulation time 4295896233 ps
CPU time 85.58 seconds
Started Sep 18 04:15:05 PM UTC 24
Finished Sep 18 04:16:33 PM UTC 24
Peak memory 260560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631309933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3631309933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.94635392
Short name T682
Test name
Test status
Simulation time 14736039089 ps
CPU time 596.9 seconds
Started Sep 18 04:15:53 PM UTC 24
Finished Sep 18 04:25:58 PM UTC 24
Peak memory 276956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94635392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.94635392
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.2624892680
Short name T689
Test name
Test status
Simulation time 27763379945 ps
CPU time 836.85 seconds
Started Sep 18 04:16:31 PM UTC 24
Finished Sep 18 04:30:38 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624892680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2624892680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.578719927
Short name T666
Test name
Test status
Simulation time 14276030270 ps
CPU time 311.64 seconds
Started Sep 18 04:15:26 PM UTC 24
Finished Sep 18 04:20:42 PM UTC 24
Peak memory 260564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578719927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.578719927
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.6310153
Short name T647
Test name
Test status
Simulation time 371520094 ps
CPU time 31.66 seconds
Started Sep 18 04:14:31 PM UTC 24
Finished Sep 18 04:15:04 PM UTC 24
Peak memory 266580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6310153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_rand
om_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.6310153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.2985117272
Short name T158
Test name
Test status
Simulation time 224688215 ps
CPU time 32.16 seconds
Started Sep 18 04:14:37 PM UTC 24
Finished Sep 18 04:15:10 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985117272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2985117272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.3501364279
Short name T288
Test name
Test status
Simulation time 3870700184 ps
CPU time 71.11 seconds
Started Sep 18 04:15:18 PM UTC 24
Finished Sep 18 04:16:31 PM UTC 24
Peak memory 266772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501364279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3501364279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.1974167614
Short name T649
Test name
Test status
Simulation time 552017681 ps
CPU time 47.58 seconds
Started Sep 18 04:14:29 PM UTC 24
Finished Sep 18 04:15:18 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974167614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1974167614
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.914192446
Short name T708
Test name
Test status
Simulation time 15719287059 ps
CPU time 1801.68 seconds
Started Sep 18 04:16:32 PM UTC 24
Finished Sep 18 04:46:56 PM UTC 24
Peak memory 315856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914192446 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.914192446
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/47.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.3733901613
Short name T690
Test name
Test status
Simulation time 23735156662 ps
CPU time 756.43 seconds
Started Sep 18 04:18:56 PM UTC 24
Finished Sep 18 04:31:43 PM UTC 24
Peak memory 283360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733901613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3733901613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.1029264228
Short name T664
Test name
Test status
Simulation time 1453335394 ps
CPU time 129.99 seconds
Started Sep 18 04:18:12 PM UTC 24
Finished Sep 18 04:20:24 PM UTC 24
Peak memory 266676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029264228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1029264228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.2258641321
Short name T711
Test name
Test status
Simulation time 262997523925 ps
CPU time 1990.51 seconds
Started Sep 18 04:19:08 PM UTC 24
Finished Sep 18 04:52:42 PM UTC 24
Peak memory 283172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258641321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2258641321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.944624708
Short name T692
Test name
Test status
Simulation time 10479271811 ps
CPU time 895.65 seconds
Started Sep 18 04:19:26 PM UTC 24
Finished Sep 18 04:34:33 PM UTC 24
Peak memory 283164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944624708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.944624708
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.4254278212
Short name T679
Test name
Test status
Simulation time 7236532203 ps
CPU time 311.74 seconds
Started Sep 18 04:19:01 PM UTC 24
Finished Sep 18 04:24:18 PM UTC 24
Peak memory 260700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254278212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4254278212
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.2197145972
Short name T658
Test name
Test status
Simulation time 6520275246 ps
CPU time 61.52 seconds
Started Sep 18 04:17:41 PM UTC 24
Finished Sep 18 04:18:44 PM UTC 24
Peak memory 266724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197145972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2197145972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.187959040
Short name T359
Test name
Test status
Simulation time 227254304 ps
CPU time 23.25 seconds
Started Sep 18 04:17:46 PM UTC 24
Finished Sep 18 04:18:11 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187959040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.187959040
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.2352440082
Short name T278
Test name
Test status
Simulation time 780803434 ps
CPU time 71.18 seconds
Started Sep 18 04:18:45 PM UTC 24
Finished Sep 18 04:19:58 PM UTC 24
Peak memory 260500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352440082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2352440082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.892009887
Short name T657
Test name
Test status
Simulation time 2555967892 ps
CPU time 56.91 seconds
Started Sep 18 04:17:02 PM UTC 24
Finished Sep 18 04:18:01 PM UTC 24
Peak memory 266904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892009887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.892009887
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.92039678
Short name T705
Test name
Test status
Simulation time 65929454740 ps
CPU time 1560.11 seconds
Started Sep 18 04:19:28 PM UTC 24
Finished Sep 18 04:45:47 PM UTC 24
Peak memory 299472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92039678 -assert nopostproc +UVM_TES
TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.92039678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all_with_rand_reset.517056902
Short name T280
Test name
Test status
Simulation time 7253767648 ps
CPU time 539.46 seconds
Started Sep 18 04:19:58 PM UTC 24
Finished Sep 18 04:29:05 PM UTC 24
Peak memory 283288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=517056902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.al
ert_handler_stress_all_with_rand_reset.517056902
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.1156977616
Short name T674
Test name
Test status
Simulation time 1992822409 ps
CPU time 111.89 seconds
Started Sep 18 04:20:29 PM UTC 24
Finished Sep 18 04:22:23 PM UTC 24
Peak memory 266676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156977616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1156977616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.3770349517
Short name T670
Test name
Test status
Simulation time 873493123 ps
CPU time 73.67 seconds
Started Sep 18 04:20:25 PM UTC 24
Finished Sep 18 04:21:41 PM UTC 24
Peak memory 260692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770349517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3770349517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.3392377347
Short name T714
Test name
Test status
Simulation time 171572037089 ps
CPU time 1912.38 seconds
Started Sep 18 04:21:22 PM UTC 24
Finished Sep 18 04:53:37 PM UTC 24
Peak memory 283096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392377347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3392377347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.3665299086
Short name T713
Test name
Test status
Simulation time 34936086229 ps
CPU time 1907.45 seconds
Started Sep 18 04:21:24 PM UTC 24
Finished Sep 18 04:53:35 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665299086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3665299086
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.3887399929
Short name T335
Test name
Test status
Simulation time 15083125394 ps
CPU time 506.86 seconds
Started Sep 18 04:20:54 PM UTC 24
Finished Sep 18 04:29:27 PM UTC 24
Peak memory 266708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887399929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3887399929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.427439857
Short name T665
Test name
Test status
Simulation time 391337160 ps
CPU time 20.9 seconds
Started Sep 18 04:20:06 PM UTC 24
Finished Sep 18 04:20:28 PM UTC 24
Peak memory 260428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427439857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.427439857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.2665979259
Short name T668
Test name
Test status
Simulation time 1047465446 ps
CPU time 33.37 seconds
Started Sep 18 04:20:18 PM UTC 24
Finished Sep 18 04:20:53 PM UTC 24
Peak memory 260464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665979259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2665979259
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.2111384044
Short name T285
Test name
Test status
Simulation time 1924404747 ps
CPU time 36.98 seconds
Started Sep 18 04:20:43 PM UTC 24
Finished Sep 18 04:21:21 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111384044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2111384044
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.2804604098
Short name T663
Test name
Test status
Simulation time 204209873 ps
CPU time 16.65 seconds
Started Sep 18 04:20:00 PM UTC 24
Finished Sep 18 04:20:17 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804604098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2804604098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.980300445
Short name T681
Test name
Test status
Simulation time 4985917323 ps
CPU time 241.94 seconds
Started Sep 18 04:21:42 PM UTC 24
Finished Sep 18 04:25:47 PM UTC 24
Peak memory 264796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980300445 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.980300445
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.2719470161
Short name T680
Test name
Test status
Simulation time 2827564359 ps
CPU time 207.01 seconds
Started Sep 18 04:22:11 PM UTC 24
Finished Sep 18 04:25:41 PM UTC 24
Peak memory 277080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2719470161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.a
lert_handler_stress_all_with_rand_reset.2719470161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.3015164243
Short name T54
Test name
Test status
Simulation time 82325825 ps
CPU time 5.61 seconds
Started Sep 18 02:51:45 PM UTC 24
Finished Sep 18 02:51:52 PM UTC 24
Peak memory 260772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015164243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3015164243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.1837135799
Short name T307
Test name
Test status
Simulation time 4200977845 ps
CPU time 727.27 seconds
Started Sep 18 02:51:24 PM UTC 24
Finished Sep 18 03:03:41 PM UTC 24
Peak memory 283040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837135799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1837135799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.3474660880
Short name T24
Test name
Test status
Simulation time 493976126 ps
CPU time 30.7 seconds
Started Sep 18 02:51:37 PM UTC 24
Finished Sep 18 02:52:09 PM UTC 24
Peak memory 260572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474660880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3474660880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.3273633826
Short name T106
Test name
Test status
Simulation time 535605570 ps
CPU time 21.8 seconds
Started Sep 18 02:51:21 PM UTC 24
Finished Sep 18 02:51:44 PM UTC 24
Peak memory 260460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273633826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3273633826
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.2679989730
Short name T105
Test name
Test status
Simulation time 600686934 ps
CPU time 20.5 seconds
Started Sep 18 02:51:18 PM UTC 24
Finished Sep 18 02:51:40 PM UTC 24
Peak memory 266572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679989730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2679989730
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.3243833850
Short name T305
Test name
Test status
Simulation time 17402772553 ps
CPU time 1514.28 seconds
Started Sep 18 02:51:37 PM UTC 24
Finished Sep 18 03:17:10 PM UTC 24
Peak memory 299552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243833850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3243833850
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.51209877
Short name T83
Test name
Test status
Simulation time 1272560648 ps
CPU time 36.6 seconds
Started Sep 18 02:51:09 PM UTC 24
Finished Sep 18 02:51:47 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51209877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran
dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.51209877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.993664579
Short name T46
Test name
Test status
Simulation time 1664976917 ps
CPU time 25.22 seconds
Started Sep 18 02:51:10 PM UTC 24
Finished Sep 18 02:51:37 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993664579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.993664579
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.246997055
Short name T90
Test name
Test status
Simulation time 95838109 ps
CPU time 11.83 seconds
Started Sep 18 02:51:23 PM UTC 24
Finished Sep 18 02:51:36 PM UTC 24
Peak memory 260700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246997055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.246997055
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.2508421409
Short name T107
Test name
Test status
Simulation time 972778240 ps
CPU time 34.39 seconds
Started Sep 18 02:51:09 PM UTC 24
Finished Sep 18 02:51:45 PM UTC 24
Peak memory 260692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508421409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2508421409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.2621220915
Short name T116
Test name
Test status
Simulation time 404465579377 ps
CPU time 2418.4 seconds
Started Sep 18 02:51:41 PM UTC 24
Finished Sep 18 03:32:28 PM UTC 24
Peak memory 299548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621220915 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.2621220915
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all_with_rand_reset.2830564012
Short name T32
Test name
Test status
Simulation time 14248024669 ps
CPU time 444.87 seconds
Started Sep 18 02:51:46 PM UTC 24
Finished Sep 18 02:59:17 PM UTC 24
Peak memory 283412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2830564012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.al
ert_handler_stress_all_with_rand_reset.2830564012
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.1749011108
Short name T127
Test name
Test status
Simulation time 31298089 ps
CPU time 4.39 seconds
Started Sep 18 02:52:46 PM UTC 24
Finished Sep 18 02:52:51 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749011108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1749011108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.1488645258
Short name T313
Test name
Test status
Simulation time 14814512041 ps
CPU time 1363.87 seconds
Started Sep 18 02:52:12 PM UTC 24
Finished Sep 18 03:15:12 PM UTC 24
Peak memory 297428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488645258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1488645258
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.2130438592
Short name T25
Test name
Test status
Simulation time 1976427626 ps
CPU time 21.06 seconds
Started Sep 18 02:52:23 PM UTC 24
Finished Sep 18 02:52:45 PM UTC 24
Peak memory 260764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130438592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2130438592
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.1290812453
Short name T137
Test name
Test status
Simulation time 37167209542 ps
CPU time 250.94 seconds
Started Sep 18 02:52:00 PM UTC 24
Finished Sep 18 02:56:15 PM UTC 24
Peak memory 266712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290812453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1290812453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.1219707810
Short name T91
Test name
Test status
Simulation time 73661654 ps
CPU time 4.64 seconds
Started Sep 18 02:51:54 PM UTC 24
Finished Sep 18 02:52:00 PM UTC 24
Peak memory 250188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219707810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1219707810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.2903102490
Short name T293
Test name
Test status
Simulation time 11670492434 ps
CPU time 992.99 seconds
Started Sep 18 02:52:16 PM UTC 24
Finished Sep 18 03:09:01 PM UTC 24
Peak memory 283356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903102490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2903102490
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.519892052
Short name T468
Test name
Test status
Simulation time 113922030451 ps
CPU time 2122.58 seconds
Started Sep 18 02:52:22 PM UTC 24
Finished Sep 18 03:28:11 PM UTC 24
Peak memory 299808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519892052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.519892052
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.1512328485
Short name T310
Test name
Test status
Simulation time 17988415848 ps
CPU time 310.4 seconds
Started Sep 18 02:52:12 PM UTC 24
Finished Sep 18 02:57:26 PM UTC 24
Peak memory 260640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512328485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1512328485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.327599971
Short name T250
Test name
Test status
Simulation time 17544713 ps
CPU time 4.66 seconds
Started Sep 18 02:51:48 PM UTC 24
Finished Sep 18 02:51:54 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327599971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.327599971
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.4079598146
Short name T84
Test name
Test status
Simulation time 692347814 ps
CPU time 16.13 seconds
Started Sep 18 02:51:53 PM UTC 24
Finished Sep 18 02:52:10 PM UTC 24
Peak memory 260464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079598146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.4079598146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.1446569260
Short name T85
Test name
Test status
Simulation time 1373645724 ps
CPU time 32.7 seconds
Started Sep 18 02:51:48 PM UTC 24
Finished Sep 18 02:52:22 PM UTC 24
Peak memory 266572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446569260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1446569260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.2774194675
Short name T125
Test name
Test status
Simulation time 15427813669 ps
CPU time 842.38 seconds
Started Sep 18 02:52:26 PM UTC 24
Finished Sep 18 03:06:39 PM UTC 24
Peak memory 283088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774194675 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.2774194675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all_with_rand_reset.2153791744
Short name T47
Test name
Test status
Simulation time 386233395 ps
CPU time 82.74 seconds
Started Sep 18 02:52:48 PM UTC 24
Finished Sep 18 02:54:13 PM UTC 24
Peak memory 283412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2153791744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.al
ert_handler_stress_all_with_rand_reset.2153791744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.1678036161
Short name T238
Test name
Test status
Simulation time 29452795 ps
CPU time 5.03 seconds
Started Sep 18 02:53:40 PM UTC 24
Finished Sep 18 02:53:46 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678036161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1678036161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.2436392903
Short name T484
Test name
Test status
Simulation time 32847175608 ps
CPU time 2366.33 seconds
Started Sep 18 02:53:01 PM UTC 24
Finished Sep 18 03:32:55 PM UTC 24
Peak memory 299556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436392903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2436392903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.1737867937
Short name T29
Test name
Test status
Simulation time 97225359 ps
CPU time 10.04 seconds
Started Sep 18 02:53:30 PM UTC 24
Finished Sep 18 02:53:42 PM UTC 24
Peak memory 260508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737867937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1737867937
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.3393899688
Short name T79
Test name
Test status
Simulation time 7372259556 ps
CPU time 167.05 seconds
Started Sep 18 02:52:53 PM UTC 24
Finished Sep 18 02:55:43 PM UTC 24
Peak memory 266736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393899688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3393899688
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.3667583311
Short name T93
Test name
Test status
Simulation time 12227457181 ps
CPU time 71.17 seconds
Started Sep 18 02:52:53 PM UTC 24
Finished Sep 18 02:54:06 PM UTC 24
Peak memory 266772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667583311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3667583311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.3938527097
Short name T301
Test name
Test status
Simulation time 169187513230 ps
CPU time 1730.64 seconds
Started Sep 18 02:53:13 PM UTC 24
Finished Sep 18 03:22:24 PM UTC 24
Peak memory 299484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938527097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3938527097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.4023653828
Short name T303
Test name
Test status
Simulation time 28655093963 ps
CPU time 995.54 seconds
Started Sep 18 02:53:30 PM UTC 24
Finished Sep 18 03:10:19 PM UTC 24
Peak memory 293664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023653828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.4023653828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.3877561249
Short name T314
Test name
Test status
Simulation time 24038539389 ps
CPU time 251.1 seconds
Started Sep 18 02:53:03 PM UTC 24
Finished Sep 18 02:57:17 PM UTC 24
Peak memory 260636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877561249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3877561249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.3793284205
Short name T86
Test name
Test status
Simulation time 2694289846 ps
CPU time 67.68 seconds
Started Sep 18 02:53:00 PM UTC 24
Finished Sep 18 02:54:10 PM UTC 24
Peak memory 266640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793284205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3793284205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.3191377760
Short name T92
Test name
Test status
Simulation time 76503855 ps
CPU time 9.85 seconds
Started Sep 18 02:52:49 PM UTC 24
Finished Sep 18 02:53:00 PM UTC 24
Peak memory 266836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191377760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3191377760
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.3543462647
Short name T340
Test name
Test status
Simulation time 34019054045 ps
CPU time 1685.8 seconds
Started Sep 18 02:53:36 PM UTC 24
Finished Sep 18 03:22:01 PM UTC 24
Peak memory 309788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543462647 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.3543462647
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.3843133128
Short name T239
Test name
Test status
Simulation time 106582872 ps
CPU time 4.8 seconds
Started Sep 18 02:54:45 PM UTC 24
Finished Sep 18 02:54:51 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843133128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3843133128
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.1230721528
Short name T69
Test name
Test status
Simulation time 131103625406 ps
CPU time 1628.35 seconds
Started Sep 18 02:54:10 PM UTC 24
Finished Sep 18 03:21:38 PM UTC 24
Peak memory 283168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230721528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1230721528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.3061808612
Short name T160
Test name
Test status
Simulation time 875243856 ps
CPU time 32.96 seconds
Started Sep 18 02:54:28 PM UTC 24
Finished Sep 18 02:55:02 PM UTC 24
Peak memory 260504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061808612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3061808612
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.1686122849
Short name T259
Test name
Test status
Simulation time 3713645511 ps
CPU time 160.9 seconds
Started Sep 18 02:54:06 PM UTC 24
Finished Sep 18 02:56:50 PM UTC 24
Peak memory 266740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686122849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1686122849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.3843872050
Short name T96
Test name
Test status
Simulation time 690894304 ps
CPU time 32.41 seconds
Started Sep 18 02:53:58 PM UTC 24
Finished Sep 18 02:54:32 PM UTC 24
Peak memory 260428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843872050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3843872050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.3713004290
Short name T331
Test name
Test status
Simulation time 210444430366 ps
CPU time 2247.48 seconds
Started Sep 18 02:54:15 PM UTC 24
Finished Sep 18 03:32:07 PM UTC 24
Peak memory 293660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713004290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3713004290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.1302067429
Short name T465
Test name
Test status
Simulation time 138048578578 ps
CPU time 1952.51 seconds
Started Sep 18 02:54:24 PM UTC 24
Finished Sep 18 03:27:20 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302067429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1302067429
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.816778285
Short name T395
Test name
Test status
Simulation time 2453329947 ps
CPU time 87.28 seconds
Started Sep 18 02:53:47 PM UTC 24
Finished Sep 18 02:55:16 PM UTC 24
Peak memory 266712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816778285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.816778285
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.1612479307
Short name T126
Test name
Test status
Simulation time 515049060 ps
CPU time 32.97 seconds
Started Sep 18 02:53:53 PM UTC 24
Finished Sep 18 02:54:27 PM UTC 24
Peak memory 266588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612479307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1612479307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.356576792
Short name T87
Test name
Test status
Simulation time 582873473 ps
CPU time 35.95 seconds
Started Sep 18 02:54:07 PM UTC 24
Finished Sep 18 02:54:45 PM UTC 24
Peak memory 260508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356576792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.356576792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.405297828
Short name T161
Test name
Test status
Simulation time 220249269 ps
CPU time 29.44 seconds
Started Sep 18 02:53:43 PM UTC 24
Finished Sep 18 02:54:13 PM UTC 24
Peak memory 260440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405297828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.405297828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.2458416014
Short name T80
Test name
Test status
Simulation time 5029641412 ps
CPU time 69.38 seconds
Started Sep 18 02:54:32 PM UTC 24
Finished Sep 18 02:55:43 PM UTC 24
Peak memory 266708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458416014 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.2458416014
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/8.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.281973002
Short name T82
Test name
Test status
Simulation time 145016236 ps
CPU time 5.31 seconds
Started Sep 18 02:55:44 PM UTC 24
Finished Sep 18 02:55:50 PM UTC 24
Peak memory 260700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281973002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.281973002
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.710412080
Short name T516
Test name
Test status
Simulation time 44493666066 ps
CPU time 2909.16 seconds
Started Sep 18 02:55:27 PM UTC 24
Finished Sep 18 03:44:29 PM UTC 24
Peak memory 300080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710412080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.710412080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.1675122136
Short name T81
Test name
Test status
Simulation time 88537680 ps
CPU time 10.46 seconds
Started Sep 18 02:55:35 PM UTC 24
Finished Sep 18 02:55:47 PM UTC 24
Peak memory 260432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675122136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1675122136
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.1983014682
Short name T402
Test name
Test status
Simulation time 17481665542 ps
CPU time 171.33 seconds
Started Sep 18 02:55:17 PM UTC 24
Finished Sep 18 02:58:11 PM UTC 24
Peak memory 266804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983014682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1983014682
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.2793130241
Short name T97
Test name
Test status
Simulation time 125270365 ps
CPU time 13.61 seconds
Started Sep 18 02:55:14 PM UTC 24
Finished Sep 18 02:55:29 PM UTC 24
Peak memory 260500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793130241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2793130241
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.2271620609
Short name T302
Test name
Test status
Simulation time 103220878364 ps
CPU time 1565.09 seconds
Started Sep 18 02:55:30 PM UTC 24
Finished Sep 18 03:21:53 PM UTC 24
Peak memory 283164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271620609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2271620609
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.1302196521
Short name T479
Test name
Test status
Simulation time 129846734145 ps
CPU time 2106.62 seconds
Started Sep 18 02:55:34 PM UTC 24
Finished Sep 18 03:31:05 PM UTC 24
Peak memory 283096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302196521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1302196521
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.2433372154
Short name T396
Test name
Test status
Simulation time 736113264 ps
CPU time 21.44 seconds
Started Sep 18 02:55:04 PM UTC 24
Finished Sep 18 02:55:26 PM UTC 24
Peak memory 266644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433372154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2433372154
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.2163219305
Short name T59
Test name
Test status
Simulation time 312085423 ps
CPU time 20.64 seconds
Started Sep 18 02:55:14 PM UTC 24
Finished Sep 18 02:55:36 PM UTC 24
Peak memory 266648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163219305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2163219305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.2845544917
Short name T88
Test name
Test status
Simulation time 7500402602 ps
CPU time 62.52 seconds
Started Sep 18 02:55:17 PM UTC 24
Finished Sep 18 02:56:21 PM UTC 24
Peak memory 266968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845544917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2845544917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.3911516860
Short name T397
Test name
Test status
Simulation time 1882787581 ps
CPU time 40.94 seconds
Started Sep 18 02:54:52 PM UTC 24
Finished Sep 18 02:55:35 PM UTC 24
Peak memory 266836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911516860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3911516860
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all_with_rand_reset.1181420660
Short name T60
Test name
Test status
Simulation time 2925994076 ps
CPU time 119.76 seconds
Started Sep 18 02:55:44 PM UTC 24
Finished Sep 18 02:57:46 PM UTC 24
Peak memory 277004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1181420660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.al
ert_handler_stress_all_with_rand_reset.1181420660
Directory /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest
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