Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	45717	1			T3	8		T13	1		T45	561
class_i[0x1]	55586	1			T45	401		T49	3		T36	692
class_i[0x2]	41398	1			T3	1		T17	4		T84	4
class_i[0x3]	62999	1			T3	3		T47	562		T17	2

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	51079	1			T3	3		T13	1		T45	281
alert[0x1]	51792	1			T3	3		T45	438		T47	180
alert[0x2]	51667	1			T45	217		T49	239		T18	8
alert[0x3]	51162	1			T3	6		T45	26		T84	3

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

205436

1

T3

12

T13

1

T45

962

esc_ping_fail

264

1

T17

2

T18

5

T19

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	51003	1			T3	3		T13	1		T45	281
esc_integrity_fail	alert[0x1]	51720	1			T3	3		T45	438		T47	180
esc_integrity_fail	alert[0x2]	51616	1			T45	217		T49	239		T18	6
esc_integrity_fail	alert[0x3]	51097	1			T3	6		T45	26		T84	3
esc_ping_fail	alert[0x0]	76	1			T17	1		T274	2		T74	2
esc_ping_fail	alert[0x1]	72	1			T17	1		T18	2		T19	1
esc_ping_fail	alert[0x2]	51	1			T18	2		T19	1		T274	2
esc_ping_fail	alert[0x3]	65	1			T18	1		T274	1		T74	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	45647	1			T3	8		T13	1		T45	561
esc_integrity_fail	class_i[0x1]	55505	1			T45	401		T49	3		T36	692
esc_integrity_fail	class_i[0x2]	41323	1			T3	1		T17	4		T84	4
esc_integrity_fail	class_i[0x3]	62961	1			T3	3		T47	562		T49	535
esc_ping_fail	class_i[0x0]	70	1			T18	2		T19	2		T337	1
esc_ping_fail	class_i[0x1]	81	1			T74	9		T337	2		T357	1
esc_ping_fail	class_i[0x2]	75	1			T18	2		T274	6		T74	1
esc_ping_fail	class_i[0x3]	38	1			T17	2		T18	1		T336	2