Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	567670942	0	0	632
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	567670942	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	567670942	567497677	0	0
tb.dut.CheckAccuCntDw	0	0	632	632	0	0
tb.dut.CheckEscCntDw	0	0	632	632	0	0
tb.dut.CheckNAlerts	0	0	632	632	0	0
tb.dut.CheckNClasses	0	0	632	632	0	0
tb.dut.CheckNEscSev	0	0	632	632	0	0
tb.dut.CrashdumpKnownO_A	0	0	567670942	567497677	0	0
tb.dut.EdnKnownO_A	0	0	567670942	567497677	0	0
tb.dut.EscPKnownO_A	0	0	567670942	567497677	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	567670942	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	567670942	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	567670942	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	567670942	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	567670942	80	0	0
tb.dut.IrqAKnownO_A	0	0	567670942	567497677	0	0
tb.dut.IrqBKnownO_A	0	0	567670942	567497677	0	0
tb.dut.IrqCKnownO_A	0	0	567670942	567497677	0	0
tb.dut.IrqDKnownO_A	0	0	567670942	567497677	0	0
tb.dut.TlAReadyKnownO_A	0	0	567670942	567497677	0	0
tb.dut.TlDValidKnownO_A	0	0	567670942	567497677	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	593709446	260148	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	593709446	13605	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	593709446	13661	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	593709446	13866	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	593709446	13792	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	593709446	13688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	593709446	12438	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	593709446	12582	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	593709446	12669	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	593709446	12299	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	593709446	13609	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	593709446	13690	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	593709446	12414	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	593709446	13928	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	593709446	12743	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	593709446	12469	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	593709446	12664	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	593709446	15023	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	593709446	12429	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	593709446	12687	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	593709446	12920	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	593709446	15036	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	593709446	13757	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	593709446	12610	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	593709446	12546	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	593709446	13576	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	593709446	12303	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	593709446	13975	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	593709446	12374	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	593709446	13547	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	593709446	12431	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	593709446	13521	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	593709446	13726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	593709446	12573	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	593709446	14931	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	593709446	12637	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	593709446	13754	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	593709446	13350	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	593709446	13943	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	593709446	13861	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	593709446	14857	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	593709446	13737	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	593709446	12540	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	593709446	13822	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	593709446	12569	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	593709446	13463	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	593709446	12551	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	593709446	13596	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	593709446	12592	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	593709446	13665	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	593709446	13571	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	593709446	13537	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	593709446	12571	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	593709446	14745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	593709446	12500	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	593709446	13836	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	593709446	12651	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	593709446	12511	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	593709446	13528	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	593709446	13778	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	593709446	13523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	593709446	14677	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	593709446	12703	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	593709446	12760	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	593709446	13637	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	593709446	12543	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	593709446	12689	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	593709446	12720	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	593709446	13628	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	593709446	13832	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	593709446	22853	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	593709446	13606	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	593709446	13628	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	593709446	12777	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	593709446	14942	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	593709446	13842	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	593709446	12599	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	593709446	13766	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	593709446	12424	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	567670942	2387	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	567670942	183467	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	567670942	274977696	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	567670942	233	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	567670942	817	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	567670942	48	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	567670942	385	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	567510543	200990571	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	567670942	904	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	567670942	883	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	567670942	859	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	567670942	831	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	567670942	1148	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	567670942	111718	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	567670942	1029	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	567670942	64	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	567670942	1313	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	567670942	1073	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	567509227	567437396	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	567670942	567497677	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	567670942	4118	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	567670942	170180	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	567670942	320885519	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	567670942	222	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	567670942	493	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	567670942	14	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	567670942	209	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	567510543	245229440	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	567670942	534	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	567670942	527	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	567670942	512	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	567670942	500	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	567670942	444	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	567670942	62610	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	567670942	385	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	567670942	43	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	567670942	1316	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	567670942	1076	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	567509227	567437396	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	567670942	567497677	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	567670942	3427	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	567670942	183957	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	567670942	265660391	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	567670942	220	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	567670942	501	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	567670942	26	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	567670942	216	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	567510543	209108836	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	567670942	548	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	567670942	541	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	567670942	534	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	567670942	520	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	567670942	689	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	567670942	71751	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	567670942	620	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	567670942	38	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	567670942	1282	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	567670942	1042	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	567509227	567437396	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	567670942	567497677	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	567670942	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	567670942	1731	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	567670942	203894	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	567670942	286820530	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	567670942	225	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	567670942	535	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	567670942	16	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	567670942	246	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	567510543	203700572	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	567670942	617	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	567670942	605	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	567670942	598	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	567670942	588	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	567670942	852	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	567670942	98131	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	567670942	757	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	567670942	73	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	567670942	1227	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	567670942	987	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	567509227	567437396	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	567670942	567497677	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	593709446	83782223	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	593709446	592992503	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	593709446	592992503	0	0
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