Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.83	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	44	5	39	88.64

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	1	10	90.91	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	5	39	88.64	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	149	1			T240	1		T241	1		T36	1
index[0x1]	155	1			T44	2		T45	1		T47	1
index[0x2]	155	1			T77	1		T20	1		T17	1
index[0x3]	172	1			T10	1		T12	1		T67	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	1	10	90.91

User Defined Bins for esc_sig_len_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
lens_less_than_1000[9]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	216	1			T10	1		T67	1		T26	1
lens_less_than_1000[1]	129	1			T12	1		T240	1		T241	1
lens_less_than_1000[2]	84	1			T44	2		T45	1		T80	1
lens_less_than_1000[3]	64	1			T77	1		T17	1		T90	1
lens_less_than_1000[4]	34	1			T136	1		T275	1		T29	1
lens_less_than_1000[5]	42	1			T20	1		T136	1		T36	1
lens_less_than_1000[6]	20	1			T58	1		T276	2		T277	1
lens_less_than_1000[7]	18	1			T241	1		T243	1		T35	1
lens_less_than_1000[8]	14	1			T241	1		T37	1		T278	2
len_2	10	1			T95	1		T105	3		T279	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	5	39	88.64	5

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0] , index[0x1]]	[lens_less_than_1000[9]]	--	--	2
[index[0x2]]	[lens_less_than_1000[9] , len_2]	--	--	2
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	52	1			T271	1		T31	1		T101	1
index[0x0]	lens_less_than_1000[1]	31	1			T240	1		T280	1		T31	1
index[0x0]	lens_less_than_1000[2]	17	1			T29	1		T93	1		T98	1
index[0x0]	lens_less_than_1000[3]	14	1			T281	1		T282	1		T283	1
index[0x0]	lens_less_than_1000[4]	7	1			T29	1		T284	1		T110	1
index[0x0]	lens_less_than_1000[5]	17	1			T36	1		T81	2		T285	1
index[0x0]	lens_less_than_1000[6]	3	1			T58	1		T286	1		T287	1
index[0x0]	lens_less_than_1000[7]	3	1			T241	1		T72	1		T92	1
index[0x0]	lens_less_than_1000[8]	2	1			T278	2		-	-		-	-
index[0x0]	len_2	3	1			T105	2		T288	1		-	-
index[0x1]	lens_less_than_1000[0]	54	1			T47	1		T37	1		T80	1
index[0x1]	lens_less_than_1000[1]	30	1			T37	1		T52	3		T81	3
index[0x1]	lens_less_than_1000[2]	18	1			T44	2		T45	1		T80	1
index[0x1]	lens_less_than_1000[3]	16	1			T289	1		T113	1		T290	1
index[0x1]	lens_less_than_1000[4]	8	1			T291	1		T247	1		T292	6
index[0x1]	lens_less_than_1000[5]	7	1			T61	1		T293	1		T246	1
index[0x1]	lens_less_than_1000[6]	4	1			T276	1		T294	1		T295	1
index[0x1]	lens_less_than_1000[7]	10	1			T243	1		T105	1		T117	1
index[0x1]	lens_less_than_1000[8]	3	1			T241	1		T37	1		T130	1
index[0x1]	len_2	5	1			T105	1		T279	1		T296	1
index[0x2]	lens_less_than_1000[0]	45	1			T137	1		T297	1		T31	1
index[0x2]	lens_less_than_1000[1]	34	1			T241	1		T90	1		T86	1
index[0x2]	lens_less_than_1000[2]	21	1			T127	1		T59	1		T298	1
index[0x2]	lens_less_than_1000[3]	19	1			T77	1		T17	1		T299	1
index[0x2]	lens_less_than_1000[4]	12	1			T136	1		T275	1		T102	1
index[0x2]	lens_less_than_1000[5]	9	1			T20	1		T69	1		T275	1
index[0x2]	lens_less_than_1000[6]	9	1			T276	1		T277	1		T300	1
index[0x2]	lens_less_than_1000[7]	2	1			T301	1		T302	1		-	-
index[0x2]	lens_less_than_1000[8]	4	1			T109	4		-	-		-	-
index[0x3]	lens_less_than_1000[0]	65	1			T10	1		T67	1		T26	1
index[0x3]	lens_less_than_1000[1]	34	1			T12	1		T146	1		T101	1
index[0x3]	lens_less_than_1000[2]	28	1			T93	1		T60	1		T303	1
index[0x3]	lens_less_than_1000[3]	15	1			T90	1		T19	2		T31	1
index[0x3]	lens_less_than_1000[4]	7	1			T102	1		T304	1		T118	1
index[0x3]	lens_less_than_1000[5]	9	1			T136	1		T101	1		T305	1
index[0x3]	lens_less_than_1000[6]	4	1			T251	1		T306	1		T307	1
index[0x3]	lens_less_than_1000[7]	3	1			T35	1		T111	1		T295	1
index[0x3]	lens_less_than_1000[8]	5	1			T122	1		T308	1		T309	1
index[0x3]	len_2	2	1			T95	1		T310	1		-	-