Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	64	1			T31	2		T91	1		T92	1
class_index[0x1]	43	1			T12	1		T14	1		T78	1
class_index[0x2]	38	1			T26	2		T87	1		T88	1
class_index[0x3]	73	1			T12	1		T37	3		T136	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	89	1			T12	1		T14	1		T26	1
intr_timeout_cnt[1]	48	1			T12	1		T82	1		T36	1
intr_timeout_cnt[2]	22	1			T26	1		T69	1		T31	1
intr_timeout_cnt[3]	8	1			T136	1		T127	1		T95	1
intr_timeout_cnt[4]	11	1			T88	1		T105	1		T311	1
intr_timeout_cnt[5]	11	1			T68	1		T312	2		T313	1
intr_timeout_cnt[6]	8	1			T37	1		T36	1		T314	1
intr_timeout_cnt[7]	12	1			T36	1		T93	1		T105	2
intr_timeout_cnt[8]	6	1			T37	1		T91	1		T120	1
intr_timeout_cnt[9]	3	1			T315	1		T259	1		T316	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[3]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	26	1			T92	1		T93	1		T58	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T31	1		T97	1		T98	1
class_index[0x0]	intr_timeout_cnt[2]	9	1			T31	1		T64	1		T317	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T95	1		T39	1		T270	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T105	1		T287	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	2	1			T107	1		T302	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T314	1		T283	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	4	1			T125	2		T318	1		T302	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T91	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	16	1			T14	1		T78	1		T86	1
class_index[0x1]	intr_timeout_cnt[1]	8	1			T12	1		T82	1		T72	1
class_index[0x1]	intr_timeout_cnt[2]	3	1			T319	1		T320	1		T310	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T62	1		T321	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	2	1			T311	1		T259	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T313	1		T107	1		T302	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T315	1		T245	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	3	1			T93	1		T105	1		T322	1
class_index[0x1]	intr_timeout_cnt[8]	2	1			T118	1		T288	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T315	1		T316	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	18	1			T26	1		T72	1		T120	1
class_index[0x2]	intr_timeout_cnt[1]	7	1			T87	1		T323	1		T324	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T26	1		T69	1		T62	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T88	1		T320	1		T302	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T68	1		T310	1		T302	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T128	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T120	1		T254	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T259	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	29	1			T12	1		T37	1		T72	1
class_index[0x3]	intr_timeout_cnt[1]	18	1			T36	1		T147	1		T148	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T311	1		T301	1		T107	2
class_index[0x3]	intr_timeout_cnt[3]	3	1			T136	1		T127	1		T325	1
class_index[0x3]	intr_timeout_cnt[4]	4	1			T39	1		T259	2		T326	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T312	2		T327	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	3	1			T37	1		T36	1		T328	1
class_index[0x3]	intr_timeout_cnt[7]	5	1			T36	1		T105	1		T125	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T37	1		-	-		-	-