Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	295337	1			T3	4		T9	17		T10	15
all_pins[1]	295337	1			T3	4		T9	17		T10	15
all_pins[2]	295337	1			T3	4		T9	17		T10	15
all_pins[3]	295337	1			T3	4		T9	17		T10	15

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	939965	1			T3	13		T9	65		T10	46
values[0x1]	241383	1			T3	3		T9	3		T10	14
transitions[0x0=>0x1]	160098	1			T3	2		T9	3		T10	8
transitions[0x1=>0x0]	160346	1			T3	3		T9	3		T10	9

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	234032	1			T3	3		T9	14		T10	11
all_pins[0]	values[0x1]	61305	1			T3	1		T9	3		T10	4
all_pins[0]	transitions[0x0=>0x1]	60747	1			T9	3		T10	3		T16	1
all_pins[0]	transitions[0x1=>0x0]	60237	1			T3	2		T10	2		T16	1
all_pins[1]	values[0x0]	235434	1			T3	4		T9	17		T10	11
all_pins[1]	values[0x1]	59903	1			T10	4		T16	2		T12	4
all_pins[1]	transitions[0x0=>0x1]	32717	1			T10	2		T16	1		T12	3
all_pins[1]	transitions[0x1=>0x0]	34119	1			T3	1		T9	3		T10	2
all_pins[2]	values[0x0]	235709	1			T3	4		T9	17		T10	11
all_pins[2]	values[0x1]	59628	1			T10	4		T12	3		T13	6
all_pins[2]	transitions[0x0=>0x1]	32824	1			T10	2		T12	1		T13	3
all_pins[2]	transitions[0x1=>0x0]	33099	1			T10	2		T16	2		T12	2
all_pins[3]	values[0x0]	234790	1			T3	2		T9	17		T10	13
all_pins[3]	values[0x1]	60547	1			T3	2		T10	2		T16	1
all_pins[3]	transitions[0x0=>0x1]	33810	1			T3	2		T10	1		T16	1
all_pins[3]	transitions[0x1=>0x0]	32891	1			T10	3		T12	1		T13	5