Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T207	4		T208	7		T242	7
all_values[1]	284	1			T207	4		T208	7		T242	7
all_values[2]	284	1			T207	4		T208	7		T242	7
all_values[3]	284	1			T207	4		T208	7		T242	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

625

1

T207

9

T208

14

T242

21

auto[1]

511

1

T207

7

T208

14

T242

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

408

1

T207

3

T208

11

T242

9

auto[1]

728

1

T207

13

T208

17

T242

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

644

1

T207

10

T208

17

T242

14

auto[1]

492

1

T207

6

T208

11

T242

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

75

1

T208

1

T242

1

T399

1

all_values[0]

auto[0]

auto[0]

auto[1]

33

1

T207

2

T208

2

T242

1

all_values[0]

auto[0]

auto[1]

auto[0]

40

1

T208

2

T400

3

T401

1

all_values[0]

auto[0]

auto[1]

auto[1]

21

1

T207

1

T242

1

T402

1

all_values[0]

auto[1]

auto[0]

auto[1]

66

1

T207

1

T208

2

T242

4

all_values[0]

auto[1]

auto[1]

auto[1]

49

1

T401

1

T403

2

T404

2

all_values[1]

auto[0]

auto[0]

auto[0]

56

1

T242

3

T399

4

T402

1

all_values[1]

auto[0]

auto[0]

auto[1]

30

1

T207

2

T401

1

T404

3

all_values[1]

auto[0]

auto[1]

auto[0]

44

1

T208

1

T242

1

T401

5

all_values[1]

auto[0]

auto[1]

auto[1]

29

1

T208

3

T399

1

T400

1

all_values[1]

auto[1]

auto[0]

auto[1]

65

1

T207

1

T208

2

T242

2

all_values[1]

auto[1]

auto[1]

auto[1]

60

1

T207

1

T208

1

T242

1

all_values[2]

auto[0]

auto[0]

auto[0]

54

1

T208

3

T242

1

T403

1

all_values[2]

auto[0]

auto[0]

auto[1]

26

1

T242

2

T404

1

T405

1

all_values[2]

auto[0]

auto[1]

auto[0]

37

1

T208

2

T399

2

T400

2

all_values[2]

auto[0]

auto[1]

auto[1]

35

1

T207

2

T399

1

T401

3

all_values[2]

auto[1]

auto[0]

auto[1]

69

1

T207

1

T208

2

T242

1

all_values[2]

auto[1]

auto[1]

auto[1]

63

1

T207

1

T242

3

T399

3

all_values[3]

auto[0]

auto[0]

auto[0]

52

1

T207

2

T242

2

T399

2

all_values[3]

auto[0]

auto[0]

auto[1]

33

1

T242

1

T399

1

T403

1

all_values[3]

auto[0]

auto[1]

auto[0]

50

1

T207

1

T208

2

T242

1

all_values[3]

auto[0]

auto[1]

auto[1]

29

1

T208

1

T400

1

T401

2

all_values[3]

auto[1]

auto[0]

auto[1]

66

1

T208

2

T242

3

T399

1

all_values[3]

auto[1]

auto[1]

auto[1]

54

1

T207

1

T208

2

T399

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal