Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	89653	1			T91	6		T29	16		T277	399
accum_cnt_1000	198266	1			T47	14		T51	5		T243	55
accum_cnt_100	23531	1			T15	2		T44	5		T240	1
accum_cnt_50	68890	1			T9	4		T15	13		T12	7
accum_cnt_10	153018	1			T3	6		T9	6		T10	24
accum_cnt_0	298634	1			T3	6		T9	38		T10	8

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	218905	1			T3	3		T9	12		T10	8
class_index[0x1]	218905	1			T3	3		T9	12		T10	8
class_index[0x2]	218905	1			T3	3		T9	12		T10	8
class_index[0x3]	218905	1			T3	3		T9	12		T10	8

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	21719	1			T335	445		T32	373		T303	549
class_index[0x0]	accum_cnt_1000	44996	1			T243	55		T36	1		T271	31
class_index[0x0]	accum_cnt_100	6685	1			T15	2		T44	5		T240	1
class_index[0x0]	accum_cnt_50	17898	1			T9	4		T15	13		T13	10
class_index[0x0]	accum_cnt_10	41853	1			T3	2		T9	6		T10	5
class_index[0x0]	accum_cnt_0	74548	1			T3	1		T9	2		T10	3
class_index[0x1]	accum_cnt_2000	20625	1			T91	6		T277	261		T32	365
class_index[0x1]	accum_cnt_1000	45769	1			T51	3		T36	13		T99	12
class_index[0x1]	accum_cnt_100	5783	1			T84	5		T51	15		T36	1
class_index[0x1]	accum_cnt_50	16845	1			T12	7		T13	5		T14	20
class_index[0x1]	accum_cnt_10	32991	1			T10	7		T16	3		T12	5
class_index[0x1]	accum_cnt_0	87190	1			T3	3		T9	12		T10	1
class_index[0x2]	accum_cnt_2000	23920	1			T29	16		T277	138		T32	382
class_index[0x2]	accum_cnt_1000	57456	1			T51	2		T271	52		T146	25
class_index[0x2]	accum_cnt_100	6105	1			T51	14		T271	14		T146	22
class_index[0x2]	accum_cnt_50	12356	1			T27	6		T26	12		T82	8
class_index[0x2]	accum_cnt_10	40114	1			T3	2		T10	4		T12	12
class_index[0x2]	accum_cnt_0	68924	1			T3	1		T9	12		T10	4
class_index[0x3]	accum_cnt_2000	23389	1			T335	260		T115	212		T32	351
class_index[0x3]	accum_cnt_1000	50045	1			T47	14		T146	32		T31	48
class_index[0x3]	accum_cnt_100	4958	1			T51	12		T146	17		T31	20
class_index[0x3]	accum_cnt_50	21791	1			T26	16		T45	17		T78	8
class_index[0x3]	accum_cnt_10	38060	1			T3	2		T10	8		T12	4
class_index[0x3]	accum_cnt_0	67972	1			T3	1		T9	12		T16	3