Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2624	1			T47	1		T127	1		T69	1
alert[0x1]	1199	1			T13	44		T336	2		T92	8
alert[0x2]	5027	1			T13	4		T337	1		T57	1
alert[0x3]	3728	1			T57	3		T58	37		T338	1
alert[0x4]	8734	1			T74	1		T337	1		T58	1
alert[0x5]	8432	1			T13	1		T76	1		T337	1
alert[0x6]	5322	1			T138	18		T30	1		T339	1
alert[0x7]	2502	1			T37	6		T18	1		T76	1
alert[0x8]	5492	1			T13	8		T37	1		T274	1
alert[0x9]	3690	1			T119	53		T58	2		T285	1
alert[0xa]	10513	1			T274	2		T58	2		T138	2
alert[0xb]	4606	1			T274	1		T29	2		T337	1
alert[0xc]	6359	1			T13	29		T47	2		T29	4
alert[0xd]	3459	1			T13	7		T18	1		T274	1
alert[0xe]	1502	1			T18	1		T74	1		T340	1
alert[0xf]	9064	1			T19	1		T337	1		T119	4
alert[0x10]	7139	1			T29	3		T337	1		T119	17
alert[0x11]	4120	1			T13	21		T127	2		T76	1
alert[0x12]	5609	1			T341	1		T29	3		T57	4
alert[0x13]	8052	1			T18	1		T76	1		T119	22
alert[0x14]	7829	1			T19	1		T336	1		T74	1
alert[0x15]	2658	1			T342	1		T341	1		T29	27
alert[0x16]	1383	1			T274	1		T29	2		T340	1
alert[0x17]	4223	1			T127	26		T76	1		T341	1
alert[0x18]	4633	1			T18	1		T337	1		T119	2
alert[0x19]	6943	1			T88	1		T76	1		T29	1
alert[0x1a]	7665	1			T18	1		T342	1		T337	1
alert[0x1b]	2527	1			T274	2		T342	1		T120	7
alert[0x1c]	4315	1			T13	3		T127	4		T29	3
alert[0x1d]	2659	1			T72	2		T337	1		T119	1
alert[0x1e]	2061	1			T120	3		T343	1		T344	1
alert[0x1f]	2412	1			T76	2		T29	3		T119	4
alert[0x20]	5273	1			T119	1		T340	2		T138	24
alert[0x21]	2854	1			T18	1		T19	1		T341	1
alert[0x22]	2266	1			T92	6		T337	1		T340	1
alert[0x23]	9211	1			T341	3		T29	2		T120	1
alert[0x24]	9830	1			T74	1		T29	1		T340	1
alert[0x25]	2678	1			T274	1		T76	1		T341	1
alert[0x26]	3788	1			T37	66		T342	3		T340	1
alert[0x27]	6828	1			T18	1		T340	1		T57	7
alert[0x28]	5602	1			T19	1		T76	1		T337	1
alert[0x29]	3206	1			T74	1		T337	2		T119	9
alert[0x2a]	7680	1			T341	1		T337	1		T138	1
alert[0x2b]	13567	1			T74	1		T76	1		T119	1
alert[0x2c]	2696	1			T47	2		T76	2		T92	1
alert[0x2d]	4574	1			T342	1		T119	4		T340	1
alert[0x2e]	6758	1			T58	14		T138	12		T285	1
alert[0x2f]	2689	1			T13	1		T18	1		T69	3
alert[0x30]	4460	1			T342	1		T341	1		T119	2
alert[0x31]	5503	1			T13	11		T336	1		T74	1
alert[0x32]	7899	1			T47	1		T37	3		T336	1
alert[0x33]	1549	1			T127	1		T119	14		T340	2
alert[0x34]	1704	1			T18	1		T127	1		T74	1
alert[0x35]	4482	1			T76	1		T342	1		T119	3
alert[0x36]	6950	1			T13	1		T17	1		T69	5
alert[0x37]	9364	1			T13	2		T37	3		T119	7
alert[0x38]	3889	1			T13	21		T74	1		T58	8
alert[0x39]	2301	1			T127	1		T138	13		T285	1
alert[0x3a]	2209	1			T19	1		T305	19		T345	35
alert[0x3b]	6643	1			T29	5		T58	76		T138	4
alert[0x3c]	4917	1			T17	1		T37	2		T274	2
alert[0x3d]	6653	1			T17	1		T91	1		T342	1
alert[0x3e]	4718	1			T13	64		T74	1		T341	1
alert[0x3f]	3002	1			T127	2		T119	24		T277	1
alert[0x40]	5686	1			T47	4		T274	1		T76	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	97937	1			T19	3		T336	7		T69	4
class_i[0x1]	79579	1			T37	81		T18	1		T19	1
class_i[0x2]	59356	1			T13	217		T47	10		T17	3
class_i[0x3]	91038	1			T19	1		T127	2		T31	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

327217

1

T13

217

T47

10

T37

81

alert_ping_fail

693

1

T17

3

T18

10

T19

5

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2612	1			T47	1		T127	1		T69	1
alert_integrity_fail	alert[0x1]	1186	1			T13	44		T92	8		T138	7
alert_integrity_fail	alert[0x2]	5013	1			T13	4		T57	1		T277	10
alert_integrity_fail	alert[0x3]	3723	1			T57	3		T58	37		T346	29
alert_integrity_fail	alert[0x4]	8725	1			T58	1		T138	140		T97	2
alert_integrity_fail	alert[0x5]	8413	1			T13	1		T119	7		T93	1
alert_integrity_fail	alert[0x6]	5312	1			T138	18		T314	1		T106	636
alert_integrity_fail	alert[0x7]	2488	1			T37	6		T29	29		T346	37
alert_integrity_fail	alert[0x8]	5475	1			T13	8		T37	1		T29	9
alert_integrity_fail	alert[0x9]	3680	1			T119	53		T58	2		T305	2
alert_integrity_fail	alert[0xa]	10500	1			T58	2		T138	2		T277	1
alert_integrity_fail	alert[0xb]	4594	1			T29	2		T58	10		T305	129
alert_integrity_fail	alert[0xc]	6352	1			T13	29		T47	2		T29	4
alert_integrity_fail	alert[0xd]	3444	1			T13	7		T59	1		T346	1
alert_integrity_fail	alert[0xe]	1489	1			T58	4		T59	3		T138	3
alert_integrity_fail	alert[0xf]	9054	1			T119	4		T93	15		T278	7
alert_integrity_fail	alert[0x10]	7134	1			T29	3		T119	17		T305	148
alert_integrity_fail	alert[0x11]	4112	1			T13	21		T127	2		T29	5
alert_integrity_fail	alert[0x12]	5600	1			T29	3		T57	4		T347	31
alert_integrity_fail	alert[0x13]	8034	1			T119	22		T58	1		T346	23
alert_integrity_fail	alert[0x14]	7820	1			T29	32		T119	47		T138	81
alert_integrity_fail	alert[0x15]	2643	1			T29	27		T272	9		T348	295
alert_integrity_fail	alert[0x16]	1366	1			T29	2		T138	5		T335	3
alert_integrity_fail	alert[0x17]	4215	1			T127	26		T349	39		T346	48
alert_integrity_fail	alert[0x18]	4623	1			T119	2		T138	67		T272	14
alert_integrity_fail	alert[0x19]	6936	1			T88	1		T29	1		T119	5
alert_integrity_fail	alert[0x1a]	7652	1			T119	19		T57	51		T138	7
alert_integrity_fail	alert[0x1b]	2509	1			T120	7		T32	23		T346	53
alert_integrity_fail	alert[0x1c]	4303	1			T13	3		T127	4		T29	3
alert_integrity_fail	alert[0x1d]	2650	1			T72	2		T119	1		T58	10
alert_integrity_fail	alert[0x1e]	2053	1			T120	3		T272	120		T345	38
alert_integrity_fail	alert[0x1f]	2401	1			T29	3		T119	4		T335	1
alert_integrity_fail	alert[0x20]	5262	1			T119	1		T138	24		T305	22
alert_integrity_fail	alert[0x21]	2846	1			T29	4		T119	12		T32	14
alert_integrity_fail	alert[0x22]	2253	1			T92	6		T61	1		T346	41
alert_integrity_fail	alert[0x23]	9203	1			T29	2		T120	1		T59	2
alert_integrity_fail	alert[0x24]	9821	1			T29	1		T93	1		T138	11
alert_integrity_fail	alert[0x25]	2668	1			T120	1		T305	4		T346	41
alert_integrity_fail	alert[0x26]	3776	1			T37	66		T57	2		T305	564
alert_integrity_fail	alert[0x27]	6820	1			T57	7		T305	210		T346	4
alert_integrity_fail	alert[0x28]	5592	1			T119	7		T58	2		T305	25
alert_integrity_fail	alert[0x29]	3195	1			T119	9		T138	11		T305	15
alert_integrity_fail	alert[0x2a]	7671	1			T138	1		T335	26		T32	1
alert_integrity_fail	alert[0x2b]	13556	1			T119	1		T138	42		T272	3
alert_integrity_fail	alert[0x2c]	2678	1			T47	2		T92	1		T58	1
alert_integrity_fail	alert[0x2d]	4566	1			T119	4		T138	7		T335	1
alert_integrity_fail	alert[0x2e]	6748	1			T58	14		T138	12		T345	100
alert_integrity_fail	alert[0x2f]	2680	1			T13	1		T69	3		T119	10
alert_integrity_fail	alert[0x30]	4448	1			T119	2		T97	5		T346	14
alert_integrity_fail	alert[0x31]	5496	1			T13	11		T120	2		T96	10
alert_integrity_fail	alert[0x32]	7892	1			T47	1		T37	3		T119	32
alert_integrity_fail	alert[0x33]	1540	1			T127	1		T119	14		T138	1
alert_integrity_fail	alert[0x34]	1687	1			T127	1		T138	14		T349	3
alert_integrity_fail	alert[0x35]	4475	1			T119	3		T272	26		T348	140
alert_integrity_fail	alert[0x36]	6935	1			T13	1		T69	5		T31	2
alert_integrity_fail	alert[0x37]	9353	1			T13	2		T37	3		T119	7
alert_integrity_fail	alert[0x38]	3875	1			T13	21		T58	8		T305	5
alert_integrity_fail	alert[0x39]	2290	1			T127	1		T138	13		T305	7
alert_integrity_fail	alert[0x3a]	2202	1			T305	19		T345	35		T314	2
alert_integrity_fail	alert[0x3b]	6641	1			T29	5		T58	76		T138	4
alert_integrity_fail	alert[0x3c]	4902	1			T37	2		T29	13		T119	10
alert_integrity_fail	alert[0x3d]	6645	1			T91	1		T29	1		T138	2
alert_integrity_fail	alert[0x3e]	4708	1			T13	64		T29	4		T335	1
alert_integrity_fail	alert[0x3f]	2999	1			T127	2		T119	24		T277	1
alert_integrity_fail	alert[0x40]	5683	1			T47	4		T29	2		T119	1
alert_ping_fail	alert[0x0]	12	1			T74	1		T341	3		T298	1
alert_ping_fail	alert[0x1]	13	1			T336	2		T338	1		T343	1
alert_ping_fail	alert[0x2]	14	1			T337	1		T30	1		T343	1
alert_ping_fail	alert[0x3]	5	1			T338	1		T350	1		T258	1
alert_ping_fail	alert[0x4]	9	1			T74	1		T337	1		T282	1
alert_ping_fail	alert[0x5]	19	1			T76	1		T337	1		T340	1
alert_ping_fail	alert[0x6]	10	1			T30	1		T339	1		T282	1
alert_ping_fail	alert[0x7]	14	1			T18	1		T76	1		T351	2
alert_ping_fail	alert[0x8]	17	1			T274	1		T74	1		T341	1
alert_ping_fail	alert[0x9]	10	1			T285	1		T352	1		T344	1
alert_ping_fail	alert[0xa]	13	1			T274	2		T285	2		T353	1
alert_ping_fail	alert[0xb]	12	1			T274	1		T337	1		T338	1
alert_ping_fail	alert[0xc]	7	1			T285	1		T343	1		T354	1
alert_ping_fail	alert[0xd]	15	1			T18	1		T274	1		T336	1
alert_ping_fail	alert[0xe]	13	1			T18	1		T74	1		T340	1
alert_ping_fail	alert[0xf]	10	1			T19	1		T337	1		T338	1
alert_ping_fail	alert[0x10]	5	1			T337	1		T355	1		T356	1
alert_ping_fail	alert[0x11]	8	1			T76	1		T357	1		T338	1
alert_ping_fail	alert[0x12]	9	1			T341	1		T358	1		T359	1
alert_ping_fail	alert[0x13]	18	1			T18	1		T76	1		T340	1
alert_ping_fail	alert[0x14]	9	1			T19	1		T336	1		T74	1
alert_ping_fail	alert[0x15]	15	1			T342	1		T341	1		T340	1
alert_ping_fail	alert[0x16]	17	1			T274	1		T340	1		T339	1
alert_ping_fail	alert[0x17]	8	1			T76	1		T341	1		T340	1
alert_ping_fail	alert[0x18]	10	1			T18	1		T337	1		T285	1
alert_ping_fail	alert[0x19]	7	1			T76	1		T337	1		T340	1
alert_ping_fail	alert[0x1a]	13	1			T18	1		T342	1		T337	1
alert_ping_fail	alert[0x1b]	18	1			T274	2		T342	1		T30	2
alert_ping_fail	alert[0x1c]	12	1			T344	1		T359	2		T360	2
alert_ping_fail	alert[0x1d]	9	1			T337	1		T340	1		T351	1
alert_ping_fail	alert[0x1e]	8	1			T343	1		T344	1		T361	1
alert_ping_fail	alert[0x1f]	11	1			T76	2		T362	1		T363	1
alert_ping_fail	alert[0x20]	11	1			T340	2		T344	1		T282	2
alert_ping_fail	alert[0x21]	8	1			T18	1		T19	1		T341	1
alert_ping_fail	alert[0x22]	13	1			T337	1		T340	1		T352	1
alert_ping_fail	alert[0x23]	8	1			T341	3		T364	1		T354	1
alert_ping_fail	alert[0x24]	9	1			T74	1		T340	1		T357	1
alert_ping_fail	alert[0x25]	10	1			T274	1		T76	1		T341	1
alert_ping_fail	alert[0x26]	12	1			T342	3		T340	1		T339	2
alert_ping_fail	alert[0x27]	8	1			T18	1		T340	1		T351	1
alert_ping_fail	alert[0x28]	10	1			T19	1		T76	1		T337	1
alert_ping_fail	alert[0x29]	11	1			T74	1		T337	2		T285	1
alert_ping_fail	alert[0x2a]	9	1			T341	1		T337	1		T351	1
alert_ping_fail	alert[0x2b]	11	1			T74	1		T76	1		T365	1
alert_ping_fail	alert[0x2c]	18	1			T76	2		T340	1		T285	1
alert_ping_fail	alert[0x2d]	8	1			T342	1		T340	1		T282	1
alert_ping_fail	alert[0x2e]	10	1			T285	1		T343	1		T366	1
alert_ping_fail	alert[0x2f]	9	1			T18	1		T74	1		T340	1
alert_ping_fail	alert[0x30]	12	1			T342	1		T341	1		T340	1
alert_ping_fail	alert[0x31]	7	1			T336	1		T74	1		T76	1
alert_ping_fail	alert[0x32]	7	1			T336	1		T74	1		T343	2
alert_ping_fail	alert[0x33]	9	1			T340	2		T344	1		T364	1
alert_ping_fail	alert[0x34]	17	1			T18	1		T74	1		T76	1
alert_ping_fail	alert[0x35]	7	1			T76	1		T342	1		T339	1
alert_ping_fail	alert[0x36]	15	1			T17	1		T76	2		T337	1
alert_ping_fail	alert[0x37]	11	1			T338	1		T285	2		T344	2
alert_ping_fail	alert[0x38]	14	1			T74	1		T338	1		T339	1
alert_ping_fail	alert[0x39]	11	1			T285	1		T282	1		T359	1
alert_ping_fail	alert[0x3a]	7	1			T19	1		T351	1		T298	1
alert_ping_fail	alert[0x3b]	2	1			T367	1		T368	1		-	-
alert_ping_fail	alert[0x3c]	15	1			T17	1		T274	2		T336	1
alert_ping_fail	alert[0x3d]	8	1			T17	1		T342	1		T369	1
alert_ping_fail	alert[0x3e]	10	1			T74	1		T341	1		T338	1
alert_ping_fail	alert[0x3f]	3	1			T358	1		T370	1		T368	1
alert_ping_fail	alert[0x40]	3	1			T274	1		T76	1		T371	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	97777	1			T69	4		T29	62		T119	36
alert_integrity_fail	class_i[0x1]	79431	1			T37	81		T88	1		T127	32
alert_integrity_fail	class_i[0x2]	59147	1			T13	217		T47	10		T127	4
alert_integrity_fail	class_i[0x3]	90862	1			T127	2		T31	1		T91	1
alert_ping_fail	class_i[0x0]	160	1			T19	3		T336	7		T74	13
alert_ping_fail	class_i[0x1]	148	1			T18	1		T19	1		T274	12
alert_ping_fail	class_i[0x2]	209	1			T17	3		T18	9		T342	5
alert_ping_fail	class_i[0x3]	176	1			T19	1		T74	2		T76	18