Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.23	99.99	98.75	97.09	100.00	100.00	99.38	99.40

Total test records in report: 837

T792	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2500259575	Sep 24 02:53:56 PM UTC 24	Sep 24 02:54:17 PM UTC 24	292526523 ps
T793	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.470257593	Sep 24 02:54:12 PM UTC 24	Sep 24 02:54:18 PM UTC 24	51527539 ps
T794	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.990974858	Sep 24 02:53:54 PM UTC 24	Sep 24 02:54:20 PM UTC 24	1454327810 ps
T795	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1333523548	Sep 24 02:53:42 PM UTC 24	Sep 24 02:54:23 PM UTC 24	8103678983 ps
T796	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.3188206212	Sep 24 02:54:21 PM UTC 24	Sep 24 02:54:25 PM UTC 24	14691683 ps
T797	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1935706326	Sep 24 02:54:14 PM UTC 24	Sep 24 02:54:25 PM UTC 24	127826201 ps
T798	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.1736784697	Sep 24 02:54:23 PM UTC 24	Sep 24 02:54:30 PM UTC 24	36855268 ps
T799	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1108117927	Sep 24 02:54:14 PM UTC 24	Sep 24 02:54:30 PM UTC 24	336140379 ps
T800	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2850617084	Sep 24 02:50:53 PM UTC 24	Sep 24 02:54:33 PM UTC 24	5823294518 ps
T215	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.4060074792	Sep 24 02:52:44 PM UTC 24	Sep 24 02:54:34 PM UTC 24	895512402 ps
T174	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2199434402	Sep 24 02:50:42 PM UTC 24	Sep 24 02:54:35 PM UTC 24	1607484726 ps
T801	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.135152219	Sep 24 02:54:32 PM UTC 24	Sep 24 02:54:35 PM UTC 24	21190689 ps
T802	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.3523133840	Sep 24 02:54:31 PM UTC 24	Sep 24 02:54:35 PM UTC 24	17349923 ps
T803	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.2499162071	Sep 24 02:54:34 PM UTC 24	Sep 24 02:54:36 PM UTC 24	16087109 ps
T804	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1876043824	Sep 24 02:54:35 PM UTC 24	Sep 24 02:54:38 PM UTC 24	8583620 ps
T805	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.2235632203	Sep 24 02:54:36 PM UTC 24	Sep 24 02:54:39 PM UTC 24	25467696 ps
T806	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.2474974622	Sep 24 02:54:36 PM UTC 24	Sep 24 02:54:39 PM UTC 24	58977850 ps
T807	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2738727825	Sep 24 02:54:36 PM UTC 24	Sep 24 02:54:40 PM UTC 24	15652926 ps
T808	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.6000332	Sep 24 02:54:19 PM UTC 24	Sep 24 02:54:40 PM UTC 24	295678287 ps
T809	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.18149712	Sep 24 02:54:26 PM UTC 24	Sep 24 02:54:40 PM UTC 24	135999017 ps
T180	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1987039849	Sep 24 02:49:43 PM UTC 24	Sep 24 02:54:40 PM UTC 24	2087031601 ps
T810	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.1321141520	Sep 24 02:54:37 PM UTC 24	Sep 24 02:54:40 PM UTC 24	7889619 ps
T811	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3275047297	Sep 24 02:49:38 PM UTC 24	Sep 24 02:54:41 PM UTC 24	14271745460 ps
T812	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2950969750	Sep 24 02:54:39 PM UTC 24	Sep 24 02:54:42 PM UTC 24	9309370 ps
T813	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.856180734	Sep 24 02:54:39 PM UTC 24	Sep 24 02:54:42 PM UTC 24	32655430 ps
T178	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1875191131	Sep 24 02:51:56 PM UTC 24	Sep 24 02:54:42 PM UTC 24	13843939082 ps
T814	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2232366854	Sep 24 02:54:26 PM UTC 24	Sep 24 02:54:44 PM UTC 24	164770049 ps
T815	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.385793331	Sep 24 02:54:41 PM UTC 24	Sep 24 02:54:44 PM UTC 24	20781390 ps
T816	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1209401479	Sep 24 02:54:41 PM UTC 24	Sep 24 02:54:44 PM UTC 24	8829336 ps
T817	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.3480116323	Sep 24 02:54:41 PM UTC 24	Sep 24 02:54:44 PM UTC 24	16836118 ps
T818	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.2184882818	Sep 24 02:54:41 PM UTC 24	Sep 24 02:54:44 PM UTC 24	6499429 ps
T819	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.4209570289	Sep 24 02:54:41 PM UTC 24	Sep 24 02:54:44 PM UTC 24	20017359 ps
T820	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1665862547	Sep 24 02:54:41 PM UTC 24	Sep 24 02:54:44 PM UTC 24	25270281 ps
T821	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2913953597	Sep 24 02:54:41 PM UTC 24	Sep 24 02:54:44 PM UTC 24	28682206 ps
T822	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.3777065121	Sep 24 02:54:42 PM UTC 24	Sep 24 02:54:45 PM UTC 24	10767444 ps
T179	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.913553909	Sep 24 02:49:51 PM UTC 24	Sep 24 02:54:47 PM UTC 24	3594306028 ps
T823	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.2222416313	Sep 24 02:54:43 PM UTC 24	Sep 24 02:54:47 PM UTC 24	47608422 ps
T824	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.3195233535	Sep 24 02:54:44 PM UTC 24	Sep 24 02:54:47 PM UTC 24	11110255 ps
T825	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.1002827306	Sep 24 02:54:43 PM UTC 24	Sep 24 02:54:47 PM UTC 24	7358721 ps
T826	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2649690912	Sep 24 02:54:45 PM UTC 24	Sep 24 02:54:47 PM UTC 24	9410839 ps
T827	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.753057288	Sep 24 02:54:45 PM UTC 24	Sep 24 02:54:48 PM UTC 24	11417951 ps
T828	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.2495577354	Sep 24 02:54:45 PM UTC 24	Sep 24 02:54:48 PM UTC 24	7932793 ps
T829	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2899310911	Sep 24 02:54:45 PM UTC 24	Sep 24 02:54:48 PM UTC 24	16648945 ps
T830	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.4241602970	Sep 24 02:54:45 PM UTC 24	Sep 24 02:54:48 PM UTC 24	25121999 ps
T831	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.3006378498	Sep 24 02:54:45 PM UTC 24	Sep 24 02:54:48 PM UTC 24	9892198 ps
T832	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.3875321180	Sep 24 02:54:46 PM UTC 24	Sep 24 02:54:49 PM UTC 24	9801386 ps
T833	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.1955086977	Sep 24 02:54:46 PM UTC 24	Sep 24 02:54:49 PM UTC 24	8425657 ps
T834	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.1272151667	Sep 24 02:54:46 PM UTC 24	Sep 24 02:54:49 PM UTC 24	6752881 ps
T835	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1308158418	Sep 24 02:50:01 PM UTC 24	Sep 24 02:54:54 PM UTC 24	4255965974 ps
T222	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1076562995	Sep 24 02:53:51 PM UTC 24	Sep 24 02:55:09 PM UTC 24	3689395533 ps
T836	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3403945877	Sep 24 02:50:30 PM UTC 24	Sep 24 02:55:14 PM UTC 24	19405412290 ps
T181	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3797754007	Sep 24 02:51:02 PM UTC 24	Sep 24 02:55:14 PM UTC 24	10080978901 ps
T219	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.398695602	Sep 24 02:54:19 PM UTC 24	Sep 24 02:55:40 PM UTC 24	3722298433 ps
T182	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.882166859	Sep 24 02:50:22 PM UTC 24	Sep 24 02:55:40 PM UTC 24	26440398370 ps
T192	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4177591203	Sep 24 02:53:36 PM UTC 24	Sep 24 02:55:49 PM UTC 24	3384037124 ps
T183	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3399301412	Sep 24 02:52:41 PM UTC 24	Sep 24 02:55:55 PM UTC 24	5654909402 ps
T175	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1594185731	Sep 24 02:51:47 PM UTC 24	Sep 24 02:55:57 PM UTC 24	3817629559 ps
T191	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3018597249	Sep 24 02:52:56 PM UTC 24	Sep 24 02:56:20 PM UTC 24	9278913604 ps
T177	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1842131684	Sep 24 02:51:13 PM UTC 24	Sep 24 02:56:38 PM UTC 24	2277830351 ps
T176	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.962228101	Sep 24 02:51:26 PM UTC 24	Sep 24 02:56:42 PM UTC 24	44286684853 ps
T184	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3825357176	Sep 24 02:52:31 PM UTC 24	Sep 24 02:56:44 PM UTC 24	2258033356 ps
T186	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3314803609	Sep 24 02:54:19 PM UTC 24	Sep 24 02:56:51 PM UTC 24	1993755205 ps
T188	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1707099226	Sep 24 02:53:10 PM UTC 24	Sep 24 02:56:59 PM UTC 24	6246251303 ps
T185	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3982723276	Sep 24 02:51:13 PM UTC 24	Sep 24 02:57:34 PM UTC 24	5958686166 ps
T193	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1068726032	Sep 24 02:51:25 PM UTC 24	Sep 24 02:58:01 PM UTC 24	7098487330 ps
T189	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2660038712	Sep 24 02:52:22 PM UTC 24	Sep 24 02:58:05 PM UTC 24	9348511259 ps
T194	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3992109214	Sep 24 02:50:02 PM UTC 24	Sep 24 02:58:21 PM UTC 24	47170527438 ps
T187	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4289170831	Sep 24 02:54:00 PM UTC 24	Sep 24 02:59:01 PM UTC 24	14296623190 ps
T190	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.989710052	Sep 24 02:52:07 PM UTC 24	Sep 24 02:59:07 PM UTC 24	10770693711 ps
T837	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3389784954	Sep 24 02:50:10 PM UTC 24	Sep 24 02:59:08 PM UTC 24	8803211502 ps
T203	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.553498822	Sep 24 02:53:08 PM UTC 24	Sep 24 02:59:51 PM UTC 24	13133905746 ps
T200	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2136542133	Sep 24 02:53:45 PM UTC 24	Sep 24 03:00:41 PM UTC 24	4398607164 ps
T412	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.35428289	Sep 24 02:51:44 PM UTC 24	Sep 24 03:00:44 PM UTC 24	24092723388 ps
T202	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2593745918	Sep 24 02:50:57 PM UTC 24	Sep 24 03:00:48 PM UTC 24	24339927742 ps
T196	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.754679709	Sep 24 02:49:26 PM UTC 24	Sep 24 03:01:23 PM UTC 24	47500225810 ps
T197	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2880727282	Sep 24 02:53:50 PM UTC 24	Sep 24 03:01:34 PM UTC 24	11221082648 ps
T413	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3813291327	Sep 24 02:52:55 PM UTC 24	Sep 24 03:03:14 PM UTC 24	21137248262 ps
T195	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3143345541	Sep 24 02:50:19 PM UTC 24	Sep 24 03:03:31 PM UTC 24	5056970996 ps
T198	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4033820174	Sep 24 02:54:17 PM UTC 24	Sep 24 03:05:02 PM UTC 24	16940380955 ps
T410	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2487999130	Sep 24 02:52:31 PM UTC 24	Sep 24 03:06:00 PM UTC 24	19091764211 ps
T201	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3593476038	Sep 24 02:52:05 PM UTC 24	Sep 24 03:09:54 PM UTC 24	50319054750 ps
T414	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3333532961	Sep 24 02:53:32 PM UTC 24	Sep 24 03:11:48 PM UTC 24	50507068961 ps
T415	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1827934522	Sep 24 02:52:21 PM UTC 24	Sep 24 03:11:58 PM UTC 24	66003865898 ps
T199	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3738554118	Sep 24 02:50:42 PM UTC 24	Sep 24 03:13:21 PM UTC 24	13228981888 ps
T411	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.675954118	Sep 24 02:51:56 PM UTC 24	Sep 24 03:17:34 PM UTC 24	20929690047 ps
T417	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1562222947	Sep 24 02:52:39 PM UTC 24	Sep 24 03:17:55 PM UTC 24	32922926215 ps
T416	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4079902835	Sep 24 02:53:57 PM UTC 24	Sep 24 03:18:30 PM UTC 24	25272551152 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.840735680
Short name	T10
Test name
Test status
Simulation time	148694667 ps
CPU time	20.37 seconds
Started	Sep 24 02:55:43 PM UTC 24
Finished	Sep 24 02:56:04 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840735680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.840735680
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.60856261
Short name	T7
Test name
Test status
Simulation time	183056004 ps
CPU time	11.94 seconds
Started	Sep 24 02:56:02 PM UTC 24
Finished	Sep 24 02:56:15 PM UTC 24
Peak memory	294848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60856261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ha ndler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.60856261
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all_with_rand_reset.3259038935
Short name	T31
Test name
Test status
Simulation time	4124463967 ps
CPU time	542.71 seconds
Started	Sep 24 02:55:44 PM UTC 24
Finished	Sep 24 03:04:54 PM UTC 24
Peak memory	283148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3259038935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.al ert_handler_stress_all_with_rand_reset.3259038935
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.1355003885
Short name	T6
Test name
Test status
Simulation time	592621602 ps
CPU time	11.82 seconds
Started	Sep 24 02:56:39 PM UTC 24
Finished	Sep 24 02:56:53 PM UTC 24
Peak memory	260700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355003885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1355003885
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.2091491336
Short name	T12
Test name
Test status
Simulation time	3724099784 ps
CPU time	44.42 seconds
Started	Sep 24 02:55:45 PM UTC 24
Finished	Sep 24 02:56:31 PM UTC 24
Peak memory	260520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091491336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2091491336
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.4167865330
Short name	T168
Test name
Test status
Simulation time	1084779057 ps
CPU time	14.65 seconds
Started	Sep 24 02:49:35 PM UTC 24
Finished	Sep 24 02:49:51 PM UTC 24
Peak memory	248468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167865330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4167865330
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.3407903849
Short name	T47
Test name
Test status
Simulation time	745079583 ps
CPU time	33.51 seconds
Started	Sep 24 02:56:59 PM UTC 24
Finished	Sep 24 02:57:34 PM UTC 24
Peak memory	266872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407903849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3407903849
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.3580720506
Short name	T29
Test name
Test status
Simulation time	18876132672 ps
CPU time	715.58 seconds
Started	Sep 24 02:56:43 PM UTC 24
Finished	Sep 24 03:08:48 PM UTC 24
Peak memory	283476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3580720506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.al ert_handler_stress_all_with_rand_reset.3580720506
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.2906579945
Short name	T40
Test name
Test status
Simulation time	475333117 ps
CPU time	46.46 seconds
Started	Sep 24 02:57:29 PM UTC 24
Finished	Sep 24 02:58:17 PM UTC 24
Peak memory	294776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906579945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2906579945
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2830124971
Short name	T214
Test name
Test status
Simulation time	583764874 ps
CPU time	57.95 seconds
Started	Sep 24 02:49:52 PM UTC 24
Finished	Sep 24 02:50:52 PM UTC 24
Peak memory	250528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830124971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2830124971
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3982723276
Short name	T185
Test name
Test status
Simulation time	5958686166 ps
CPU time	375.39 seconds
Started	Sep 24 02:51:13 PM UTC 24
Finished	Sep 24 02:57:34 PM UTC 24
Peak memory	283752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982723276 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.3982723276
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.3682557766
Short name	T334
Test name
Test status
Simulation time	143995053398 ps
CPU time	2216.16 seconds
Started	Sep 24 03:06:05 PM UTC 24
Finished	Sep 24 03:43:26 PM UTC 24
Peak memory	283092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682557766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3682557766
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all_with_rand_reset.319485447
Short name	T84
Test name
Test status
Simulation time	1129187775 ps
CPU time	170.53 seconds
Started	Sep 24 02:56:02 PM UTC 24
Finished	Sep 24 02:58:56 PM UTC 24
Peak memory	283356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=319485447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ale rt_handler_stress_all_with_rand_reset.319485447
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all_with_rand_reset.1747087490
Short name	T110
Test name
Test status
Simulation time	4200466606 ps
CPU time	625.56 seconds
Started	Sep 24 03:40:26 PM UTC 24
Finished	Sep 24 03:51:00 PM UTC 24
Peak memory	281104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1747087490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.a lert_handler_stress_all_with_rand_reset.1747087490
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.2145794838
Short name	T118
Test name
Test status
Simulation time	50686143238 ps
CPU time	493.32 seconds
Started	Sep 24 03:43:04 PM UTC 24
Finished	Sep 24 03:51:23 PM UTC 24
Peak memory	266708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145794838 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.2145794838
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.754679709
Short name	T196
Test name
Test status
Simulation time	47500225810 ps
CPU time	705.98 seconds
Started	Sep 24 02:49:26 PM UTC 24
Finished	Sep 24 03:01:23 PM UTC 24
Peak memory	277540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754679709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow _reg_errors_with_csr_rw.754679709
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.1930678622
Short name	T346
Test name
Test status
Simulation time	22416712325 ps
CPU time	1508.97 seconds
Started	Sep 24 03:00:12 PM UTC 24
Finished	Sep 24 03:25:40 PM UTC 24
Peak memory	283096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930678622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1930678622
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3825357176
Short name	T184
Test name
Test status
Simulation time	2258033356 ps
CPU time	248.5 seconds
Started	Sep 24 02:52:31 PM UTC 24
Finished	Sep 24 02:56:44 PM UTC 24
Peak memory	277540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825357176 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.3825357176
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all_with_rand_reset.360715649
Short name	T72
Test name
Test status
Simulation time	1812560458 ps
CPU time	248.24 seconds
Started	Sep 24 03:00:49 PM UTC 24
Finished	Sep 24 03:05:02 PM UTC 24
Peak memory	277212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=360715649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.ale rt_handler_stress_all_with_rand_reset.360715649
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.503417698
Short name	T104
Test name
Test status
Simulation time	52897807696 ps
CPU time	1811.3 seconds
Started	Sep 24 03:01:35 PM UTC 24
Finished	Sep 24 03:32:07 PM UTC 24
Peak memory	283092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503417698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.503417698
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.1210011309
Short name	T76
Test name
Test status
Simulation time	54003379810 ps
CPU time	537.65 seconds
Started	Sep 24 02:56:22 PM UTC 24
Finished	Sep 24 03:05:26 PM UTC 24
Peak memory	260568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210011309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1210011309
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3143345541
Short name	T195
Test name
Test status
Simulation time	5056970996 ps
CPU time	782.31 seconds
Started	Sep 24 02:50:19 PM UTC 24
Finished	Sep 24 03:03:31 PM UTC 24
Peak memory	277740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143345541 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado w_reg_errors_with_csr_rw.3143345541
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.202040610
Short name	T373
Test name
Test status
Simulation time	151789525759 ps
CPU time	1798.3 seconds
Started	Sep 24 03:22:29 PM UTC 24
Finished	Sep 24 03:52:49 PM UTC 24
Peak memory	283352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202040610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.202040610
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all_with_rand_reset.4120268953
Short name	T138
Test name
Test status
Simulation time	6385815000 ps
CPU time	417.26 seconds
Started	Sep 24 03:09:27 PM UTC 24
Finished	Sep 24 03:16:30 PM UTC 24
Peak memory	279384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4120268953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.a lert_handler_stress_all_with_rand_reset.4120268953
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.1177357983
Short name	T26
Test name
Test status
Simulation time	2030164815 ps
CPU time	76.93 seconds
Started	Sep 24 02:55:46 PM UTC 24
Finished	Sep 24 02:57:05 PM UTC 24
Peak memory	266680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177357983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1177357983
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.3525748333
Short name	T242
Test name
Test status
Simulation time	12649929 ps
CPU time	2.28 seconds
Started	Sep 24 02:50:06 PM UTC 24
Finished	Sep 24 02:50:09 PM UTC 24
Peak memory	248624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525748333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3525748333
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2660038712
Short name	T189
Test name
Test status
Simulation time	9348511259 ps
CPU time	338.45 seconds
Started	Sep 24 02:52:22 PM UTC 24
Finished	Sep 24 02:58:05 PM UTC 24
Peak memory	277740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660038712 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.2660038712
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.284368020
Short name	T74
Test name
Test status
Simulation time	10758586623 ps
CPU time	425.26 seconds
Started	Sep 24 02:58:01 PM UTC 24
Finished	Sep 24 03:05:13 PM UTC 24
Peak memory	266780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284368020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.284368020
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.1133436116
Short name	T36
Test name
Test status
Simulation time	4456640917 ps
CPU time	50.78 seconds
Started	Sep 24 02:59:28 PM UTC 24
Finished	Sep 24 03:00:20 PM UTC 24
Peak memory	260856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133436116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1133436116
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3333532961
Short name	T414
Test name
Test status
Simulation time	50507068961 ps
CPU time	1081.12 seconds
Started	Sep 24 02:53:32 PM UTC 24
Finished	Sep 24 03:11:48 PM UTC 24
Peak memory	277536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333532961 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad ow_reg_errors_with_csr_rw.3333532961
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.231918695
Short name	T376
Test name
Test status
Simulation time	15117508057 ps
CPU time	1381.11 seconds
Started	Sep 24 03:20:05 PM UTC 24
Finished	Sep 24 03:43:25 PM UTC 24
Peak memory	295448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231918695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.231918695
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.981183546
Short name	T344
Test name
Test status
Simulation time	26457253198 ps
CPU time	451.43 seconds
Started	Sep 24 03:19:23 PM UTC 24
Finished	Sep 24 03:27:00 PM UTC 24
Peak memory	260828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981183546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.981183546
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.2535307093
Short name	T37
Test name
Test status
Simulation time	628481830 ps
CPU time	59.94 seconds
Started	Sep 24 02:57:54 PM UTC 24
Finished	Sep 24 02:58:55 PM UTC 24
Peak memory	260728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535307093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2535307093
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2199434402
Short name	T174
Test name
Test status
Simulation time	1607484726 ps
CPU time	228.95 seconds
Started	Sep 24 02:50:42 PM UTC 24
Finished	Sep 24 02:54:35 PM UTC 24
Peak memory	277740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199434402 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.2199434402
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.1866253403
Short name	T285
Test name
Test status
Simulation time	20068902479 ps
CPU time	499.21 seconds
Started	Sep 24 03:08:52 PM UTC 24
Finished	Sep 24 03:17:18 PM UTC 24
Peak memory	260572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866253403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1866253403
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.3515716256
Short name	T302
Test name
Test status
Simulation time	1188541141484 ps
CPU time	3170.52 seconds
Started	Sep 24 04:28:51 PM UTC 24
Finished	Sep 24 05:22:17 PM UTC 24
Peak memory	302316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515716256 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.3515716256
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.2418638838
Short name	T300
Test name
Test status
Simulation time	20657608849 ps
CPU time	2091.6 seconds
Started	Sep 24 02:55:50 PM UTC 24
Finished	Sep 24 03:31:06 PM UTC 24
Peak memory	302124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418638838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2418638838
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2712079268
Short name	T157
Test name
Test status
Simulation time	747703892 ps
CPU time	26.21 seconds
Started	Sep 24 02:50:02 PM UTC 24
Finished	Sep 24 02:50:30 PM UTC 24
Peak memory	258712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712079268 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.2712079268
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.2888610586
Short name	T44
Test name
Test status
Simulation time	4431759015 ps
CPU time	54.43 seconds
Started	Sep 24 02:56:05 PM UTC 24
Finished	Sep 24 02:57:00 PM UTC 24
Peak memory	266728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888610586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2888610586
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.509605196
Short name	T351
Test name
Test status
Simulation time	23120114567 ps
CPU time	471.72 seconds
Started	Sep 24 03:25:24 PM UTC 24
Finished	Sep 24 03:33:22 PM UTC 24
Peak memory	260564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509605196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.509605196
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3738554118
Short name	T199
Test name
Test status
Simulation time	13228981888 ps
CPU time	1342.56 seconds
Started	Sep 24 02:50:42 PM UTC 24
Finished	Sep 24 03:13:21 PM UTC 24
Peak memory	283756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738554118 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shado w_reg_errors_with_csr_rw.3738554118
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.416216810
Short name	T165
Test name
Test status
Simulation time	35661022 ps
CPU time	7.1 seconds
Started	Sep 24 02:50:09 PM UTC 24
Finished	Sep 24 02:50:17 PM UTC 24
Peak memory	248544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416216810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.416216810
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.3879945122
Short name	T387
Test name
Test status
Simulation time	66617330997 ps
CPU time	2709.81 seconds
Started	Sep 24 03:33:48 PM UTC 24
Finished	Sep 24 04:19:30 PM UTC 24
Peak memory	302380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879945122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3879945122
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.1253729073
Short name	T127
Test name
Test status
Simulation time	244665675 ps
CPU time	16.49 seconds
Started	Sep 24 03:01:16 PM UTC 24
Finished	Sep 24 03:01:34 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253729073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1253729073
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.1784058978
Short name	T405
Test name
Test status
Simulation time	9346903 ps
CPU time	2.63 seconds
Started	Sep 24 02:52:14 PM UTC 24
Finished	Sep 24 02:52:18 PM UTC 24
Peak memory	248496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784058978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1784058978
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.913553909
Short name	T179
Test name
Test status
Simulation time	3594306028 ps
CPU time	291.07 seconds
Started	Sep 24 02:49:51 PM UTC 24
Finished	Sep 24 02:54:47 PM UTC 24
Peak memory	283688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913553909 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.913553909
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.299689688
Short name	T62
Test name
Test status
Simulation time	39130032597 ps
CPU time	2166.78 seconds
Started	Sep 24 02:58:11 PM UTC 24
Finished	Sep 24 03:34:45 PM UTC 24
Peak memory	299472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299689688 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.299689688
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.4269775772
Short name	T367
Test name
Test status
Simulation time	22814318023 ps
CPU time	620.5 seconds
Started	Sep 24 03:49:07 PM UTC 24
Finished	Sep 24 03:59:35 PM UTC 24
Peak memory	260572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269775772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4269775772
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all_with_rand_reset.2371192332
Short name	T315
Test name
Test status
Simulation time	10158173506 ps
CPU time	343.98 seconds
Started	Sep 24 03:58:09 PM UTC 24
Finished	Sep 24 04:03:58 PM UTC 24
Peak memory	279120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2371192332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.a lert_handler_stress_all_with_rand_reset.2371192332
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.1847759677
Short name	T360
Test name
Test status
Simulation time	215195393323 ps
CPU time	3470.35 seconds
Started	Sep 24 02:59:35 PM UTC 24
Finished	Sep 24 03:58:06 PM UTC 24
Peak memory	302044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847759677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1847759677
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.2781408986
Short name	T105
Test name
Test status
Simulation time	13179316805 ps
CPU time	933.96 seconds
Started	Sep 24 03:26:37 PM UTC 24
Finished	Sep 24 03:42:22 PM UTC 24
Peak memory	281116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781408986 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.2781408986
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.1067766982
Short name	T327
Test name
Test status
Simulation time	316166921656 ps
CPU time	4934.88 seconds
Started	Sep 24 03:32:20 PM UTC 24
Finished	Sep 24 04:55:33 PM UTC 24
Peak memory	318432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067766982 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.1067766982
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.1411711145
Short name	T398
Test name
Test status
Simulation time	731160446771 ps
CPU time	2064.92 seconds
Started	Sep 24 03:47:58 PM UTC 24
Finished	Sep 24 04:22:47 PM UTC 24
Peak memory	296172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411711145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1411711145
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2880727282
Short name	T197
Test name
Test status
Simulation time	11221082648 ps
CPU time	456.22 seconds
Started	Sep 24 02:53:50 PM UTC 24
Finished	Sep 24 03:01:34 PM UTC 24
Peak memory	277616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880727282 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.2880727282
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4079902835
Short name	T416
Test name
Test status
Simulation time	25272551152 ps
CPU time	1452.28 seconds
Started	Sep 24 02:53:57 PM UTC 24
Finished	Sep 24 03:18:30 PM UTC 24
Peak memory	283884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079902835 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shad ow_reg_errors_with_csr_rw.4079902835
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.4164089134
Short name	T123
Test name
Test status
Simulation time	163371610852 ps
CPU time	3110.88 seconds
Started	Sep 24 02:55:44 PM UTC 24
Finished	Sep 24 03:48:15 PM UTC 24
Peak memory	302320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164089134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.4164089134
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.2213769668
Short name	T348
Test name
Test status
Simulation time	28196637140 ps
CPU time	2323.48 seconds
Started	Sep 24 02:55:48 PM UTC 24
Finished	Sep 24 03:35:01 PM UTC 24
Peak memory	297964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213769668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2213769668
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.3412717655
Short name	T364
Test name
Test status
Simulation time	35078196515 ps
CPU time	351.2 seconds
Started	Sep 24 03:38:31 PM UTC 24
Finished	Sep 24 03:44:27 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412717655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3412717655
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all_with_rand_reset.616049101
Short name	T259
Test name
Test status
Simulation time	17638631542 ps
CPU time	401.75 seconds
Started	Sep 24 04:06:19 PM UTC 24
Finished	Sep 24 04:13:07 PM UTC 24
Peak memory	279116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=616049101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.al ert_handler_stress_all_with_rand_reset.616049101
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.3366846288
Short name	T723
Test name
Test status
Simulation time	196606437223 ps
CPU time	2796.18 seconds
Started	Sep 24 04:28:31 PM UTC 24
Finished	Sep 24 05:15:39 PM UTC 24
Peak memory	300004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366846288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3366846288
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.1038290656
Short name	T270
Test name
Test status
Simulation time	41908478968 ps
CPU time	2653.84 seconds
Started	Sep 24 04:06:19 PM UTC 24
Finished	Sep 24 04:51:04 PM UTC 24
Peak memory	302048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038290656 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.1038290656
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.746603576
Short name	T211
Test name
Test status
Simulation time	236138769 ps
CPU time	7.01 seconds
Started	Sep 24 02:52:34 PM UTC 24
Finished	Sep 24 02:52:42 PM UTC 24
Peak memory	248060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746603576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.746603576
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.3086804651
Short name	T27
Test name
Test status
Simulation time	495715302 ps
CPU time	44.71 seconds
Started	Sep 24 02:56:07 PM UTC 24
Finished	Sep 24 02:56:53 PM UTC 24
Peak memory	260508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086804651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3086804651
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.169258731
Short name	T1
Test name
Test status
Simulation time	147278611 ps
CPU time	4.85 seconds
Started	Sep 24 02:55:44 PM UTC 24
Finished	Sep 24 02:55:50 PM UTC 24
Peak memory	260764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169258731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.169258731
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.2746069193
Short name	T232
Test name
Test status
Simulation time	103847335 ps
CPU time	2.51 seconds
Started	Sep 24 03:09:23 PM UTC 24
Finished	Sep 24 03:09:26 PM UTC 24
Peak memory	260708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746069193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2746069193
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.1346939027
Short name	T233
Test name
Test status
Simulation time	156159610 ps
CPU time	5.51 seconds
Started	Sep 24 03:11:19 PM UTC 24
Finished	Sep 24 03:11:26 PM UTC 24
Peak memory	260776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346939027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1346939027
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.1247376936
Short name	T234
Test name
Test status
Simulation time	82209013 ps
CPU time	6.17 seconds
Started	Sep 24 03:14:26 PM UTC 24
Finished	Sep 24 03:14:34 PM UTC 24
Peak memory	260968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247376936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1247376936
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.1216989066
Short name	T751
Test name
Test status
Simulation time	12108989 ps
CPU time	2.15 seconds
Started	Sep 24 02:52:25 PM UTC 24
Finished	Sep 24 02:52:28 PM UTC 24
Peak memory	248344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216989066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1216989066
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.475881840
Short name	T109
Test name
Test status
Simulation time	35848223092 ps
CPU time	2200.36 seconds
Started	Sep 24 02:55:44 PM UTC 24
Finished	Sep 24 03:32:50 PM UTC 24
Peak memory	300268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475881840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.475881840
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.740314673
Short name	T338
Test name
Test status
Simulation time	9831502807 ps
CPU time	544.03 seconds
Started	Sep 24 03:06:02 PM UTC 24
Finished	Sep 24 03:15:13 PM UTC 24
Peak memory	260704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740314673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.740314673
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.294741054
Short name	T377
Test name
Test status
Simulation time	204322484625 ps
CPU time	3230.57 seconds
Started	Sep 24 02:56:29 PM UTC 24
Finished	Sep 24 03:50:55 PM UTC 24
Peak memory	302044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294741054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.294741054
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.999204769
Short name	T310
Test name
Test status
Simulation time	673229054310 ps
CPU time	3389.58 seconds
Started	Sep 24 03:53:36 PM UTC 24
Finished	Sep 24 04:50:46 PM UTC 24
Peak memory	302044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999204769 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.999204769
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.902349973
Short name	T295
Test name
Test status
Simulation time	55602787828 ps
CPU time	1781.8 seconds
Started	Sep 24 04:07:49 PM UTC 24
Finished	Sep 24 04:37:52 PM UTC 24
Peak memory	283100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902349973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.902349973
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.49889785
Short name	T172
Test name
Test status
Simulation time	18437871841 ps
CPU time	145.89 seconds
Started	Sep 24 02:49:27 PM UTC 24
Finished	Sep 24 02:51:57 PM UTC 24
Peak memory	279584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49889785 -assert nopostproc +UVM_TESTNAME=alert_handler_ba se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.49889785
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4289170831
Short name	T187
Test name
Test status
Simulation time	14296623190 ps
CPU time	297.02 seconds
Started	Sep 24 02:54:00 PM UTC 24
Finished	Sep 24 02:59:01 PM UTC 24
Peak memory	277804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289170831 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.4289170831
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.3647644430
Short name	T117
Test name
Test status
Simulation time	6874898615 ps
CPU time	474.93 seconds
Started	Sep 24 03:53:50 PM UTC 24
Finished	Sep 24 04:01:52 PM UTC 24
Peak memory	279120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3647644430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.a lert_handler_stress_all_with_rand_reset.3647644430
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.103710413
Short name	T342
Test name
Test status
Simulation time	11034896243 ps
CPU time	234.7 seconds
Started	Sep 24 03:03:44 PM UTC 24
Finished	Sep 24 03:07:43 PM UTC 24
Peak memory	260564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103710413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.103710413
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all_with_rand_reset.500141321
Short name	T58
Test name
Test status
Simulation time	7099790089 ps
CPU time	574.87 seconds
Started	Sep 24 03:05:03 PM UTC 24
Finished	Sep 24 03:14:46 PM UTC 24
Peak memory	283352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=500141321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.al ert_handler_stress_all_with_rand_reset.500141321
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.2047846370
Short name	T91
Test name
Test status
Simulation time	185084139 ps
CPU time	36.23 seconds
Started	Sep 24 03:05:33 PM UTC 24
Finished	Sep 24 03:06:11 PM UTC 24
Peak memory	266572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047846370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2047846370
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.1914246732
Short name	T365
Test name
Test status
Simulation time	33593956652 ps
CPU time	1431.31 seconds
Started	Sep 24 03:17:58 PM UTC 24
Finished	Sep 24 03:42:07 PM UTC 24
Peak memory	283356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914246732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1914246732
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.2065813915
Short name	T278
Test name
Test status
Simulation time	4785185052 ps
CPU time	53.49 seconds
Started	Sep 24 03:21:41 PM UTC 24
Finished	Sep 24 03:22:37 PM UTC 24
Peak memory	266772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065813915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2065813915
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.4123573290
Short name	T314
Test name
Test status
Simulation time	14312591709 ps
CPU time	94.68 seconds
Started	Sep 24 03:31:09 PM UTC 24
Finished	Sep 24 03:32:46 PM UTC 24
Peak memory	266964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123573290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.4123573290
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all_with_rand_reset.413995121
Short name	T122
Test name
Test status
Simulation time	9368596320 ps
CPU time	268.6 seconds
Started	Sep 24 03:32:47 PM UTC 24
Finished	Sep 24 03:37:19 PM UTC 24
Peak memory	283216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=413995121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.al ert_handler_stress_all_with_rand_reset.413995121
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.1948453007
Short name	T128
Test name
Test status
Simulation time	1972557673 ps
CPU time	47.02 seconds
Started	Sep 24 03:33:23 PM UTC 24
Finished	Sep 24 03:34:12 PM UTC 24
Peak memory	260428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948453007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1948453007
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.2304982430
Short name	T358
Test name
Test status
Simulation time	3052875611 ps
CPU time	120.3 seconds
Started	Sep 24 03:42:10 PM UTC 24
Finished	Sep 24 03:44:13 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304982430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2304982430
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.3893643970
Short name	T355
Test name
Test status
Simulation time	83869593312 ps
CPU time	711.04 seconds
Started	Sep 24 03:55:05 PM UTC 24
Finished	Sep 24 04:07:04 PM UTC 24
Peak memory	260568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893643970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3893643970
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.1506146938
Short name	T292
Test name
Test status
Simulation time	14118200400 ps
CPU time	1648.6 seconds
Started	Sep 24 04:02:05 PM UTC 24
Finished	Sep 24 04:29:54 PM UTC 24
Peak memory	299548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506146938 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.1506146938
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.441949669
Short name	T254
Test name
Test status
Simulation time	3641620155 ps
CPU time	96.25 seconds
Started	Sep 24 04:07:15 PM UTC 24
Finished	Sep 24 04:08:54 PM UTC 24
Peak memory	266744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441949669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.441949669
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.3983692672
Short name	T30
Test name
Test status
Simulation time	5099493692 ps
CPU time	280.13 seconds
Started	Sep 24 03:13:11 PM UTC 24
Finished	Sep 24 03:17:56 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983692672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3983692672
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3797754007
Short name	T181
Test name
Test status
Simulation time	10080978901 ps
CPU time	248.03 seconds
Started	Sep 24 02:51:02 PM UTC 24
Finished	Sep 24 02:55:14 PM UTC 24
Peak memory	277536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797754007 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.3797754007
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3565132507
Short name	T218
Test name
Test status
Simulation time	54609390 ps
CPU time	6.96 seconds
Started	Sep 24 02:52:58 PM UTC 24
Finished	Sep 24 02:53:06 PM UTC 24
Peak memory	250520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565132507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3565132507
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.30132011
Short name	T209
Test name
Test status
Simulation time	209722425 ps
CPU time	13.37 seconds
Started	Sep 24 02:53:38 PM UTC 24
Finished	Sep 24 02:53:53 PM UTC 24
Peak memory	248676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30132011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.30132011
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.852429547
Short name	T213
Test name
Test status
Simulation time	3663289431 ps
CPU time	102.08 seconds
Started	Sep 24 02:52:14 PM UTC 24
Finished	Sep 24 02:53:59 PM UTC 24
Peak memory	258852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852429547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.852429547
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1979452748
Short name	T206
Test name
Test status
Simulation time	42564287 ps
CPU time	6.04 seconds
Started	Sep 24 02:50:44 PM UTC 24
Finished	Sep 24 02:50:51 PM UTC 24
Peak memory	248680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979452748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1979452748
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2497352999
Short name	T205
Test name
Test status
Simulation time	22201131 ps
CPU time	4.12 seconds
Started	Sep 24 02:50:06 PM UTC 24
Finished	Sep 24 02:50:11 PM UTC 24
Peak memory	248556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497352999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2497352999
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.1433876664
Short name	T13
Test name
Test status
Simulation time	1125786868 ps
CPU time	53.51 seconds
Started	Sep 24 02:55:43 PM UTC 24
Finished	Sep 24 02:56:38 PM UTC 24
Peak memory	260464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433876664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1433876664
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1547260429
Short name	T216
Test name
Test status
Simulation time	54328850 ps
CPU time	5.74 seconds
Started	Sep 24 02:52:24 PM UTC 24
Finished	Sep 24 02:52:31 PM UTC 24
Peak memory	248676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547260429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1547260429
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.4060074792
Short name	T215
Test name
Test status
Simulation time	895512402 ps
CPU time	107.27 seconds
Started	Sep 24 02:52:44 PM UTC 24
Finished	Sep 24 02:54:34 PM UTC 24
Peak memory	260836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060074792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.4060074792
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.123530270
Short name	T212
Test name
Test status
Simulation time	52595736 ps
CPU time	4.06 seconds
Started	Sep 24 02:53:17 PM UTC 24
Finished	Sep 24 02:53:22 PM UTC 24
Peak memory	248548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123530270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.123530270
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1898529550
Short name	T220
Test name
Test status
Simulation time	619188725 ps
CPU time	46.49 seconds
Started	Sep 24 02:51:09 PM UTC 24
Finished	Sep 24 02:51:57 PM UTC 24
Peak memory	250792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898529550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1898529550
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1816189063
Short name	T210
Test name
Test status
Simulation time	6590679427 ps
CPU time	56.35 seconds
Started	Sep 24 02:51:58 PM UTC 24
Finished	Sep 24 02:52:56 PM UTC 24
Peak memory	260832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816189063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1816189063
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.364889560
Short name	T204
Test name
Test status
Simulation time	368315721 ps
CPU time	25.5 seconds
Started	Sep 24 02:49:30 PM UTC 24
Finished	Sep 24 02:49:57 PM UTC 24
Peak memory	250524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364889560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.364889560
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1076562995
Short name	T222
Test name
Test status
Simulation time	3689395533 ps
CPU time	75.87 seconds
Started	Sep 24 02:53:51 PM UTC 24
Finished	Sep 24 02:55:09 PM UTC 24
Peak memory	250584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076562995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1076562995
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.187397824
Short name	T217
Test name
Test status
Simulation time	35359005 ps
CPU time	3.76 seconds
Started	Sep 24 02:54:04 PM UTC 24
Finished	Sep 24 02:54:09 PM UTC 24
Peak memory	248472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187397824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.187397824
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.398695602
Short name	T219
Test name
Test status
Simulation time	3722298433 ps
CPU time	78.87 seconds
Started	Sep 24 02:54:19 PM UTC 24
Finished	Sep 24 02:55:40 PM UTC 24
Peak memory	258780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398695602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.398695602
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.4222538315
Short name	T34
Test name
Test status
Simulation time	6196705861 ps
CPU time	81.04 seconds
Started	Sep 24 02:55:41 PM UTC 24
Finished	Sep 24 02:57:04 PM UTC 24
Peak memory	266772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222538315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.4222538315
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.295313980
Short name	T745
Test name
Test status
Simulation time	1119138817 ps
CPU time	158.02 seconds
Started	Sep 24 02:49:38 PM UTC 24
Finished	Sep 24 02:52:19 PM UTC 24
Peak memory	250728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295313980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.295313980
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3275047297
Short name	T811
Test name
Test status
Simulation time	14271745460 ps
CPU time	298.32 seconds
Started	Sep 24 02:49:38 PM UTC 24
Finished	Sep 24 02:54:41 PM UTC 24
Peak memory	248540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275047297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3275047297
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3827502739
Short name	T154
Test name
Test status
Simulation time	294996764 ps
CPU time	5.02 seconds
Started	Sep 24 02:49:34 PM UTC 24
Finished	Sep 24 02:49:40 PM UTC 24
Peak memory	250528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827502739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3827502739
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4071186360
Short name	T223
Test name
Test status
Simulation time	99220495 ps
CPU time	11.96 seconds
Started	Sep 24 02:49:43 PM UTC 24
Finished	Sep 24 02:49:56 PM UTC 24
Peak memory	250788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071186360 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_ rw_with_rand_reset.4071186360
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.4029983107
Short name	T207
Test name
Test status
Simulation time	15438908 ps
CPU time	2.13 seconds
Started	Sep 24 02:49:30 PM UTC 24
Finished	Sep 24 02:49:34 PM UTC 24
Peak memory	248488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029983107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.4029983107
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3332137232
Short name	T164
Test name
Test status
Simulation time	96287999 ps
CPU time	20.18 seconds
Started	Sep 24 02:49:41 PM UTC 24
Finished	Sep 24 02:50:03 PM UTC 24
Peak memory	260764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332137232 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.3332137232
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.1501732690
Short name	T727
Test name
Test status
Simulation time	50405160 ps
CPU time	10.32 seconds
Started	Sep 24 02:49:30 PM UTC 24
Finished	Sep 24 02:49:42 PM UTC 24
Peak memory	265200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501732690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1501732690
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1308158418
Short name	T835
Test name
Test status
Simulation time	4255965974 ps
CPU time	288.61 seconds
Started	Sep 24 02:50:01 PM UTC 24
Finished	Sep 24 02:54:54 PM UTC 24
Peak memory	250588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308158418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1308158418
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1509014326
Short name	T782
Test name
Test status
Simulation time	11428718759 ps
CPU time	221.33 seconds
Started	Sep 24 02:50:00 PM UTC 24
Finished	Sep 24 02:53:45 PM UTC 24
Peak memory	248544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509014326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1509014326
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3054556176
Short name	T155
Test name
Test status
Simulation time	274141424 ps
CPU time	6.65 seconds
Started	Sep 24 02:49:57 PM UTC 24
Finished	Sep 24 02:50:05 PM UTC 24
Peak memory	260764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054556176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3054556176
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1986874615
Short name	T407
Test name
Test status
Simulation time	37805244 ps
CPU time	8.71 seconds
Started	Sep 24 02:50:02 PM UTC 24
Finished	Sep 24 02:50:12 PM UTC 24
Peak memory	264924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986874615 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_ rw_with_rand_reset.1986874615
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.3068641893
Short name	T169
Test name
Test status
Simulation time	20493806 ps
CPU time	5.49 seconds
Started	Sep 24 02:49:58 PM UTC 24
Finished	Sep 24 02:50:05 PM UTC 24
Peak memory	250520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068641893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3068641893
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.1143446166
Short name	T208
Test name
Test status
Simulation time	42780029 ps
CPU time	2.33 seconds
Started	Sep 24 02:49:57 PM UTC 24
Finished	Sep 24 02:50:01 PM UTC 24
Peak memory	248496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143446166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1143446166
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1987039849
Short name	T180
Test name
Test status
Simulation time	2087031601 ps
CPU time	292.99 seconds
Started	Sep 24 02:49:43 PM UTC 24
Finished	Sep 24 02:54:40 PM UTC 24
Peak memory	277676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987039849 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shado w_reg_errors_with_csr_rw.1987039849
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.588641818
Short name	T728
Test name
Test status
Simulation time	376722926 ps
CPU time	14.72 seconds
Started	Sep 24 02:49:52 PM UTC 24
Finished	Sep 24 02:50:08 PM UTC 24
Peak memory	265120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588641818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.588641818
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.804547534
Short name	T752
Test name
Test status
Simulation time	110344757 ps
CPU time	8.67 seconds
Started	Sep 24 02:52:19 PM UTC 24
Finished	Sep 24 02:52:29 PM UTC 24
Peak memory	261028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804547534 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem_ rw_with_rand_reset.804547534
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.2827880821
Short name	T747
Test name
Test status
Simulation time	112772413 ps
CPU time	4.81 seconds
Started	Sep 24 02:52:16 PM UTC 24
Finished	Sep 24 02:52:22 PM UTC 24
Peak memory	248476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827880821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2827880821
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.977159940
Short name	T763
Test name
Test status
Simulation time	563736682 ps
CPU time	30.02 seconds
Started	Sep 24 02:52:18 PM UTC 24
Finished	Sep 24 02:52:50 PM UTC 24
Peak memory	258712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977159940 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.977159940
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.989710052
Short name	T190
Test name
Test status
Simulation time	10770693711 ps
CPU time	414.49 seconds
Started	Sep 24 02:52:07 PM UTC 24
Finished	Sep 24 02:59:07 PM UTC 24
Peak memory	277552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989710052 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.989710052
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3593476038
Short name	T201
Test name
Test status
Simulation time	50319054750 ps
CPU time	1054.68 seconds
Started	Sep 24 02:52:05 PM UTC 24
Finished	Sep 24 03:09:54 PM UTC 24
Peak memory	277540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593476038 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad ow_reg_errors_with_csr_rw.3593476038
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.1789974400
Short name	T750
Test name
Test status
Simulation time	302633288 ps
CPU time	12.08 seconds
Started	Sep 24 02:52:11 PM UTC 24
Finished	Sep 24 02:52:24 PM UTC 24
Peak memory	264936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789974400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1789974400
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1065150786
Short name	T760
Test name
Test status
Simulation time	63578228 ps
CPU time	12.43 seconds
Started	Sep 24 02:52:30 PM UTC 24
Finished	Sep 24 02:52:44 PM UTC 24
Peak memory	267044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065150786 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem _rw_with_rand_reset.1065150786
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.3052297771
Short name	T757
Test name
Test status
Simulation time	69904125 ps
CPU time	6.95 seconds
Started	Sep 24 02:52:25 PM UTC 24
Finished	Sep 24 02:52:33 PM UTC 24
Peak memory	248620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052297771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3052297771
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4116216919
Short name	T777
Test name
Test status
Simulation time	840411597 ps
CPU time	64.97 seconds
Started	Sep 24 02:52:29 PM UTC 24
Finished	Sep 24 02:53:36 PM UTC 24
Peak memory	258788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116216919 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.4116216919
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1827934522
Short name	T415
Test name
Test status
Simulation time	66003865898 ps
CPU time	1164.74 seconds
Started	Sep 24 02:52:21 PM UTC 24
Finished	Sep 24 03:11:58 PM UTC 24
Peak memory	277540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827934522 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shad ow_reg_errors_with_csr_rw.1827934522
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.667842390
Short name	T754
Test name
Test status
Simulation time	46541336 ps
CPU time	8.67 seconds
Started	Sep 24 02:52:23 PM UTC 24
Finished	Sep 24 02:52:33 PM UTC 24
Peak memory	261040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667842390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.667842390
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2765010199
Short name	T761
Test name
Test status
Simulation time	77572678 ps
CPU time	8.68 seconds
Started	Sep 24 02:52:37 PM UTC 24
Finished	Sep 24 02:52:47 PM UTC 24
Peak memory	250660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765010199 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem _rw_with_rand_reset.2765010199
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.2491954303
Short name	T759
Test name
Test status
Simulation time	35652889 ps
CPU time	8.29 seconds
Started	Sep 24 02:52:34 PM UTC 24
Finished	Sep 24 02:52:43 PM UTC 24
Peak memory	248672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491954303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2491954303
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.1254682478
Short name	T758
Test name
Test status
Simulation time	10992088 ps
CPU time	2.09 seconds
Started	Sep 24 02:52:34 PM UTC 24
Finished	Sep 24 02:52:37 PM UTC 24
Peak memory	248096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254682478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1254682478
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3167296692
Short name	T765
Test name
Test status
Simulation time	93123741 ps
CPU time	19.34 seconds
Started	Sep 24 02:52:36 PM UTC 24
Finished	Sep 24 02:52:57 PM UTC 24
Peak memory	258916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167296692 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.3167296692
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2487999130
Short name	T410
Test name
Test status
Simulation time	19091764211 ps
CPU time	797.25 seconds
Started	Sep 24 02:52:31 PM UTC 24
Finished	Sep 24 03:06:00 PM UTC 24
Peak memory	277540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487999130 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad ow_reg_errors_with_csr_rw.2487999130
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.143133582
Short name	T766
Test name
Test status
Simulation time	1267211013 ps
CPU time	31.16 seconds
Started	Sep 24 02:52:32 PM UTC 24
Finished	Sep 24 02:53:05 PM UTC 24
Peak memory	260836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143133582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.143133582
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3965011670
Short name	T768
Test name
Test status
Simulation time	258621554 ps
CPU time	15.27 seconds
Started	Sep 24 02:52:51 PM UTC 24
Finished	Sep 24 02:53:07 PM UTC 24
Peak memory	267044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965011670 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem _rw_with_rand_reset.3965011670
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.426012622
Short name	T764
Test name
Test status
Simulation time	181395334 ps
CPU time	6.95 seconds
Started	Sep 24 02:52:47 PM UTC 24
Finished	Sep 24 02:52:56 PM UTC 24
Peak memory	250596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426012622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.426012622
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.4017866888
Short name	T762
Test name
Test status
Simulation time	13896137 ps
CPU time	2.37 seconds
Started	Sep 24 02:52:45 PM UTC 24
Finished	Sep 24 02:52:49 PM UTC 24
Peak memory	248424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017866888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.4017866888
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3962576122
Short name	T779
Test name
Test status
Simulation time	1079848857 ps
CPU time	48.39 seconds
Started	Sep 24 02:52:50 PM UTC 24
Finished	Sep 24 02:53:40 PM UTC 24
Peak memory	258720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962576122 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.3962576122
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3399301412
Short name	T183
Test name
Test status
Simulation time	5654909402 ps
CPU time	190.2 seconds
Started	Sep 24 02:52:41 PM UTC 24
Finished	Sep 24 02:55:55 PM UTC 24
Peak memory	277540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399301412 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.3399301412
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1562222947
Short name	T417
Test name
Test status
Simulation time	32922926215 ps
CPU time	1498.46 seconds
Started	Sep 24 02:52:39 PM UTC 24
Finished	Sep 24 03:17:55 PM UTC 24
Peak memory	277536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562222947 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shad ow_reg_errors_with_csr_rw.1562222947
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.3936594440
Short name	T767
Test name
Test status
Simulation time	243227121 ps
CPU time	22.81 seconds
Started	Sep 24 02:52:42 PM UTC 24
Finished	Sep 24 02:53:06 PM UTC 24
Peak memory	260840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936594440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3936594440
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.111952658
Short name	T772
Test name
Test status
Simulation time	337018722 ps
CPU time	9.73 seconds
Started	Sep 24 02:53:08 PM UTC 24
Finished	Sep 24 02:53:18 PM UTC 24
Peak memory	250660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111952658 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem_ rw_with_rand_reset.111952658
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.1580827534
Short name	T771
Test name
Test status
Simulation time	64661115 ps
CPU time	8.53 seconds
Started	Sep 24 02:53:06 PM UTC 24
Finished	Sep 24 02:53:16 PM UTC 24
Peak memory	248544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580827534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1580827534
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.4279883057
Short name	T769
Test name
Test status
Simulation time	14374550 ps
CPU time	2.15 seconds
Started	Sep 24 02:53:05 PM UTC 24
Finished	Sep 24 02:53:09 PM UTC 24
Peak memory	248424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279883057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4279883057
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1100682866
Short name	T781
Test name
Test status
Simulation time	164137857 ps
CPU time	34.92 seconds
Started	Sep 24 02:53:06 PM UTC 24
Finished	Sep 24 02:53:43 PM UTC 24
Peak memory	260836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100682866 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.1100682866
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3018597249
Short name	T191
Test name
Test status
Simulation time	9278913604 ps
CPU time	200.38 seconds
Started	Sep 24 02:52:56 PM UTC 24
Finished	Sep 24 02:56:20 PM UTC 24
Peak memory	277536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018597249 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.3018597249
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3813291327
Short name	T413
Test name
Test status
Simulation time	21137248262 ps
CPU time	609.99 seconds
Started	Sep 24 02:52:55 PM UTC 24
Finished	Sep 24 03:03:14 PM UTC 24
Peak memory	277740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813291327 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shad ow_reg_errors_with_csr_rw.3813291327
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.1781890534
Short name	T770
Test name
Test status
Simulation time	56065043 ps
CPU time	12.54 seconds
Started	Sep 24 02:52:57 PM UTC 24
Finished	Sep 24 02:53:10 PM UTC 24
Peak memory	266984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781890534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1781890534
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2687716516
Short name	T778
Test name
Test status
Simulation time	71083704 ps
CPU time	8.76 seconds
Started	Sep 24 02:53:26 PM UTC 24
Finished	Sep 24 02:53:36 PM UTC 24
Peak memory	267044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687716516 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem _rw_with_rand_reset.2687716516
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.939658544
Short name	T775
Test name
Test status
Simulation time	221713923 ps
CPU time	6.82 seconds
Started	Sep 24 02:53:23 PM UTC 24
Finished	Sep 24 02:53:31 PM UTC 24
Peak memory	248548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939658544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.939658544
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.2887830406
Short name	T773
Test name
Test status
Simulation time	30849502 ps
CPU time	3.67 seconds
Started	Sep 24 02:53:19 PM UTC 24
Finished	Sep 24 02:53:24 PM UTC 24
Peak memory	248688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887830406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2887830406
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4103391111
Short name	T786
Test name
Test status
Simulation time	955787559 ps
CPU time	26.9 seconds
Started	Sep 24 02:53:25 PM UTC 24
Finished	Sep 24 02:53:53 PM UTC 24
Peak memory	250724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103391111 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.4103391111
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1707099226
Short name	T188
Test name
Test status
Simulation time	6246251303 ps
CPU time	225.41 seconds
Started	Sep 24 02:53:10 PM UTC 24
Finished	Sep 24 02:56:59 PM UTC 24
Peak memory	277536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707099226 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.1707099226
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.553498822
Short name	T203
Test name
Test status
Simulation time	13133905746 ps
CPU time	397.28 seconds
Started	Sep 24 02:53:08 PM UTC 24
Finished	Sep 24 02:59:51 PM UTC 24
Peak memory	281708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553498822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shado w_reg_errors_with_csr_rw.553498822
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.464915500
Short name	T776
Test name
Test status
Simulation time	602193244 ps
CPU time	23.76 seconds
Started	Sep 24 02:53:11 PM UTC 24
Finished	Sep 24 02:53:36 PM UTC 24
Peak memory	260836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464915500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.464915500
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3342660038
Short name	T785
Test name
Test status
Simulation time	114933830 ps
CPU time	6.96 seconds
Started	Sep 24 02:53:43 PM UTC 24
Finished	Sep 24 02:53:51 PM UTC 24
Peak memory	250588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342660038 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem _rw_with_rand_reset.3342660038
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.1457004441
Short name	T783
Test name
Test status
Simulation time	35755720 ps
CPU time	8.74 seconds
Started	Sep 24 02:53:40 PM UTC 24
Finished	Sep 24 02:53:50 PM UTC 24
Peak memory	248476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457004441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1457004441
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.1272071364
Short name	T780
Test name
Test status
Simulation time	6781595 ps
CPU time	1.66 seconds
Started	Sep 24 02:53:38 PM UTC 24
Finished	Sep 24 02:53:41 PM UTC 24
Peak memory	246864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272071364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1272071364
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1333523548
Short name	T795
Test name
Test status
Simulation time	8103678983 ps
CPU time	38.97 seconds
Started	Sep 24 02:53:42 PM UTC 24
Finished	Sep 24 02:54:23 PM UTC 24
Peak memory	258780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333523548 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.1333523548
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4177591203
Short name	T192
Test name
Test status
Simulation time	3384037124 ps
CPU time	129.31 seconds
Started	Sep 24 02:53:36 PM UTC 24
Finished	Sep 24 02:55:49 PM UTC 24
Peak memory	277608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177591203 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.4177591203
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.3446767614
Short name	T784
Test name
Test status
Simulation time	207572901 ps
CPU time	11.3 seconds
Started	Sep 24 02:53:38 PM UTC 24
Finished	Sep 24 02:53:51 PM UTC 24
Peak memory	267188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446767614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3446767614
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2500259575
Short name	T792
Test name
Test status
Simulation time	292526523 ps
CPU time	19.41 seconds
Started	Sep 24 02:53:56 PM UTC 24
Finished	Sep 24 02:54:17 PM UTC 24
Peak memory	262876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500259575 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem _rw_with_rand_reset.2500259575
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.339740066
Short name	T788
Test name
Test status
Simulation time	93320429 ps
CPU time	7.07 seconds
Started	Sep 24 02:53:53 PM UTC 24
Finished	Sep 24 02:54:01 PM UTC 24
Peak memory	248552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339740066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.339740066
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.261791753
Short name	T787
Test name
Test status
Simulation time	30105596 ps
CPU time	2.34 seconds
Started	Sep 24 02:53:52 PM UTC 24
Finished	Sep 24 02:53:55 PM UTC 24
Peak memory	248496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261791753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.261791753
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.990974858
Short name	T794
Test name
Test status
Simulation time	1454327810 ps
CPU time	24.89 seconds
Started	Sep 24 02:53:54 PM UTC 24
Finished	Sep 24 02:54:20 PM UTC 24
Peak memory	258788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990974858 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.990974858
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2136542133
Short name	T200
Test name
Test status
Simulation time	4398607164 ps
CPU time	409.23 seconds
Started	Sep 24 02:53:45 PM UTC 24
Finished	Sep 24 03:00:41 PM UTC 24
Peak memory	279660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136542133 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad ow_reg_errors_with_csr_rw.2136542133
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.3552955254
Short name	T789
Test name
Test status
Simulation time	218199187 ps
CPU time	10.59 seconds
Started	Sep 24 02:53:51 PM UTC 24
Finished	Sep 24 02:54:03 PM UTC 24
Peak memory	260840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552955254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3552955254
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1935706326
Short name	T797
Test name
Test status
Simulation time	127826201 ps
CPU time	10.48 seconds
Started	Sep 24 02:54:14 PM UTC 24
Finished	Sep 24 02:54:25 PM UTC 24
Peak memory	260900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935706326 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem _rw_with_rand_reset.1935706326
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.470257593
Short name	T793
Test name
Test status
Simulation time	51527539 ps
CPU time	5.24 seconds
Started	Sep 24 02:54:12 PM UTC 24
Finished	Sep 24 02:54:18 PM UTC 24
Peak memory	250520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470257593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.470257593
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.2508945323
Short name	T791
Test name
Test status
Simulation time	16113423 ps
CPU time	2.22 seconds
Started	Sep 24 02:54:10 PM UTC 24
Finished	Sep 24 02:54:13 PM UTC 24
Peak memory	246448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508945323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2508945323
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1108117927
Short name	T799
Test name
Test status
Simulation time	336140379 ps
CPU time	15.53 seconds
Started	Sep 24 02:54:14 PM UTC 24
Finished	Sep 24 02:54:30 PM UTC 24
Peak memory	260764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108117927 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.1108117927
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.3837050501
Short name	T790
Test name
Test status
Simulation time	102550389 ps
CPU time	7.54 seconds
Started	Sep 24 02:54:03 PM UTC 24
Finished	Sep 24 02:54:11 PM UTC 24
Peak memory	261040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837050501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3837050501
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.18149712
Short name	T809
Test name
Test status
Simulation time	135999017 ps
CPU time	12.73 seconds
Started	Sep 24 02:54:26 PM UTC 24
Finished	Sep 24 02:54:40 PM UTC 24
Peak memory	250592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18149712 -assert nop ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem_r w_with_rand_reset.18149712
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.1736784697
Short name	T798
Test name
Test status
Simulation time	36855268 ps
CPU time	6.06 seconds
Started	Sep 24 02:54:23 PM UTC 24
Finished	Sep 24 02:54:30 PM UTC 24
Peak memory	248472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736784697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1736784697
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.3188206212
Short name	T796
Test name
Test status
Simulation time	14691683 ps
CPU time	2.8 seconds
Started	Sep 24 02:54:21 PM UTC 24
Finished	Sep 24 02:54:25 PM UTC 24
Peak memory	248428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188206212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3188206212
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2232366854
Short name	T814
Test name
Test status
Simulation time	164770049 ps
CPU time	16.06 seconds
Started	Sep 24 02:54:26 PM UTC 24
Finished	Sep 24 02:54:44 PM UTC 24
Peak memory	258916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232366854 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.2232366854
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3314803609
Short name	T186
Test name
Test status
Simulation time	1993755205 ps
CPU time	149.7 seconds
Started	Sep 24 02:54:19 PM UTC 24
Finished	Sep 24 02:56:51 PM UTC 24
Peak memory	267236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314803609 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.3314803609
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4033820174
Short name	T198
Test name
Test status
Simulation time	16940380955 ps
CPU time	636.44 seconds
Started	Sep 24 02:54:17 PM UTC 24
Finished	Sep 24 03:05:02 PM UTC 24
Peak memory	277540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033820174 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad ow_reg_errors_with_csr_rw.4033820174
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.6000332
Short name	T808
Test name
Test status
Simulation time	295678287 ps
CPU time	19.68 seconds
Started	Sep 24 02:54:19 PM UTC 24
Finished	Sep 24 02:54:40 PM UTC 24
Peak memory	267172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6000332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_S EQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.6000332
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3822332462
Short name	T774
Test name
Test status
Simulation time	2107366980 ps
CPU time	188.98 seconds
Started	Sep 24 02:50:12 PM UTC 24
Finished	Sep 24 02:53:25 PM UTC 24
Peak memory	250792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822332462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3822332462
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3389784954
Short name	T837
Test name
Test status
Simulation time	8803211502 ps
CPU time	531.13 seconds
Started	Sep 24 02:50:10 PM UTC 24
Finished	Sep 24 02:59:08 PM UTC 24
Peak memory	250664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389784954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3389784954
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.582165090
Short name	T156
Test name
Test status
Simulation time	138909180 ps
CPU time	15.87 seconds
Started	Sep 24 02:50:07 PM UTC 24
Finished	Sep 24 02:50:24 PM UTC 24
Peak memory	250528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582165090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.582165090
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1820591222
Short name	T406
Test name
Test status
Simulation time	194106407 ps
CPU time	7.26 seconds
Started	Sep 24 02:50:18 PM UTC 24
Finished	Sep 24 02:50:26 PM UTC 24
Peak memory	250788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820591222 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_ rw_with_rand_reset.1820591222
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1297600367
Short name	T158
Test name
Test status
Simulation time	575805164 ps
CPU time	24.4 seconds
Started	Sep 24 02:50:13 PM UTC 24
Finished	Sep 24 02:50:39 PM UTC 24
Peak memory	258916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297600367 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.1297600367
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2104299651
Short name	T173
Test name
Test status
Simulation time	1578002357 ps
CPU time	228.97 seconds
Started	Sep 24 02:50:04 PM UTC 24
Finished	Sep 24 02:53:57 PM UTC 24
Peak memory	277472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104299651 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.2104299651
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3992109214
Short name	T194
Test name
Test status
Simulation time	47170527438 ps
CPU time	491.63 seconds
Started	Sep 24 02:50:02 PM UTC 24
Finished	Sep 24 02:58:21 PM UTC 24
Peak memory	277540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992109214 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shado w_reg_errors_with_csr_rw.3992109214
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.1254161145
Short name	T729
Test name
Test status
Simulation time	1133201278 ps
CPU time	15.61 seconds
Started	Sep 24 02:50:04 PM UTC 24
Finished	Sep 24 02:50:21 PM UTC 24
Peak memory	260840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254161145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1254161145
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.3523133840
Short name	T802
Test name
Test status
Simulation time	17349923 ps
CPU time	2.8 seconds
Started	Sep 24 02:54:31 PM UTC 24
Finished	Sep 24 02:54:35 PM UTC 24
Peak memory	248420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523133840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3523133840
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.135152219
Short name	T801
Test name
Test status
Simulation time	21190689 ps
CPU time	2.28 seconds
Started	Sep 24 02:54:32 PM UTC 24
Finished	Sep 24 02:54:35 PM UTC 24
Peak memory	248420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135152219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.135152219
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.2499162071
Short name	T803
Test name
Test status
Simulation time	16087109 ps
CPU time	1.51 seconds
Started	Sep 24 02:54:34 PM UTC 24
Finished	Sep 24 02:54:36 PM UTC 24
Peak memory	246864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499162071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2499162071
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1876043824
Short name	T804
Test name
Test status
Simulation time	8583620 ps
CPU time	2.25 seconds
Started	Sep 24 02:54:35 PM UTC 24
Finished	Sep 24 02:54:38 PM UTC 24
Peak memory	248624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876043824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1876043824
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2738727825
Short name	T807
Test name
Test status
Simulation time	15652926 ps
CPU time	2.61 seconds
Started	Sep 24 02:54:36 PM UTC 24
Finished	Sep 24 02:54:40 PM UTC 24
Peak memory	248500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738727825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2738727825
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.2235632203
Short name	T805
Test name
Test status
Simulation time	25467696 ps
CPU time	1.74 seconds
Started	Sep 24 02:54:36 PM UTC 24
Finished	Sep 24 02:54:39 PM UTC 24
Peak memory	246864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235632203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2235632203
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.2474974622
Short name	T806
Test name
Test status
Simulation time	58977850 ps
CPU time	2.16 seconds
Started	Sep 24 02:54:36 PM UTC 24
Finished	Sep 24 02:54:39 PM UTC 24
Peak memory	248424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474974622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2474974622
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.1321141520
Short name	T810
Test name
Test status
Simulation time	7889619 ps
CPU time	2.18 seconds
Started	Sep 24 02:54:37 PM UTC 24
Finished	Sep 24 02:54:40 PM UTC 24
Peak memory	248624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321141520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1321141520
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2950969750
Short name	T812
Test name
Test status
Simulation time	9309370 ps
CPU time	1.74 seconds
Started	Sep 24 02:54:39 PM UTC 24
Finished	Sep 24 02:54:42 PM UTC 24
Peak memory	246796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950969750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2950969750
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.856180734
Short name	T813
Test name
Test status
Simulation time	32655430 ps
CPU time	2.04 seconds
Started	Sep 24 02:54:39 PM UTC 24
Finished	Sep 24 02:54:42 PM UTC 24
Peak memory	248624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856180734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.856180734
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2269101000
Short name	T749
Test name
Test status
Simulation time	546531922 ps
CPU time	103.72 seconds
Started	Sep 24 02:50:38 PM UTC 24
Finished	Sep 24 02:52:24 PM UTC 24
Peak memory	250528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269101000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2269101000
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3403945877
Short name	T836
Test name
Test status
Simulation time	19405412290 ps
CPU time	278.6 seconds
Started	Sep 24 02:50:30 PM UTC 24
Finished	Sep 24 02:55:14 PM UTC 24
Peak memory	248540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403945877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3403945877
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.805274044
Short name	T171
Test name
Test status
Simulation time	222964425 ps
CPU time	8.56 seconds
Started	Sep 24 02:50:27 PM UTC 24
Finished	Sep 24 02:50:37 PM UTC 24
Peak memory	261036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805274044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.805274044
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.4082447329
Short name	T409
Test name
Test status
Simulation time	171845469 ps
CPU time	9.41 seconds
Started	Sep 24 02:50:40 PM UTC 24
Finished	Sep 24 02:50:50 PM UTC 24
Peak memory	252836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082447329 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_ rw_with_rand_reset.4082447329
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.2300543326
Short name	T170
Test name
Test status
Simulation time	64150548 ps
CPU time	5.9 seconds
Started	Sep 24 02:50:29 PM UTC 24
Finished	Sep 24 02:50:37 PM UTC 24
Peak memory	248672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300543326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2300543326
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.4213324337
Short name	T399
Test name
Test status
Simulation time	8896221 ps
CPU time	2.6 seconds
Started	Sep 24 02:50:25 PM UTC 24
Finished	Sep 24 02:50:29 PM UTC 24
Peak memory	248496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213324337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.4213324337
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2939038751
Short name	T163
Test name
Test status
Simulation time	1005147360 ps
CPU time	59.39 seconds
Started	Sep 24 02:50:38 PM UTC 24
Finished	Sep 24 02:51:39 PM UTC 24
Peak memory	260836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939038751 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.2939038751
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.882166859
Short name	T182
Test name
Test status
Simulation time	26440398370 ps
CPU time	313.73 seconds
Started	Sep 24 02:50:22 PM UTC 24
Finished	Sep 24 02:55:40 PM UTC 24
Peak memory	277548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882166859 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.882166859
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.2946039190
Short name	T730
Test name
Test status
Simulation time	246081936 ps
CPU time	18.11 seconds
Started	Sep 24 02:50:22 PM UTC 24
Finished	Sep 24 02:50:41 PM UTC 24
Peak memory	260840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946039190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2946039190
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3987779316
Short name	T221
Test name
Test status
Simulation time	2728769597 ps
CPU time	57.4 seconds
Started	Sep 24 02:50:23 PM UTC 24
Finished	Sep 24 02:51:22 PM UTC 24
Peak memory	261096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987779316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3987779316
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.3480116323
Short name	T817
Test name
Test status
Simulation time	16836118 ps
CPU time	2.06 seconds
Started	Sep 24 02:54:41 PM UTC 24
Finished	Sep 24 02:54:44 PM UTC 24
Peak memory	246576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480116323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3480116323
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2913953597
Short name	T821
Test name
Test status
Simulation time	28682206 ps
CPU time	2.51 seconds
Started	Sep 24 02:54:41 PM UTC 24
Finished	Sep 24 02:54:44 PM UTC 24
Peak memory	248496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913953597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2913953597
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1209401479
Short name	T816
Test name
Test status
Simulation time	8829336 ps
CPU time	1.93 seconds
Started	Sep 24 02:54:41 PM UTC 24
Finished	Sep 24 02:54:44 PM UTC 24
Peak memory	246796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209401479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1209401479
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.385793331
Short name	T815
Test name
Test status
Simulation time	20781390 ps
CPU time	1.91 seconds
Started	Sep 24 02:54:41 PM UTC 24
Finished	Sep 24 02:54:44 PM UTC 24
Peak memory	246856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385793331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.385793331
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.4209570289
Short name	T819
Test name
Test status
Simulation time	20017359 ps
CPU time	2.15 seconds
Started	Sep 24 02:54:41 PM UTC 24
Finished	Sep 24 02:54:44 PM UTC 24
Peak memory	248420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209570289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.4209570289
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.2184882818
Short name	T818
Test name
Test status
Simulation time	6499429 ps
CPU time	1.83 seconds
Started	Sep 24 02:54:41 PM UTC 24
Finished	Sep 24 02:54:44 PM UTC 24
Peak memory	246796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184882818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2184882818
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1665862547
Short name	T820
Test name
Test status
Simulation time	25270281 ps
CPU time	2.08 seconds
Started	Sep 24 02:54:41 PM UTC 24
Finished	Sep 24 02:54:44 PM UTC 24
Peak memory	246376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665862547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1665862547
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.3777065121
Short name	T822
Test name
Test status
Simulation time	10767444 ps
CPU time	1.38 seconds
Started	Sep 24 02:54:42 PM UTC 24
Finished	Sep 24 02:54:45 PM UTC 24
Peak memory	246864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777065121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3777065121
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.1002827306
Short name	T825
Test name
Test status
Simulation time	7358721 ps
CPU time	2.42 seconds
Started	Sep 24 02:54:43 PM UTC 24
Finished	Sep 24 02:54:47 PM UTC 24
Peak memory	248172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002827306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1002827306
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.2222416313
Short name	T823
Test name
Test status
Simulation time	47608422 ps
CPU time	2.12 seconds
Started	Sep 24 02:54:43 PM UTC 24
Finished	Sep 24 02:54:47 PM UTC 24
Peak memory	248420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222416313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2222416313
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3147923998
Short name	T748
Test name
Test status
Simulation time	1108554431 ps
CPU time	88.55 seconds
Started	Sep 24 02:50:53 PM UTC 24
Finished	Sep 24 02:52:23 PM UTC 24
Peak memory	248680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147923998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3147923998
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2850617084
Short name	T800
Test name
Test status
Simulation time	5823294518 ps
CPU time	216.63 seconds
Started	Sep 24 02:50:53 PM UTC 24
Finished	Sep 24 02:54:33 PM UTC 24
Peak memory	248744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850617084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2850617084
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.4102026857
Short name	T159
Test name
Test status
Simulation time	460386683 ps
CPU time	11.31 seconds
Started	Sep 24 02:50:50 PM UTC 24
Finished	Sep 24 02:51:02 PM UTC 24
Peak memory	260840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102026857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.4102026857
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.125094407
Short name	T408
Test name
Test status
Simulation time	65587962 ps
CPU time	15.32 seconds
Started	Sep 24 02:50:55 PM UTC 24
Finished	Sep 24 02:51:12 PM UTC 24
Peak memory	267172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125094407 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_r w_with_rand_reset.125094407
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.3820546012
Short name	T160
Test name
Test status
Simulation time	43455948 ps
CPU time	9.98 seconds
Started	Sep 24 02:50:52 PM UTC 24
Finished	Sep 24 02:51:03 PM UTC 24
Peak memory	250784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820546012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3820546012
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.2414427249
Short name	T400
Test name
Test status
Simulation time	7614701 ps
CPU time	1.68 seconds
Started	Sep 24 02:50:46 PM UTC 24
Finished	Sep 24 02:50:49 PM UTC 24
Peak memory	246796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414427249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2414427249
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2736305651
Short name	T736
Test name
Test status
Simulation time	2247517459 ps
CPU time	61.36 seconds
Started	Sep 24 02:50:54 PM UTC 24
Finished	Sep 24 02:51:57 PM UTC 24
Peak memory	260824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736305651 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.2736305651
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.2064860315
Short name	T268
Test name
Test status
Simulation time	2423587160 ps
CPU time	36.66 seconds
Started	Sep 24 02:50:43 PM UTC 24
Finished	Sep 24 02:51:21 PM UTC 24
Peak memory	260904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064860315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2064860315
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.3195233535
Short name	T824
Test name
Test status
Simulation time	11110255 ps
CPU time	2.09 seconds
Started	Sep 24 02:54:44 PM UTC 24
Finished	Sep 24 02:54:47 PM UTC 24
Peak memory	248624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195233535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3195233535
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.753057288
Short name	T827
Test name
Test status
Simulation time	11417951 ps
CPU time	2.02 seconds
Started	Sep 24 02:54:45 PM UTC 24
Finished	Sep 24 02:54:48 PM UTC 24
Peak memory	248496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753057288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.753057288
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2649690912
Short name	T826
Test name
Test status
Simulation time	9410839 ps
CPU time	1.64 seconds
Started	Sep 24 02:54:45 PM UTC 24
Finished	Sep 24 02:54:47 PM UTC 24
Peak memory	246864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649690912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2649690912
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.2495577354
Short name	T828
Test name
Test status
Simulation time	7932793 ps
CPU time	2.06 seconds
Started	Sep 24 02:54:45 PM UTC 24
Finished	Sep 24 02:54:48 PM UTC 24
Peak memory	248500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495577354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2495577354
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.3006378498
Short name	T831
Test name
Test status
Simulation time	9892198 ps
CPU time	2.53 seconds
Started	Sep 24 02:54:45 PM UTC 24
Finished	Sep 24 02:54:48 PM UTC 24
Peak memory	248624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006378498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3006378498
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2899310911
Short name	T829
Test name
Test status
Simulation time	16648945 ps
CPU time	2.26 seconds
Started	Sep 24 02:54:45 PM UTC 24
Finished	Sep 24 02:54:48 PM UTC 24
Peak memory	248424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899310911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2899310911
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.4241602970
Short name	T830
Test name
Test status
Simulation time	25121999 ps
CPU time	2.41 seconds
Started	Sep 24 02:54:45 PM UTC 24
Finished	Sep 24 02:54:48 PM UTC 24
Peak memory	248496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241602970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4241602970
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.1272151667
Short name	T834
Test name
Test status
Simulation time	6752881 ps
CPU time	2.24 seconds
Started	Sep 24 02:54:46 PM UTC 24
Finished	Sep 24 02:54:49 PM UTC 24
Peak memory	248688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272151667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1272151667
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.3875321180
Short name	T832
Test name
Test status
Simulation time	9801386 ps
CPU time	1.63 seconds
Started	Sep 24 02:54:46 PM UTC 24
Finished	Sep 24 02:54:49 PM UTC 24
Peak memory	246796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875321180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3875321180
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.1955086977
Short name	T833
Test name
Test status
Simulation time	8425657 ps
CPU time	1.72 seconds
Started	Sep 24 02:54:46 PM UTC 24
Finished	Sep 24 02:54:49 PM UTC 24
Peak memory	246864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955086977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1955086977
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.614383586
Short name	T419
Test name
Test status
Simulation time	67276509 ps
CPU time	8.76 seconds
Started	Sep 24 02:51:13 PM UTC 24
Finished	Sep 24 02:51:23 PM UTC 24
Peak memory	262884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614383586 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_r w_with_rand_reset.614383586
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.2814904106
Short name	T161
Test name
Test status
Simulation time	60021850 ps
CPU time	5.46 seconds
Started	Sep 24 02:51:10 PM UTC 24
Finished	Sep 24 02:51:17 PM UTC 24
Peak memory	248472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814904106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2814904106
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.2846299130
Short name	T401
Test name
Test status
Simulation time	22091316 ps
CPU time	2.21 seconds
Started	Sep 24 02:51:09 PM UTC 24
Finished	Sep 24 02:51:12 PM UTC 24
Peak memory	248500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846299130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2846299130
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.295988347
Short name	T166
Test name
Test status
Simulation time	177477850 ps
CPU time	34.54 seconds
Started	Sep 24 02:51:12 PM UTC 24
Finished	Sep 24 02:51:48 PM UTC 24
Peak memory	260760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295988347 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.295988347
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2593745918
Short name	T202
Test name
Test status
Simulation time	24339927742 ps
CPU time	582.28 seconds
Started	Sep 24 02:50:57 PM UTC 24
Finished	Sep 24 03:00:48 PM UTC 24
Peak memory	277540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593745918 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shado w_reg_errors_with_csr_rw.2593745918
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.3389839377
Short name	T731
Test name
Test status
Simulation time	66845639 ps
CPU time	7.43 seconds
Started	Sep 24 02:51:04 PM UTC 24
Finished	Sep 24 02:51:12 PM UTC 24
Peak memory	260848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389839377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3389839377
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3217828619
Short name	T733
Test name
Test status
Simulation time	1834788324 ps
CPU time	12.97 seconds
Started	Sep 24 02:51:24 PM UTC 24
Finished	Sep 24 02:51:39 PM UTC 24
Peak memory	250588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217828619 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_ rw_with_rand_reset.3217828619
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.3547471451
Short name	T162
Test name
Test status
Simulation time	371518245 ps
CPU time	8.1 seconds
Started	Sep 24 02:51:23 PM UTC 24
Finished	Sep 24 02:51:33 PM UTC 24
Peak memory	250592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547471451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3547471451
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.3664145930
Short name	T402
Test name
Test status
Simulation time	11279064 ps
CPU time	2.12 seconds
Started	Sep 24 02:51:22 PM UTC 24
Finished	Sep 24 02:51:25 PM UTC 24
Peak memory	248496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664145930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3664145930
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2257589552
Short name	T755
Test name
Test status
Simulation time	662507858 ps
CPU time	65.08 seconds
Started	Sep 24 02:51:24 PM UTC 24
Finished	Sep 24 02:52:32 PM UTC 24
Peak memory	258916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257589552 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.2257589552
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1842131684
Short name	T177
Test name
Test status
Simulation time	2277830351 ps
CPU time	319.48 seconds
Started	Sep 24 02:51:13 PM UTC 24
Finished	Sep 24 02:56:38 PM UTC 24
Peak memory	281604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842131684 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shado w_reg_errors_with_csr_rw.1842131684
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.305405003
Short name	T732
Test name
Test status
Simulation time	800207519 ps
CPU time	20.49 seconds
Started	Sep 24 02:51:15 PM UTC 24
Finished	Sep 24 02:51:36 PM UTC 24
Peak memory	260824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305405003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.305405003
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3546967087
Short name	T224
Test name
Test status
Simulation time	416538117 ps
CPU time	4.51 seconds
Started	Sep 24 02:51:18 PM UTC 24
Finished	Sep 24 02:51:24 PM UTC 24
Peak memory	248744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546967087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3546967087
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1111138903
Short name	T418
Test name
Test status
Simulation time	232116234 ps
CPU time	10.54 seconds
Started	Sep 24 02:51:43 PM UTC 24
Finished	Sep 24 02:51:55 PM UTC 24
Peak memory	248544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111138903 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_ rw_with_rand_reset.1111138903
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.4044695488
Short name	T167
Test name
Test status
Simulation time	553679105 ps
CPU time	14 seconds
Started	Sep 24 02:51:40 PM UTC 24
Finished	Sep 24 02:51:55 PM UTC 24
Peak memory	248364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044695488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4044695488
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.4136704734
Short name	T403
Test name
Test status
Simulation time	11797600 ps
CPU time	2.13 seconds
Started	Sep 24 02:51:40 PM UTC 24
Finished	Sep 24 02:51:43 PM UTC 24
Peak memory	248412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136704734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4136704734
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1188203428
Short name	T738
Test name
Test status
Simulation time	332191854 ps
CPU time	19.81 seconds
Started	Sep 24 02:51:42 PM UTC 24
Finished	Sep 24 02:52:03 PM UTC 24
Peak memory	250788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188203428 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.1188203428
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.962228101
Short name	T176
Test name
Test status
Simulation time	44286684853 ps
CPU time	310.87 seconds
Started	Sep 24 02:51:26 PM UTC 24
Finished	Sep 24 02:56:42 PM UTC 24
Peak memory	283956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962228101 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.962228101
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1068726032
Short name	T193
Test name
Test status
Simulation time	7098487330 ps
CPU time	389.28 seconds
Started	Sep 24 02:51:25 PM UTC 24
Finished	Sep 24 02:58:01 PM UTC 24
Peak memory	277612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068726032 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado w_reg_errors_with_csr_rw.1068726032
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.2639454040
Short name	T734
Test name
Test status
Simulation time	1902732366 ps
CPU time	14.8 seconds
Started	Sep 24 02:51:33 PM UTC 24
Finished	Sep 24 02:51:50 PM UTC 24
Peak memory	260976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639454040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2639454040
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4159282657
Short name	T753
Test name
Test status
Simulation time	1409430520 ps
CPU time	50.38 seconds
Started	Sep 24 02:51:37 PM UTC 24
Finished	Sep 24 02:52:30 PM UTC 24
Peak memory	250528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159282657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4159282657
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4246343204
Short name	T743
Test name
Test status
Simulation time	603357993 ps
CPU time	19.94 seconds
Started	Sep 24 02:51:55 PM UTC 24
Finished	Sep 24 02:52:16 PM UTC 24
Peak memory	262876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246343204 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_ rw_with_rand_reset.4246343204
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.1954852047
Short name	T739
Test name
Test status
Simulation time	64229650 ps
CPU time	8.15 seconds
Started	Sep 24 02:51:54 PM UTC 24
Finished	Sep 24 02:52:04 PM UTC 24
Peak memory	248676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954852047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1954852047
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.823451156
Short name	T404
Test name
Test status
Simulation time	15260712 ps
CPU time	2.43 seconds
Started	Sep 24 02:51:50 PM UTC 24
Finished	Sep 24 02:51:54 PM UTC 24
Peak memory	248480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823451156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.823451156
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2319415012
Short name	T746
Test name
Test status
Simulation time	658570385 ps
CPU time	25.51 seconds
Started	Sep 24 02:51:55 PM UTC 24
Finished	Sep 24 02:52:21 PM UTC 24
Peak memory	258716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319415012 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.2319415012
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1594185731
Short name	T175
Test name
Test status
Simulation time	3817629559 ps
CPU time	245.11 seconds
Started	Sep 24 02:51:47 PM UTC 24
Finished	Sep 24 02:55:57 PM UTC 24
Peak memory	283948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594185731 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.1594185731
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.35428289
Short name	T412
Test name
Test status
Simulation time	24092723388 ps
CPU time	532.81 seconds
Started	Sep 24 02:51:44 PM UTC 24
Finished	Sep 24 03:00:44 PM UTC 24
Peak memory	277740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35428289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_ reg_errors_with_csr_rw.35428289
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.1386943178
Short name	T740
Test name
Test status
Simulation time	123666550 ps
CPU time	14.01 seconds
Started	Sep 24 02:51:49 PM UTC 24
Finished	Sep 24 02:52:04 PM UTC 24
Peak memory	260836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386943178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1386943178
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3040955780
Short name	T735
Test name
Test status
Simulation time	64359711 ps
CPU time	3.69 seconds
Started	Sep 24 02:51:49 PM UTC 24
Finished	Sep 24 02:51:54 PM UTC 24
Peak memory	248552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040955780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3040955780
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1909325080
Short name	T741
Test name
Test status
Simulation time	139487634 ps
CPU time	7.64 seconds
Started	Sep 24 02:52:04 PM UTC 24
Finished	Sep 24 02:52:13 PM UTC 24
Peak memory	250852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909325080 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_ rw_with_rand_reset.1909325080
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.24646545
Short name	T742
Test name
Test status
Simulation time	107720350 ps
CPU time	10.42 seconds
Started	Sep 24 02:52:02 PM UTC 24
Finished	Sep 24 02:52:14 PM UTC 24
Peak memory	248556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24646545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_han dler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.24646545
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.1785633074
Short name	T737
Test name
Test status
Simulation time	12129556 ps
CPU time	2.12 seconds
Started	Sep 24 02:51:58 PM UTC 24
Finished	Sep 24 02:52:01 PM UTC 24
Peak memory	248496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785633074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1785633074
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2438605408
Short name	T756
Test name
Test status
Simulation time	338959858 ps
CPU time	27.21 seconds
Started	Sep 24 02:52:04 PM UTC 24
Finished	Sep 24 02:52:33 PM UTC 24
Peak memory	258724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438605408 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.2438605408
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1875191131
Short name	T178
Test name
Test status
Simulation time	13843939082 ps
CPU time	163.74 seconds
Started	Sep 24 02:51:56 PM UTC 24
Finished	Sep 24 02:54:42 PM UTC 24
Peak memory	277736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875191131 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.1875191131
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.675954118
Short name	T411
Test name
Test status
Simulation time	20929690047 ps
CPU time	1519.02 seconds
Started	Sep 24 02:51:56 PM UTC 24
Finished	Sep 24 03:17:34 PM UTC 24
Peak memory	277516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675954118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow _reg_errors_with_csr_rw.675954118
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.2095214508
Short name	T744
Test name
Test status
Simulation time	173982303 ps
CPU time	19.69 seconds
Started	Sep 24 02:51:58 PM UTC 24
Finished	Sep 24 02:52:19 PM UTC 24
Peak memory	264928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095214508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2095214508
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.3473866634
Short name	T2
Test name
Test status
Simulation time	298593664 ps
CPU time	9.49 seconds
Started	Sep 24 02:55:44 PM UTC 24
Finished	Sep 24 02:55:54 PM UTC 24
Peak memory	260340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473866634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3473866634
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.1740497145
Short name	T151
Test name
Test status
Simulation time	8693161688 ps
CPU time	190.85 seconds
Started	Sep 24 02:55:43 PM UTC 24
Finished	Sep 24 02:58:57 PM UTC 24
Peak memory	266696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740497145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1740497145
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.2692641618
Short name	T14
Test name
Test status
Simulation time	2000952912 ps
CPU time	59.28 seconds
Started	Sep 24 02:55:43 PM UTC 24
Finished	Sep 24 02:56:44 PM UTC 24
Peak memory	260452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692641618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2692641618
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.691219744
Short name	T331
Test name
Test status
Simulation time	86424907848 ps
CPU time	1509.89 seconds
Started	Sep 24 02:55:44 PM UTC 24
Finished	Sep 24 03:21:12 PM UTC 24
Peak memory	283156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691219744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.691219744
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.657573843
Short name	T18
Test name
Test status
Simulation time	24129189177 ps
CPU time	241.1 seconds
Started	Sep 24 02:55:44 PM UTC 24
Finished	Sep 24 02:59:48 PM UTC 24
Peak memory	260636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657573843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.657573843
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.2362424852
Short name	T9
Test name
Test status
Simulation time	177165855 ps
CPU time	18.85 seconds
Started	Sep 24 02:55:41 PM UTC 24
Finished	Sep 24 02:56:01 PM UTC 24
Peak memory	266604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362424852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2362424852
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.3532834090
Short name	T4
Test name
Test status
Simulation time	879513252 ps
CPU time	17.88 seconds
Started	Sep 24 02:55:44 PM UTC 24
Finished	Sep 24 02:56:03 PM UTC 24
Peak memory	292876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532834090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3532834090
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.2506069030
Short name	T152
Test name
Test status
Simulation time	8792461575 ps
CPU time	215.6 seconds
Started	Sep 24 02:55:44 PM UTC 24
Finished	Sep 24 02:59:23 PM UTC 24
Peak memory	266700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506069030 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.2506069030
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/0.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.2931979772
Short name	T11
Test name
Test status
Simulation time	16622726 ps
CPU time	2.77 seconds
Started	Sep 24 02:55:58 PM UTC 24
Finished	Sep 24 02:56:02 PM UTC 24
Peak memory	260696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931979772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2931979772
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.423039677
Short name	T5
Test name
Test status
Simulation time	1494955861 ps
CPU time	9.94 seconds
Started	Sep 24 02:55:55 PM UTC 24
Finished	Sep 24 02:56:06 PM UTC 24
Peak memory	260432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423039677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.423039677
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.3969681011
Short name	T243
Test name
Test status
Simulation time	3388749914 ps
CPU time	220.85 seconds
Started	Sep 24 02:55:47 PM UTC 24
Finished	Sep 24 02:59:31 PM UTC 24
Peak memory	266704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969681011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3969681011
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.2183251349
Short name	T389
Test name
Test status
Simulation time	132612799031 ps
CPU time	2245.47 seconds
Started	Sep 24 02:55:51 PM UTC 24
Finished	Sep 24 03:33:44 PM UTC 24
Peak memory	295984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183251349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2183251349
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.4060693664
Short name	T274
Test name
Test status
Simulation time	31767470938 ps
CPU time	322.74 seconds
Started	Sep 24 02:55:48 PM UTC 24
Finished	Sep 24 03:01:15 PM UTC 24
Peak memory	266784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060693664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.4060693664
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.536064444
Short name	T15
Test name
Test status
Simulation time	659028818 ps
CPU time	41.52 seconds
Started	Sep 24 02:55:45 PM UTC 24
Finished	Sep 24 02:56:28 PM UTC 24
Peak memory	266872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536064444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.536064444
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.1624142766
Short name	T3
Test name
Test status
Simulation time	166558258 ps
CPU time	13.37 seconds
Started	Sep 24 02:55:47 PM UTC 24
Finished	Sep 24 02:56:01 PM UTC 24
Peak memory	266680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624142766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1624142766
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.4194181758
Short name	T42
Test name
Test status
Simulation time	699140275 ps
CPU time	51.8 seconds
Started	Sep 24 02:55:45 PM UTC 24
Finished	Sep 24 02:56:39 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194181758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.4194181758
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.3803507809
Short name	T272
Test name
Test status
Simulation time	72827567031 ps
CPU time	1877.29 seconds
Started	Sep 24 02:55:55 PM UTC 24
Finished	Sep 24 03:27:35 PM UTC 24
Peak memory	299472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803507809 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.3803507809
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/1.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.993682410
Short name	T73
Test name
Test status
Simulation time	106943970 ps
CPU time	5.22 seconds
Started	Sep 24 03:05:01 PM UTC 24
Finished	Sep 24 03:05:07 PM UTC 24
Peak memory	260700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993682410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.993682410
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.45640354
Short name	T139
Test name
Test status
Simulation time	99743588090 ps
CPU time	3006.7 seconds
Started	Sep 24 03:03:41 PM UTC 24
Finished	Sep 24 03:54:22 PM UTC 24
Peak memory	295916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45640354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.45640354
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.3139108181
Short name	T71
Test name
Test status
Simulation time	2990014254 ps
CPU time	48.87 seconds
Started	Sep 24 03:04:09 PM UTC 24
Finished	Sep 24 03:04:59 PM UTC 24
Peak memory	260508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139108181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3139108181
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.3528809694
Short name	T429
Test name
Test status
Simulation time	7567648464 ps
CPU time	269.41 seconds
Started	Sep 24 03:03:33 PM UTC 24
Finished	Sep 24 03:08:07 PM UTC 24
Peak memory	266964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528809694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3528809694
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.571184411
Short name	T70
Test name
Test status
Simulation time	367336548 ps
CPU time	35.89 seconds
Started	Sep 24 03:03:31 PM UTC 24
Finished	Sep 24 03:04:08 PM UTC 24
Peak memory	266572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571184411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.571184411
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.3406657498
Short name	T353
Test name
Test status
Simulation time	190290379368 ps
CPU time	2857.06 seconds
Started	Sep 24 03:04:06 PM UTC 24
Finished	Sep 24 03:52:15 PM UTC 24
Peak memory	295908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406657498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3406657498
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.2895768386
Short name	T115
Test name
Test status
Simulation time	6811626333 ps
CPU time	866.31 seconds
Started	Sep 24 03:04:06 PM UTC 24
Finished	Sep 24 03:18:43 PM UTC 24
Peak memory	283096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895768386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2895768386
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.2372407007
Short name	T425
Test name
Test status
Simulation time	2854492966 ps
CPU time	23.32 seconds
Started	Sep 24 03:03:05 PM UTC 24
Finished	Sep 24 03:03:30 PM UTC 24
Peak memory	260516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372407007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2372407007
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.3408494441
Short name	T54
Test name
Test status
Simulation time	257644952 ps
CPU time	26.42 seconds
Started	Sep 24 03:03:16 PM UTC 24
Finished	Sep 24 03:03:44 PM UTC 24
Peak memory	264532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408494441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3408494441
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.810639005
Short name	T69
Test name
Test status
Simulation time	128827898 ps
CPU time	22.52 seconds
Started	Sep 24 03:03:41 PM UTC 24
Finished	Sep 24 03:04:05 PM UTC 24
Peak memory	260468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810639005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.810639005
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.2040815702
Short name	T281
Test name
Test status
Simulation time	329229910 ps
CPU time	34.86 seconds
Started	Sep 24 03:03:04 PM UTC 24
Finished	Sep 24 03:03:40 PM UTC 24
Peak memory	266848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040815702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2040815702
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.546352834
Short name	T140
Test name
Test status
Simulation time	192741482384 ps
CPU time	3382.47 seconds
Started	Sep 24 03:04:55 PM UTC 24
Finished	Sep 24 04:01:57 PM UTC 24
Peak memory	302044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546352834 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.546352834
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/10.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.698340096
Short name	T231
Test name
Test status
Simulation time	67623079 ps
CPU time	5.64 seconds
Started	Sep 24 03:06:45 PM UTC 24
Finished	Sep 24 03:06:51 PM UTC 24
Peak memory	260696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698340096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.698340096
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.3858678293
Short name	T345
Test name
Test status
Simulation time	21880596481 ps
CPU time	1449.18 seconds
Started	Sep 24 03:05:39 PM UTC 24
Finished	Sep 24 03:30:06 PM UTC 24
Peak memory	299480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858678293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3858678293
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.1099765131
Short name	T426
Test name
Test status
Simulation time	352374146 ps
CPU time	27.07 seconds
Started	Sep 24 03:06:11 PM UTC 24
Finished	Sep 24 03:06:40 PM UTC 24
Peak memory	260708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099765131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1099765131
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.568330039
Short name	T269
Test name
Test status
Simulation time	24966192122 ps
CPU time	200.68 seconds
Started	Sep 24 03:05:27 PM UTC 24
Finished	Sep 24 03:08:51 PM UTC 24
Peak memory	266732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568330039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.568330039
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.2789460101
Short name	T100
Test name
Test status
Simulation time	171121461 ps
CPU time	17.91 seconds
Started	Sep 24 03:05:19 PM UTC 24
Finished	Sep 24 03:05:38 PM UTC 24
Peak memory	266648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789460101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2789460101
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.3704327840
Short name	T396
Test name
Test status
Simulation time	39262620702 ps
CPU time	1511.67 seconds
Started	Sep 24 03:06:08 PM UTC 24
Finished	Sep 24 03:31:39 PM UTC 24
Peak memory	283428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704327840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3704327840
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.3980021023
Short name	T275
Test name
Test status
Simulation time	857559259 ps
CPU time	92.68 seconds
Started	Sep 24 03:05:08 PM UTC 24
Finished	Sep 24 03:06:43 PM UTC 24
Peak memory	266616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980021023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3980021023
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.2716789810
Short name	T427
Test name
Test status
Simulation time	3995265517 ps
CPU time	100.01 seconds
Started	Sep 24 03:05:15 PM UTC 24
Finished	Sep 24 03:06:57 PM UTC 24
Peak memory	260528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716789810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2716789810
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.1999093401
Short name	T75
Test name
Test status
Simulation time	125386726 ps
CPU time	13.67 seconds
Started	Sep 24 03:05:03 PM UTC 24
Finished	Sep 24 03:05:18 PM UTC 24
Peak memory	262560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999093401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1999093401
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.2961717198
Short name	T349
Test name
Test status
Simulation time	19300085686 ps
CPU time	934.19 seconds
Started	Sep 24 03:06:40 PM UTC 24
Finished	Sep 24 03:22:27 PM UTC 24
Peak memory	283228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961717198 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.2961717198
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/11.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.2955546712
Short name	T293
Test name
Test status
Simulation time	20927991350 ps
CPU time	1071.36 seconds
Started	Sep 24 03:08:50 PM UTC 24
Finished	Sep 24 03:26:54 PM UTC 24
Peak memory	283292 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955546712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2955546712
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.702868867
Short name	T431
Test name
Test status
Simulation time	480938145 ps
CPU time	21.9 seconds
Started	Sep 24 03:08:58 PM UTC 24
Finished	Sep 24 03:09:22 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702868867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.702868867
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.3406708357
Short name	T434
Test name
Test status
Simulation time	6002947658 ps
CPU time	134.72 seconds
Started	Sep 24 03:08:09 PM UTC 24
Finished	Sep 24 03:10:26 PM UTC 24
Peak memory	266964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406708357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3406708357
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.3306830392
Short name	T432
Test name
Test status
Simulation time	5835480216 ps
CPU time	114.72 seconds
Started	Sep 24 03:07:46 PM UTC 24
Finished	Sep 24 03:09:44 PM UTC 24
Peak memory	266968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306830392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3306830392
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.722643848
Short name	T378
Test name
Test status
Simulation time	74250740808 ps
CPU time	1867.99 seconds
Started	Sep 24 03:08:53 PM UTC 24
Finished	Sep 24 03:40:24 PM UTC 24
Peak memory	299472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722643848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.722643848
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.1699060575
Short name	T486
Test name
Test status
Simulation time	43407941705 ps
CPU time	1499.05 seconds
Started	Sep 24 03:08:54 PM UTC 24
Finished	Sep 24 03:34:13 PM UTC 24
Peak memory	299556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699060575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1699060575
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.1720149337
Short name	T430
Test name
Test status
Simulation time	2533264899 ps
CPU time	77.34 seconds
Started	Sep 24 03:07:38 PM UTC 24
Finished	Sep 24 03:08:57 PM UTC 24
Peak memory	266936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720149337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1720149337
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.3082077080
Short name	T55
Test name
Test status
Simulation time	17653544308 ps
CPU time	67.75 seconds
Started	Sep 24 03:07:44 PM UTC 24
Finished	Sep 24 03:08:54 PM UTC 24
Peak memory	260560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082077080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3082077080
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.219849205
Short name	T244
Test name
Test status
Simulation time	1146298352 ps
CPU time	48.95 seconds
Started	Sep 24 03:08:27 PM UTC 24
Finished	Sep 24 03:09:18 PM UTC 24
Peak memory	260464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219849205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.219849205
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.2390241207
Short name	T428
Test name
Test status
Simulation time	967238931 ps
CPU time	37.54 seconds
Started	Sep 24 03:06:58 PM UTC 24
Finished	Sep 24 03:07:37 PM UTC 24
Peak memory	266656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390241207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2390241207
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.3859566997
Short name	T306
Test name
Test status
Simulation time	239373085904 ps
CPU time	4020.26 seconds
Started	Sep 24 03:09:19 PM UTC 24
Finished	Sep 24 04:17:09 PM UTC 24
Peak memory	302048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859566997 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.3859566997
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/12.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.3565143028
Short name	T304
Test name
Test status
Simulation time	32960321786 ps
CPU time	2271.1 seconds
Started	Sep 24 03:10:26 PM UTC 24
Finished	Sep 24 03:48:46 PM UTC 24
Peak memory	283164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565143028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3565143028
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.3269965379
Short name	T438
Test name
Test status
Simulation time	6139110110 ps
CPU time	52.41 seconds
Started	Sep 24 03:11:12 PM UTC 24
Finished	Sep 24 03:12:07 PM UTC 24
Peak memory	260836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269965379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3269965379
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.2665234356
Short name	T436
Test name
Test status
Simulation time	3383156308 ps
CPU time	43.64 seconds
Started	Sep 24 03:10:17 PM UTC 24
Finished	Sep 24 03:11:02 PM UTC 24
Peak memory	266636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665234356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2665234356
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.2446786362
Short name	T435
Test name
Test status
Simulation time	297193114 ps
CPU time	29.4 seconds
Started	Sep 24 03:10:03 PM UTC 24
Finished	Sep 24 03:10:35 PM UTC 24
Peak memory	260632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446786362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2446786362
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.2434154764
Short name	T372
Test name
Test status
Simulation time	89094105702 ps
CPU time	1817.99 seconds
Started	Sep 24 03:10:36 PM UTC 24
Finished	Sep 24 03:41:16 PM UTC 24
Peak memory	283356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434154764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2434154764
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.3862297451
Short name	T517
Test name
Test status
Simulation time	289967436918 ps
CPU time	2252.96 seconds
Started	Sep 24 03:11:03 PM UTC 24
Finished	Sep 24 03:49:04 PM UTC 24
Peak memory	299556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862297451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3862297451
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.2351500027
Short name	T357
Test name
Test status
Simulation time	2343503740 ps
CPU time	78.67 seconds
Started	Sep 24 03:10:28 PM UTC 24
Finished	Sep 24 03:11:48 PM UTC 24
Peak memory	260508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351500027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2351500027
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.3517881814
Short name	T437
Test name
Test status
Simulation time	3148933625 ps
CPU time	73.4 seconds
Started	Sep 24 03:09:56 PM UTC 24
Finished	Sep 24 03:11:12 PM UTC 24
Peak memory	266936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517881814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3517881814
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.3281681311
Short name	T56
Test name
Test status
Simulation time	208643236 ps
CPU time	23.68 seconds
Started	Sep 24 03:09:58 PM UTC 24
Finished	Sep 24 03:10:24 PM UTC 24
Peak memory	264560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281681311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3281681311
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.4129543425
Short name	T57
Test name
Test status
Simulation time	271747786 ps
CPU time	47.29 seconds
Started	Sep 24 03:10:24 PM UTC 24
Finished	Sep 24 03:11:13 PM UTC 24
Peak memory	260500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129543425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4129543425
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.1552704435
Short name	T433
Test name
Test status
Simulation time	141215233 ps
CPU time	16.37 seconds
Started	Sep 24 03:09:45 PM UTC 24
Finished	Sep 24 03:10:03 PM UTC 24
Peak memory	262560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552704435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1552704435
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.4265015860
Short name	T568
Test name
Test status
Simulation time	157060514383 ps
CPU time	3126.54 seconds
Started	Sep 24 03:11:14 PM UTC 24
Finished	Sep 24 04:04:00 PM UTC 24
Peak memory	302048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265015860 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.4265015860
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all_with_rand_reset.3180815557
Short name	T59
Test name
Test status
Simulation time	1748772215 ps
CPU time	222.72 seconds
Started	Sep 24 03:11:27 PM UTC 24
Finished	Sep 24 03:15:13 PM UTC 24
Peak memory	277208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3180815557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.a lert_handler_stress_all_with_rand_reset.3180815557
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.4142955065
Short name	T38
Test name
Test status
Simulation time	33092251897 ps
CPU time	2353.72 seconds
Started	Sep 24 03:12:56 PM UTC 24
Finished	Sep 24 03:52:39 PM UTC 24
Peak memory	297428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142955065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.4142955065
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.125229275
Short name	T443
Test name
Test status
Simulation time	973949568 ps
CPU time	57.35 seconds
Started	Sep 24 03:13:25 PM UTC 24
Finished	Sep 24 03:14:24 PM UTC 24
Peak memory	260432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125229275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.125229275
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.631157705
Short name	T299
Test name
Test status
Simulation time	5745282045 ps
CPU time	167.7 seconds
Started	Sep 24 03:12:29 PM UTC 24
Finished	Sep 24 03:15:19 PM UTC 24
Peak memory	266732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631157705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.631157705
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.3725865794
Short name	T440
Test name
Test status
Simulation time	906726447 ps
CPU time	23.44 seconds
Started	Sep 24 03:12:07 PM UTC 24
Finished	Sep 24 03:12:32 PM UTC 24
Peak memory	266840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725865794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3725865794
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.3563065212
Short name	T363
Test name
Test status
Simulation time	197326100359 ps
CPU time	2965.22 seconds
Started	Sep 24 03:13:11 PM UTC 24
Finished	Sep 24 04:03:12 PM UTC 24
Peak memory	302048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563065212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3563065212
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.1520289629
Short name	T290
Test name
Test status
Simulation time	22301996832 ps
CPU time	1244.69 seconds
Started	Sep 24 03:13:23 PM UTC 24
Finished	Sep 24 03:34:24 PM UTC 24
Peak memory	299492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520289629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1520289629
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.4013517540
Short name	T439
Test name
Test status
Simulation time	1293532033 ps
CPU time	35.93 seconds
Started	Sep 24 03:11:50 PM UTC 24
Finished	Sep 24 03:12:28 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013517540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.4013517540
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.3141041570
Short name	T442
Test name
Test status
Simulation time	3335902649 ps
CPU time	81.97 seconds
Started	Sep 24 03:12:00 PM UTC 24
Finished	Sep 24 03:13:24 PM UTC 24
Peak memory	266656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141041570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3141041570
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.233567472
Short name	T93
Test name
Test status
Simulation time	1071631794 ps
CPU time	36.13 seconds
Started	Sep 24 03:12:33 PM UTC 24
Finished	Sep 24 03:13:10 PM UTC 24
Peak memory	266584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233567472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.233567472
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.2697557740
Short name	T441
Test name
Test status
Simulation time	1172191641 ps
CPU time	78.14 seconds
Started	Sep 24 03:11:50 PM UTC 24
Finished	Sep 24 03:13:10 PM UTC 24
Peak memory	266656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697557740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2697557740
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.2775726257
Short name	T96
Test name
Test status
Simulation time	6397012213 ps
CPU time	117.47 seconds
Started	Sep 24 03:14:18 PM UTC 24
Finished	Sep 24 03:16:18 PM UTC 24
Peak memory	266704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775726257 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.2775726257
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.3917375296
Short name	T235
Test name
Test status
Simulation time	14135134 ps
CPU time	4.08 seconds
Started	Sep 24 03:16:31 PM UTC 24
Finished	Sep 24 03:16:36 PM UTC 24
Peak memory	260704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917375296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3917375296
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.1600037363
Short name	T116
Test name
Test status
Simulation time	8990251206 ps
CPU time	1354.16 seconds
Started	Sep 24 03:16:04 PM UTC 24
Finished	Sep 24 03:38:56 PM UTC 24
Peak memory	299476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600037363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1600037363
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.1978622324
Short name	T447
Test name
Test status
Simulation time	729954941 ps
CPU time	28.57 seconds
Started	Sep 24 03:16:21 PM UTC 24
Finished	Sep 24 03:16:51 PM UTC 24
Peak memory	260708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978622324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1978622324
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.819086678
Short name	T446
Test name
Test status
Simulation time	1163689908 ps
CPU time	28.21 seconds
Started	Sep 24 03:15:50 PM UTC 24
Finished	Sep 24 03:16:20 PM UTC 24
Peak memory	266868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819086678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.819086678
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.4188242855
Short name	T94
Test name
Test status
Simulation time	359735772 ps
CPU time	41.55 seconds
Started	Sep 24 03:15:20 PM UTC 24
Finished	Sep 24 03:16:03 PM UTC 24
Peak memory	266576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188242855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.4188242855
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.4193061967
Short name	T375
Test name
Test status
Simulation time	64337364432 ps
CPU time	2224.21 seconds
Started	Sep 24 03:16:17 PM UTC 24
Finished	Sep 24 03:53:47 PM UTC 24
Peak memory	293332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193061967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.4193061967
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.3391481707
Short name	T132
Test name
Test status
Simulation time	36957709470 ps
CPU time	1686.03 seconds
Started	Sep 24 03:16:19 PM UTC 24
Finished	Sep 24 03:44:46 PM UTC 24
Peak memory	299684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391481707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3391481707
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.3099622851
Short name	T343
Test name
Test status
Simulation time	11876527900 ps
CPU time	423.36 seconds
Started	Sep 24 03:16:17 PM UTC 24
Finished	Sep 24 03:23:26 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099622851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3099622851
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.2380024438
Short name	T60
Test name
Test status
Simulation time	874898948 ps
CPU time	59.28 seconds
Started	Sep 24 03:15:15 PM UTC 24
Finished	Sep 24 03:16:16 PM UTC 24
Peak memory	260468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380024438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2380024438
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.2059853177
Short name	T444
Test name
Test status
Simulation time	7006326148 ps
CPU time	33.43 seconds
Started	Sep 24 03:15:15 PM UTC 24
Finished	Sep 24 03:15:50 PM UTC 24
Peak memory	260664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059853177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2059853177
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.3253605996
Short name	T95
Test name
Test status
Simulation time	232112049 ps
CPU time	23.72 seconds
Started	Sep 24 03:15:50 PM UTC 24
Finished	Sep 24 03:16:15 PM UTC 24
Peak memory	260428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253605996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3253605996
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.1379938065
Short name	T445
Test name
Test status
Simulation time	8696778697 ps
CPU time	60.68 seconds
Started	Sep 24 03:14:47 PM UTC 24
Finished	Sep 24 03:15:50 PM UTC 24
Peak memory	266976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379938065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1379938065
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.1223578715
Short name	T126
Test name
Test status
Simulation time	33584647511 ps
CPU time	2196.38 seconds
Started	Sep 24 03:16:31 PM UTC 24
Finished	Sep 24 03:53:34 PM UTC 24
Peak memory	293332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223578715 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.1223578715
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/15.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.3490683019
Short name	T236
Test name
Test status
Simulation time	18623231 ps
CPU time	4.53 seconds
Started	Sep 24 03:18:21 PM UTC 24
Finished	Sep 24 03:18:26 PM UTC 24
Peak memory	260776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490683019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3490683019
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.3626667719
Short name	T564
Test name
Test status
Simulation time	179097658392 ps
CPU time	2695.98 seconds
Started	Sep 24 03:17:56 PM UTC 24
Finished	Sep 24 04:03:23 PM UTC 24
Peak memory	302124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626667719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3626667719
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.598225206
Short name	T451
Test name
Test status
Simulation time	1832181144 ps
CPU time	21.66 seconds
Started	Sep 24 03:18:05 PM UTC 24
Finished	Sep 24 03:18:28 PM UTC 24
Peak memory	260696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598225206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.598225206
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.2167220357
Short name	T289
Test name
Test status
Simulation time	10441706461 ps
CPU time	94.3 seconds
Started	Sep 24 03:17:37 PM UTC 24
Finished	Sep 24 03:19:13 PM UTC 24
Peak memory	266772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167220357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2167220357
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.76582004
Short name	T450
Test name
Test status
Simulation time	1640982645 ps
CPU time	56.77 seconds
Started	Sep 24 03:17:21 PM UTC 24
Finished	Sep 24 03:18:20 PM UTC 24
Peak memory	260696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76582004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc _intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.76582004
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.2654816366
Short name	T129
Test name
Test status
Simulation time	46467182922 ps
CPU time	1865.07 seconds
Started	Sep 24 03:17:58 PM UTC 24
Finished	Sep 24 03:49:26 PM UTC 24
Peak memory	283096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654816366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2654816366
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.3258574698
Short name	T339
Test name
Test status
Simulation time	2550831252 ps
CPU time	165.73 seconds
Started	Sep 24 03:17:58 PM UTC 24
Finished	Sep 24 03:20:47 PM UTC 24
Peak memory	260580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258574698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3258574698
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.1292205205
Short name	T448
Test name
Test status
Simulation time	508812231 ps
CPU time	26.94 seconds
Started	Sep 24 03:16:52 PM UTC 24
Finished	Sep 24 03:17:20 PM UTC 24
Peak memory	260472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292205205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1292205205
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.1956858299
Short name	T276
Test name
Test status
Simulation time	806813478 ps
CPU time	35.72 seconds
Started	Sep 24 03:17:18 PM UTC 24
Finished	Sep 24 03:17:56 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956858299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1956858299
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.3108412725
Short name	T147
Test name
Test status
Simulation time	5646987048 ps
CPU time	56.92 seconds
Started	Sep 24 03:17:54 PM UTC 24
Finished	Sep 24 03:18:53 PM UTC 24
Peak memory	260820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108412725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3108412725
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.528658168
Short name	T449
Test name
Test status
Simulation time	2663861102 ps
CPU time	63.83 seconds
Started	Sep 24 03:16:50 PM UTC 24
Finished	Sep 24 03:17:56 PM UTC 24
Peak memory	260496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528658168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.528658168
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.356120447
Short name	T535
Test name
Test status
Simulation time	130995796240 ps
CPU time	2207.11 seconds
Started	Sep 24 03:18:07 PM UTC 24
Finished	Sep 24 03:55:21 PM UTC 24
Peak memory	299540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356120447 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.356120447
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all_with_rand_reset.1316737358
Short name	T97
Test name
Test status
Simulation time	2705454697 ps
CPU time	94.15 seconds
Started	Sep 24 03:18:27 PM UTC 24
Finished	Sep 24 03:20:03 PM UTC 24
Peak memory	277008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1316737358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.a lert_handler_stress_all_with_rand_reset.1316737358
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.325460004
Short name	T237
Test name
Test status
Simulation time	266366619 ps
CPU time	7.02 seconds
Started	Sep 24 03:20:48 PM UTC 24
Finished	Sep 24 03:20:56 PM UTC 24
Peak memory	260700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325460004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.325460004
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.2967934213
Short name	T520
Test name
Test status
Simulation time	12364896234 ps
CPU time	1862.89 seconds
Started	Sep 24 03:19:15 PM UTC 24
Finished	Sep 24 03:50:42 PM UTC 24
Peak memory	299476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967934213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2967934213
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.3399927298
Short name	T457
Test name
Test status
Simulation time	1818210190 ps
CPU time	42.59 seconds
Started	Sep 24 03:20:29 PM UTC 24
Finished	Sep 24 03:21:13 PM UTC 24
Peak memory	260516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399927298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3399927298
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.802571699
Short name	T464
Test name
Test status
Simulation time	5046252465 ps
CPU time	368.17 seconds
Started	Sep 24 03:18:53 PM UTC 24
Finished	Sep 24 03:25:07 PM UTC 24
Peak memory	262708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802571699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.802571699
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.3360329982
Short name	T454
Test name
Test status
Simulation time	1456983889 ps
CPU time	30.9 seconds
Started	Sep 24 03:18:49 PM UTC 24
Finished	Sep 24 03:19:21 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360329982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3360329982
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.1895707644
Short name	T569
Test name
Test status
Simulation time	45718199121 ps
CPU time	2985.08 seconds
Started	Sep 24 03:20:15 PM UTC 24
Finished	Sep 24 04:10:36 PM UTC 24
Peak memory	300012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895707644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1895707644
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.4092305584
Short name	T452
Test name
Test status
Simulation time	171506352 ps
CPU time	14.67 seconds
Started	Sep 24 03:18:32 PM UTC 24
Finished	Sep 24 03:18:48 PM UTC 24
Peak memory	260792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092305584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.4092305584
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.1500582241
Short name	T456
Test name
Test status
Simulation time	965710032 ps
CPU time	100.17 seconds
Started	Sep 24 03:18:45 PM UTC 24
Finished	Sep 24 03:20:28 PM UTC 24
Peak memory	266936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500582241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1500582241
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.3925852494
Short name	T455
Test name
Test status
Simulation time	1926433218 ps
CPU time	56.58 seconds
Started	Sep 24 03:19:15 PM UTC 24
Finished	Sep 24 03:20:13 PM UTC 24
Peak memory	260500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925852494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3925852494
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.4227115746
Short name	T453
Test name
Test status
Simulation time	1113055263 ps
CPU time	43.1 seconds
Started	Sep 24 03:18:29 PM UTC 24
Finished	Sep 24 03:19:14 PM UTC 24
Peak memory	260512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227115746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4227115746
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.2854618208
Short name	T33
Test name
Test status
Simulation time	3077457194 ps
CPU time	85.65 seconds
Started	Sep 24 03:20:34 PM UTC 24
Finished	Sep 24 03:22:02 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854618208 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.2854618208
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all_with_rand_reset.3829147335
Short name	T61
Test name
Test status
Simulation time	7825174659 ps
CPU time	236.81 seconds
Started	Sep 24 03:20:52 PM UTC 24
Finished	Sep 24 03:24:53 PM UTC 24
Peak memory	277144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3829147335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.a lert_handler_stress_all_with_rand_reset.3829147335
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.3842241072
Short name	T238
Test name
Test status
Simulation time	87376014 ps
CPU time	4.37 seconds
Started	Sep 24 03:23:40 PM UTC 24
Finished	Sep 24 03:23:45 PM UTC 24
Peak memory	260700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842241072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3842241072
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.3570943141
Short name	T529
Test name
Test status
Simulation time	49714037713 ps
CPU time	1896.46 seconds
Started	Sep 24 03:22:02 PM UTC 24
Finished	Sep 24 03:54:03 PM UTC 24
Peak memory	281116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570943141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3570943141
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.801502658
Short name	T460
Test name
Test status
Simulation time	188008917 ps
CPU time	10.66 seconds
Started	Sep 24 03:23:27 PM UTC 24
Finished	Sep 24 03:23:39 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801502658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.801502658
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.3934598602
Short name	T461
Test name
Test status
Simulation time	2102678396 ps
CPU time	115.93 seconds
Started	Sep 24 03:21:40 PM UTC 24
Finished	Sep 24 03:23:39 PM UTC 24
Peak memory	266568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934598602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3934598602
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.2524267112
Short name	T148
Test name
Test status
Simulation time	41569702 ps
CPU time	9.46 seconds
Started	Sep 24 03:21:29 PM UTC 24
Finished	Sep 24 03:21:40 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524267112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2524267112
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.3669474592
Short name	T521
Test name
Test status
Simulation time	26344157145 ps
CPU time	1690.94 seconds
Started	Sep 24 03:22:37 PM UTC 24
Finished	Sep 24 03:51:08 PM UTC 24
Peak memory	276956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669474592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3669474592
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.2741437611
Short name	T352
Test name
Test status
Simulation time	6386233414 ps
CPU time	186.36 seconds
Started	Sep 24 03:22:06 PM UTC 24
Finished	Sep 24 03:25:15 PM UTC 24
Peak memory	260568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741437611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2741437611
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.3376000105
Short name	T458
Test name
Test status
Simulation time	101359292 ps
CPU time	12.78 seconds
Started	Sep 24 03:21:14 PM UTC 24
Finished	Sep 24 03:21:28 PM UTC 24
Peak memory	260728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376000105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3376000105
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.3879776554
Short name	T113
Test name
Test status
Simulation time	2658529959 ps
CPU time	47.65 seconds
Started	Sep 24 03:21:15 PM UTC 24
Finished	Sep 24 03:22:04 PM UTC 24
Peak memory	266640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879776554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3879776554
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.2990674992
Short name	T459
Test name
Test status
Simulation time	1085444909 ps
CPU time	40.1 seconds
Started	Sep 24 03:20:58 PM UTC 24
Finished	Sep 24 03:21:39 PM UTC 24
Peak memory	266584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990674992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2990674992
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.3833076082
Short name	T102
Test name
Test status
Simulation time	5811703140 ps
CPU time	546.17 seconds
Started	Sep 24 03:23:40 PM UTC 24
Finished	Sep 24 03:32:54 PM UTC 24
Peak memory	266780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833076082 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.3833076082
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/18.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.2238797987
Short name	T239
Test name
Test status
Simulation time	109243917 ps
CPU time	5.72 seconds
Started	Sep 24 03:26:39 PM UTC 24
Finished	Sep 24 03:26:46 PM UTC 24
Peak memory	260968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238797987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2238797987
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.93044365
Short name	T347
Test name
Test status
Simulation time	9453627265 ps
CPU time	1335.91 seconds
Started	Sep 24 03:25:18 PM UTC 24
Finished	Sep 24 03:47:51 PM UTC 24
Peak memory	299744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93044365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.93044365
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.1010143335
Short name	T469
Test name
Test status
Simulation time	430674083 ps
CPU time	33.34 seconds
Started	Sep 24 03:26:03 PM UTC 24
Finished	Sep 24 03:26:38 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010143335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1010143335
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.4183781316
Short name	T111
Test name
Test status
Simulation time	3621086319 ps
CPU time	85.52 seconds
Started	Sep 24 03:25:08 PM UTC 24
Finished	Sep 24 03:26:36 PM UTC 24
Peak memory	266636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183781316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.4183781316
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.3579335345
Short name	T466
Test name
Test status
Simulation time	1511512754 ps
CPU time	20.49 seconds
Started	Sep 24 03:25:02 PM UTC 24
Finished	Sep 24 03:25:24 PM UTC 24
Peak memory	264528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579335345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3579335345
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.3745197715
Short name	T393
Test name
Test status
Simulation time	30835766478 ps
CPU time	2334.65 seconds
Started	Sep 24 03:25:41 PM UTC 24
Finished	Sep 24 04:05:04 PM UTC 24
Peak memory	285868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745197715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3745197715
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.1372062612
Short name	T511
Test name
Test status
Simulation time	11673035057 ps
CPU time	1278.81 seconds
Started	Sep 24 03:25:44 PM UTC 24
Finished	Sep 24 03:47:19 PM UTC 24
Peak memory	299480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372062612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1372062612
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.3535960855
Short name	T465
Test name
Test status
Simulation time	324627887 ps
CPU time	21.01 seconds
Started	Sep 24 03:24:55 PM UTC 24
Finished	Sep 24 03:25:18 PM UTC 24
Peak memory	264548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535960855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3535960855
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.2230549255
Short name	T463
Test name
Test status
Simulation time	57046544 ps
CPU time	3.06 seconds
Started	Sep 24 03:24:57 PM UTC 24
Finished	Sep 24 03:25:01 PM UTC 24
Peak memory	250220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230549255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2230549255
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.3895996930
Short name	T468
Test name
Test status
Simulation time	900575939 ps
CPU time	44.08 seconds
Started	Sep 24 03:25:16 PM UTC 24
Finished	Sep 24 03:26:02 PM UTC 24
Peak memory	260428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895996930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3895996930
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.3521347160
Short name	T462
Test name
Test status
Simulation time	867610901 ps
CPU time	44.68 seconds
Started	Sep 24 03:24:10 PM UTC 24
Finished	Sep 24 03:24:56 PM UTC 24
Peak memory	266592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521347160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3521347160
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all_with_rand_reset.290448699
Short name	T98
Test name
Test status
Simulation time	904107355 ps
CPU time	88.87 seconds
Started	Sep 24 03:26:47 PM UTC 24
Finished	Sep 24 03:28:18 PM UTC 24
Peak memory	277016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=290448699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.al ert_handler_stress_all_with_rand_reset.290448699
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.1704870808
Short name	T43
Test name
Test status
Simulation time	147411750 ps
CPU time	3.41 seconds
Started	Sep 24 02:56:40 PM UTC 24
Finished	Sep 24 02:56:44 PM UTC 24
Peak memory	260692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704870808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1704870808
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.2351807607
Short name	T106
Test name
Test status
Simulation time	788686053815 ps
CPU time	2980.36 seconds
Started	Sep 24 02:56:21 PM UTC 24
Finished	Sep 24 03:46:36 PM UTC 24
Peak memory	295908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351807607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2351807607
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.936780719
Short name	T271
Test name
Test status
Simulation time	19339588119 ps
CPU time	338.83 seconds
Started	Sep 24 02:56:16 PM UTC 24
Finished	Sep 24 03:02:00 PM UTC 24
Peak memory	266276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936780719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.936780719
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.150425385
Short name	T303
Test name
Test status
Simulation time	35356378912 ps
CPU time	2002.96 seconds
Started	Sep 24 02:56:32 PM UTC 24
Finished	Sep 24 03:30:19 PM UTC 24
Peak memory	299472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150425385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.150425385
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.1107100184
Short name	T16
Test name
Test status
Simulation time	31265795 ps
CPU time	8.95 seconds
Started	Sep 24 02:56:05 PM UTC 24
Finished	Sep 24 02:56:15 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107100184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1107100184
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.1583621280
Short name	T8
Test name
Test status
Simulation time	7710291622 ps
CPU time	34.97 seconds
Started	Sep 24 02:56:45 PM UTC 24
Finished	Sep 24 02:57:21 PM UTC 24
Peak memory	297164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583621280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1583621280
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.2579614374
Short name	T45
Test name
Test status
Simulation time	651731854 ps
CPU time	61.9 seconds
Started	Sep 24 02:56:16 PM UTC 24
Finished	Sep 24 02:57:20 PM UTC 24
Peak memory	260436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579614374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2579614374
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.2811248528
Short name	T77
Test name
Test status
Simulation time	1185652841 ps
CPU time	79.95 seconds
Started	Sep 24 02:56:02 PM UTC 24
Finished	Sep 24 02:57:24 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811248528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2811248528
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.4206960238
Short name	T551
Test name
Test status
Simulation time	242946982006 ps
CPU time	3727.38 seconds
Started	Sep 24 02:56:39 PM UTC 24
Finished	Sep 24 03:59:30 PM UTC 24
Peak memory	302116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206960238 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.4206960238
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/2.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.1619637776
Short name	T256
Test name
Test status
Simulation time	38024157627 ps
CPU time	2518.8 seconds
Started	Sep 24 03:27:38 PM UTC 24
Finished	Sep 24 04:10:06 PM UTC 24
Peak memory	302048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619637776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1619637776
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.3404185847
Short name	T478
Test name
Test status
Simulation time	51857226611 ps
CPU time	208.92 seconds
Started	Sep 24 03:27:27 PM UTC 24
Finished	Sep 24 03:30:59 PM UTC 24
Peak memory	262604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404185847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3404185847
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.2381185486
Short name	T475
Test name
Test status
Simulation time	385486101 ps
CPU time	43.41 seconds
Started	Sep 24 03:27:14 PM UTC 24
Finished	Sep 24 03:27:59 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381185486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2381185486
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.2489589711
Short name	T390
Test name
Test status
Simulation time	75180649945 ps
CPU time	1462.55 seconds
Started	Sep 24 03:27:52 PM UTC 24
Finished	Sep 24 03:52:34 PM UTC 24
Peak memory	297428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489589711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2489589711
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.2811314256
Short name	T252
Test name
Test status
Simulation time	127593072936 ps
CPU time	2344.48 seconds
Started	Sep 24 03:28:00 PM UTC 24
Finished	Sep 24 04:07:32 PM UTC 24
Peak memory	295988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811314256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2811314256
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.740197205
Short name	T282
Test name
Test status
Simulation time	13764806294 ps
CPU time	590.34 seconds
Started	Sep 24 03:27:49 PM UTC 24
Finished	Sep 24 03:37:47 PM UTC 24
Peak memory	260892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740197205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.740197205
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.3720247033
Short name	T473
Test name
Test status
Simulation time	428994166 ps
CPU time	45.31 seconds
Started	Sep 24 03:27:01 PM UTC 24
Finished	Sep 24 03:27:48 PM UTC 24
Peak memory	266680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720247033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3720247033
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.80890696
Short name	T471
Test name
Test status
Simulation time	38562130 ps
CPU time	6.58 seconds
Started	Sep 24 03:27:06 PM UTC 24
Finished	Sep 24 03:27:14 PM UTC 24
Peak memory	250188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80890696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.80890696
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.2334690959
Short name	T474
Test name
Test status
Simulation time	359524832 ps
CPU time	19.54 seconds
Started	Sep 24 03:27:30 PM UTC 24
Finished	Sep 24 03:27:51 PM UTC 24
Peak memory	260500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334690959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2334690959
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.1140280580
Short name	T472
Test name
Test status
Simulation time	248120418 ps
CPU time	31.51 seconds
Started	Sep 24 03:26:56 PM UTC 24
Finished	Sep 24 03:27:29 PM UTC 24
Peak memory	266584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140280580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1140280580
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.1545810304
Short name	T689
Test name
Test status
Simulation time	77161542368 ps
CPU time	4362.03 seconds
Started	Sep 24 03:28:19 PM UTC 24
Finished	Sep 24 04:41:56 PM UTC 24
Peak memory	302124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545810304 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.1545810304
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.2428455691
Short name	T319
Test name
Test status
Simulation time	6180527601 ps
CPU time	471.69 seconds
Started	Sep 24 03:29:13 PM UTC 24
Finished	Sep 24 03:37:11 PM UTC 24
Peak memory	277272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2428455691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a lert_handler_stress_all_with_rand_reset.2428455691
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.284865947
Short name	T553
Test name
Test status
Simulation time	13987817875 ps
CPU time	1699.15 seconds
Started	Sep 24 03:31:18 PM UTC 24
Finished	Sep 24 04:00:00 PM UTC 24
Peak memory	299552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284865947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.284865947
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.2534595137
Short name	T485
Test name
Test status
Simulation time	2733636347 ps
CPU time	186.04 seconds
Started	Sep 24 03:31:00 PM UTC 24
Finished	Sep 24 03:34:10 PM UTC 24
Peak memory	266636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534595137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2534595137
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.2468178530
Short name	T479
Test name
Test status
Simulation time	3775256363 ps
CPU time	79.95 seconds
Started	Sep 24 03:30:57 PM UTC 24
Finished	Sep 24 03:32:19 PM UTC 24
Peak memory	266640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468178530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2468178530
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.2287461398
Short name	T573
Test name
Test status
Simulation time	146285485828 ps
CPU time	2028.95 seconds
Started	Sep 24 03:31:40 PM UTC 24
Finished	Sep 24 04:05:53 PM UTC 24
Peak memory	285932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287461398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2287461398
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.3866887500
Short name	T646
Test name
Test status
Simulation time	51067877794 ps
CPU time	3293.75 seconds
Started	Sep 24 03:32:10 PM UTC 24
Finished	Sep 24 04:27:42 PM UTC 24
Peak memory	296180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866887500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3866887500
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.28310777
Short name	T298
Test name
Test status
Simulation time	5549490636 ps
CPU time	260.14 seconds
Started	Sep 24 03:31:38 PM UTC 24
Finished	Sep 24 03:36:03 PM UTC 24
Peak memory	264928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28310777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.28310777
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.169756350
Short name	T103
Test name
Test status
Simulation time	5439581131 ps
CPU time	73.32 seconds
Started	Sep 24 03:30:22 PM UTC 24
Finished	Sep 24 03:31:37 PM UTC 24
Peak memory	266812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169756350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.169756350
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.3221980944
Short name	T477
Test name
Test status
Simulation time	29752257 ps
CPU time	7.25 seconds
Started	Sep 24 03:30:48 PM UTC 24
Finished	Sep 24 03:30:56 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221980944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3221980944
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.2797174373
Short name	T476
Test name
Test status
Simulation time	687235862 ps
CPU time	36.83 seconds
Started	Sep 24 03:30:09 PM UTC 24
Finished	Sep 24 03:30:47 PM UTC 24
Peak memory	260440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797174373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2797174373
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/21.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.3882400887
Short name	T250
Test name
Test status
Simulation time	29963774066 ps
CPU time	1989.87 seconds
Started	Sep 24 03:33:44 PM UTC 24
Finished	Sep 24 04:07:18 PM UTC 24
Peak memory	283092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882400887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3882400887
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.241776518
Short name	T490
Test name
Test status
Simulation time	7526925248 ps
CPU time	148.76 seconds
Started	Sep 24 03:33:18 PM UTC 24
Finished	Sep 24 03:35:50 PM UTC 24
Peak memory	266700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241776518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.241776518
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.584551790
Short name	T483
Test name
Test status
Simulation time	187214459 ps
CPU time	23.2 seconds
Started	Sep 24 03:33:18 PM UTC 24
Finished	Sep 24 03:33:43 PM UTC 24
Peak memory	266836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584551790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.584551790
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.1546105469
Short name	T531
Test name
Test status
Simulation time	12862280166 ps
CPU time	1186.73 seconds
Started	Sep 24 03:34:11 PM UTC 24
Finished	Sep 24 03:54:13 PM UTC 24
Peak memory	299556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546105469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1546105469
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.3386544476
Short name	T359
Test name
Test status
Simulation time	56714591093 ps
CPU time	620.96 seconds
Started	Sep 24 03:33:47 PM UTC 24
Finished	Sep 24 03:44:16 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386544476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3386544476
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.2126403058
Short name	T481
Test name
Test status
Simulation time	978937799 ps
CPU time	24.38 seconds
Started	Sep 24 03:32:52 PM UTC 24
Finished	Sep 24 03:33:17 PM UTC 24
Peak memory	266680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126403058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2126403058
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.2264798323
Short name	T484
Test name
Test status
Simulation time	334362425 ps
CPU time	50.67 seconds
Started	Sep 24 03:32:55 PM UTC 24
Finished	Sep 24 03:33:48 PM UTC 24
Peak memory	266680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264798323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2264798323
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.676613003
Short name	T482
Test name
Test status
Simulation time	4228369095 ps
CPU time	28.4 seconds
Started	Sep 24 03:32:48 PM UTC 24
Finished	Sep 24 03:33:18 PM UTC 24
Peak memory	266716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676613003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.676613003
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.2364719650
Short name	T575
Test name
Test status
Simulation time	18383291454 ps
CPU time	1894.88 seconds
Started	Sep 24 03:34:13 PM UTC 24
Finished	Sep 24 04:06:11 PM UTC 24
Peak memory	299548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364719650 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.2364719650
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/22.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.3308390085
Short name	T141
Test name
Test status
Simulation time	112918920284 ps
CPU time	1757.74 seconds
Started	Sep 24 03:35:35 PM UTC 24
Finished	Sep 24 04:05:12 PM UTC 24
Peak memory	283092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308390085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3308390085
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.2612328852
Short name	T493
Test name
Test status
Simulation time	1076446274 ps
CPU time	142.51 seconds
Started	Sep 24 03:35:26 PM UTC 24
Finished	Sep 24 03:37:51 PM UTC 24
Peak memory	266568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612328852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2612328852
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.2204504912
Short name	T489
Test name
Test status
Simulation time	177058804 ps
CPU time	21.1 seconds
Started	Sep 24 03:35:19 PM UTC 24
Finished	Sep 24 03:35:41 PM UTC 24
Peak memory	260432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204504912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2204504912
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.186285095
Short name	T385
Test name
Test status
Simulation time	43031999338 ps
CPU time	671.76 seconds
Started	Sep 24 03:35:50 PM UTC 24
Finished	Sep 24 03:47:11 PM UTC 24
Peak memory	283160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186285095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.186285095
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.457464522
Short name	T537
Test name
Test status
Simulation time	17150491119 ps
CPU time	1158.15 seconds
Started	Sep 24 03:36:03 PM UTC 24
Finished	Sep 24 03:55:37 PM UTC 24
Peak memory	299740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457464522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.457464522
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.745252178
Short name	T366
Test name
Test status
Simulation time	5676486753 ps
CPU time	184.49 seconds
Started	Sep 24 03:35:42 PM UTC 24
Finished	Sep 24 03:38:50 PM UTC 24
Peak memory	260636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745252178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.745252178
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.3630734008
Short name	T488
Test name
Test status
Simulation time	404184971 ps
CPU time	43.36 seconds
Started	Sep 24 03:34:49 PM UTC 24
Finished	Sep 24 03:35:34 PM UTC 24
Peak memory	266680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630734008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3630734008
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.2154899224
Short name	T284
Test name
Test status
Simulation time	104997874 ps
CPU time	13.51 seconds
Started	Sep 24 03:35:03 PM UTC 24
Finished	Sep 24 03:35:18 PM UTC 24
Peak memory	260728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154899224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2154899224
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.1682625002
Short name	T491
Test name
Test status
Simulation time	850019509 ps
CPU time	66.26 seconds
Started	Sep 24 03:35:34 PM UTC 24
Finished	Sep 24 03:36:42 PM UTC 24
Peak memory	266572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682625002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1682625002
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.2660264107
Short name	T487
Test name
Test status
Simulation time	1493895551 ps
CPU time	65.1 seconds
Started	Sep 24 03:34:26 PM UTC 24
Finished	Sep 24 03:35:33 PM UTC 24
Peak memory	260512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660264107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2660264107
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.1974005433
Short name	T682
Test name
Test status
Simulation time	234417847334 ps
CPU time	3567.53 seconds
Started	Sep 24 03:36:43 PM UTC 24
Finished	Sep 24 04:36:54 PM UTC 24
Peak memory	302048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974005433 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.1974005433
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/23.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.746771779
Short name	T586
Test name
Test status
Simulation time	25445256584 ps
CPU time	1988.79 seconds
Started	Sep 24 03:37:58 PM UTC 24
Finished	Sep 24 04:11:30 PM UTC 24
Peak memory	285748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746771779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.746771779
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.268831555
Short name	T498
Test name
Test status
Simulation time	7211358112 ps
CPU time	192.12 seconds
Started	Sep 24 03:37:52 PM UTC 24
Finished	Sep 24 03:41:08 PM UTC 24
Peak memory	266804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268831555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.268831555
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.3508635879
Short name	T496
Test name
Test status
Simulation time	1723426345 ps
CPU time	40.49 seconds
Started	Sep 24 03:37:48 PM UTC 24
Finished	Sep 24 03:38:30 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508635879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3508635879
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.3586989769
Short name	T386
Test name
Test status
Simulation time	19821870805 ps
CPU time	1916.69 seconds
Started	Sep 24 03:38:35 PM UTC 24
Finished	Sep 24 04:10:56 PM UTC 24
Peak memory	299476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586989769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3586989769
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.1436386575
Short name	T523
Test name
Test status
Simulation time	21342398682 ps
CPU time	758.35 seconds
Started	Sep 24 03:38:51 PM UTC 24
Finished	Sep 24 03:51:39 PM UTC 24
Peak memory	283364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436386575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1436386575
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.2325925863
Short name	T494
Test name
Test status
Simulation time	330630236 ps
CPU time	25.05 seconds
Started	Sep 24 03:37:28 PM UTC 24
Finished	Sep 24 03:37:54 PM UTC 24
Peak memory	266608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325925863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2325925863
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.2160749690
Short name	T495
Test name
Test status
Simulation time	119363255 ps
CPU time	18.08 seconds
Started	Sep 24 03:37:38 PM UTC 24
Finished	Sep 24 03:37:57 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160749690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2160749690
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.3037424209
Short name	T497
Test name
Test status
Simulation time	1272463488 ps
CPU time	36.73 seconds
Started	Sep 24 03:37:55 PM UTC 24
Finished	Sep 24 03:38:34 PM UTC 24
Peak memory	266836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037424209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3037424209
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.4142956907
Short name	T492
Test name
Test status
Simulation time	61697721 ps
CPU time	5.28 seconds
Started	Sep 24 03:37:20 PM UTC 24
Finished	Sep 24 03:37:27 PM UTC 24
Peak memory	262752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142956907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.4142956907
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.1182793417
Short name	T39
Test name
Test status
Simulation time	18432393851 ps
CPU time	1947.91 seconds
Started	Sep 24 03:38:58 PM UTC 24
Finished	Sep 24 04:11:52 PM UTC 24
Peak memory	299488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182793417 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.1182793417
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/24.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.1657633307
Short name	T65
Test name
Test status
Simulation time	35809699743 ps
CPU time	1702.98 seconds
Started	Sep 24 03:41:52 PM UTC 24
Finished	Sep 24 04:10:36 PM UTC 24
Peak memory	283164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657633307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1657633307
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.2523424690
Short name	T508
Test name
Test status
Simulation time	7591572681 ps
CPU time	263.41 seconds
Started	Sep 24 03:41:37 PM UTC 24
Finished	Sep 24 03:46:05 PM UTC 24
Peak memory	266772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523424690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2523424690
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.2423998704
Short name	T501
Test name
Test status
Simulation time	41207589 ps
CPU time	6.34 seconds
Started	Sep 24 03:41:34 PM UTC 24
Finished	Sep 24 03:41:42 PM UTC 24
Peak memory	260432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423998704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2423998704
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.2057518719
Short name	T379
Test name
Test status
Simulation time	63344366725 ps
CPU time	1423.95 seconds
Started	Sep 24 03:42:14 PM UTC 24
Finished	Sep 24 04:06:16 PM UTC 24
Peak memory	299548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057518719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2057518719
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.1501006216
Short name	T260
Test name
Test status
Simulation time	89124859055 ps
CPU time	1820.43 seconds
Started	Sep 24 03:42:24 PM UTC 24
Finished	Sep 24 04:13:07 PM UTC 24
Peak memory	298896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501006216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1501006216
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.648132297
Short name	T500
Test name
Test status
Simulation time	150732800 ps
CPU time	24.98 seconds
Started	Sep 24 03:41:10 PM UTC 24
Finished	Sep 24 03:41:36 PM UTC 24
Peak memory	266612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648132297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.648132297
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.3575993866
Short name	T131
Test name
Test status
Simulation time	519272009 ps
CPU time	32.42 seconds
Started	Sep 24 03:41:18 PM UTC 24
Finished	Sep 24 03:41:52 PM UTC 24
Peak memory	266872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575993866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3575993866
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.854637959
Short name	T283
Test name
Test status
Simulation time	1047131942 ps
CPU time	29.56 seconds
Started	Sep 24 03:41:42 PM UTC 24
Finished	Sep 24 03:42:13 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854637959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.854637959
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.956092863
Short name	T499
Test name
Test status
Simulation time	231298157 ps
CPU time	37.82 seconds
Started	Sep 24 03:40:54 PM UTC 24
Finished	Sep 24 03:41:33 PM UTC 24
Peak memory	266580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956092863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.956092863
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all_with_rand_reset.901744490
Short name	T124
Test name
Test status
Simulation time	74973649911 ps
CPU time	345.82 seconds
Started	Sep 24 03:43:07 PM UTC 24
Finished	Sep 24 03:48:58 PM UTC 24
Peak memory	279120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=901744490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.al ert_handler_stress_all_with_rand_reset.901744490
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.3965165956
Short name	T678
Test name
Test status
Simulation time	76855943888 ps
CPU time	2919.73 seconds
Started	Sep 24 03:44:17 PM UTC 24
Finished	Sep 24 04:33:30 PM UTC 24
Peak memory	302380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965165956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3965165956
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.575842909
Short name	T509
Test name
Test status
Simulation time	1648754452 ps
CPU time	145.27 seconds
Started	Sep 24 03:44:14 PM UTC 24
Finished	Sep 24 03:46:42 PM UTC 24
Peak memory	266676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575842909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.575842909
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.2694537203
Short name	T507
Test name
Test status
Simulation time	495830546 ps
CPU time	44.81 seconds
Started	Sep 24 03:44:13 PM UTC 24
Finished	Sep 24 03:45:00 PM UTC 24
Peak memory	260440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694537203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2694537203
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.2023751656
Short name	T381
Test name
Test status
Simulation time	31825761445 ps
CPU time	1962.07 seconds
Started	Sep 24 03:44:49 PM UTC 24
Finished	Sep 24 04:17:54 PM UTC 24
Peak memory	297956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023751656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2023751656
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.322121984
Short name	T550
Test name
Test status
Simulation time	6853560103 ps
CPU time	853.55 seconds
Started	Sep 24 03:44:57 PM UTC 24
Finished	Sep 24 03:59:22 PM UTC 24
Peak memory	283092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322121984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.322121984
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.3459298625
Short name	T369
Test name
Test status
Simulation time	50247540007 ps
CPU time	646.77 seconds
Started	Sep 24 03:44:28 PM UTC 24
Finished	Sep 24 03:55:24 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459298625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3459298625
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.469108968
Short name	T505
Test name
Test status
Simulation time	706510981 ps
CPU time	42.45 seconds
Started	Sep 24 03:43:29 PM UTC 24
Finished	Sep 24 03:44:14 PM UTC 24
Peak memory	266684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469108968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.469108968
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.2273542434
Short name	T504
Test name
Test status
Simulation time	4037311341 ps
CPU time	31.47 seconds
Started	Sep 24 03:43:40 PM UTC 24
Finished	Sep 24 03:44:13 PM UTC 24
Peak memory	260792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273542434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2273542434
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.2675368415
Short name	T273
Test name
Test status
Simulation time	265837783 ps
CPU time	48.77 seconds
Started	Sep 24 03:44:14 PM UTC 24
Finished	Sep 24 03:45:05 PM UTC 24
Peak memory	260428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675368415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2675368415
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.2265754091
Short name	T506
Test name
Test status
Simulation time	934471672 ps
CPU time	87.4 seconds
Started	Sep 24 03:43:27 PM UTC 24
Finished	Sep 24 03:44:57 PM UTC 24
Peak memory	266656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265754091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2265754091
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.1078568066
Short name	T321
Test name
Test status
Simulation time	13183464801 ps
CPU time	785.84 seconds
Started	Sep 24 03:45:00 PM UTC 24
Finished	Sep 24 03:58:16 PM UTC 24
Peak memory	276944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078568066 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.1078568066
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.4169879429
Short name	T64
Test name
Test status
Simulation time	5906992766 ps
CPU time	215.69 seconds
Started	Sep 24 03:45:06 PM UTC 24
Finished	Sep 24 03:48:45 PM UTC 24
Peak memory	277336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4169879429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.a lert_handler_stress_all_with_rand_reset.4169879429
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.963773258
Short name	T133
Test name
Test status
Simulation time	34029971268 ps
CPU time	2295.01 seconds
Started	Sep 24 03:47:21 PM UTC 24
Finished	Sep 24 04:26:03 PM UTC 24
Peak memory	286000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963773258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.963773258
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.3568243152
Short name	T514
Test name
Test status
Simulation time	3674104064 ps
CPU time	76.92 seconds
Started	Sep 24 03:47:13 PM UTC 24
Finished	Sep 24 03:48:32 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568243152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3568243152
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.2994108247
Short name	T513
Test name
Test status
Simulation time	4530979754 ps
CPU time	71.41 seconds
Started	Sep 24 03:47:09 PM UTC 24
Finished	Sep 24 03:48:22 PM UTC 24
Peak memory	260560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994108247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2994108247
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.1329345810
Short name	T262
Test name
Test status
Simulation time	43989757444 ps
CPU time	1548.68 seconds
Started	Sep 24 03:48:13 PM UTC 24
Finished	Sep 24 04:14:22 PM UTC 24
Peak memory	277028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329345810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1329345810
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.3781151282
Short name	T354
Test name
Test status
Simulation time	4362258297 ps
CPU time	149 seconds
Started	Sep 24 03:47:53 PM UTC 24
Finished	Sep 24 03:50:25 PM UTC 24
Peak memory	260708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781151282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3781151282
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.3457218833
Short name	T512
Test name
Test status
Simulation time	759851537 ps
CPU time	75.74 seconds
Started	Sep 24 03:46:39 PM UTC 24
Finished	Sep 24 03:47:57 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457218833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3457218833
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.3163572839
Short name	T279
Test name
Test status
Simulation time	268652893 ps
CPU time	26.5 seconds
Started	Sep 24 03:46:43 PM UTC 24
Finished	Sep 24 03:47:11 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163572839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3163572839
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.3485243002
Short name	T63
Test name
Test status
Simulation time	4417112965 ps
CPU time	56.8 seconds
Started	Sep 24 03:47:13 PM UTC 24
Finished	Sep 24 03:48:11 PM UTC 24
Peak memory	266700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485243002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3485243002
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.1431815323
Short name	T510
Test name
Test status
Simulation time	601071690 ps
CPU time	59.73 seconds
Started	Sep 24 03:46:06 PM UTC 24
Finished	Sep 24 03:47:08 PM UTC 24
Peak memory	266584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431815323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1431815323
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.1721734464
Short name	T264
Test name
Test status
Simulation time	47736943100 ps
CPU time	1552 seconds
Started	Sep 24 03:48:14 PM UTC 24
Finished	Sep 24 04:14:27 PM UTC 24
Peak memory	293328 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721734464 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.1721734464
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all_with_rand_reset.581339379
Short name	T288
Test name
Test status
Simulation time	19389141686 ps
CPU time	415.52 seconds
Started	Sep 24 03:48:18 PM UTC 24
Finished	Sep 24 03:55:20 PM UTC 24
Peak memory	283288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=581339379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.al ert_handler_stress_all_with_rand_reset.581339379
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.2621179588
Short name	T257
Test name
Test status
Simulation time	10914476017 ps
CPU time	1273.22 seconds
Started	Sep 24 03:49:00 PM UTC 24
Finished	Sep 24 04:10:29 PM UTC 24
Peak memory	295452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621179588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2621179588
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.1748382190
Short name	T518
Test name
Test status
Simulation time	433179066 ps
CPU time	15.42 seconds
Started	Sep 24 03:48:48 PM UTC 24
Finished	Sep 24 03:49:05 PM UTC 24
Peak memory	266568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748382190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1748382190
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.4261760586
Short name	T519
Test name
Test status
Simulation time	803832621 ps
CPU time	62.31 seconds
Started	Sep 24 03:48:46 PM UTC 24
Finished	Sep 24 03:49:50 PM UTC 24
Peak memory	266648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261760586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.4261760586
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.4012623688
Short name	T641
Test name
Test status
Simulation time	35516499485 ps
CPU time	2248.51 seconds
Started	Sep 24 03:49:07 PM UTC 24
Finished	Sep 24 04:27:02 PM UTC 24
Peak memory	285996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012623688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.4012623688
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.3524709967
Short name	T634
Test name
Test status
Simulation time	147674554943 ps
CPU time	2168.73 seconds
Started	Sep 24 03:49:24 PM UTC 24
Finished	Sep 24 04:25:59 PM UTC 24
Peak memory	286004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524709967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3524709967
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.1632976196
Short name	T516
Test name
Test status
Simulation time	178418415 ps
CPU time	18.07 seconds
Started	Sep 24 03:48:33 PM UTC 24
Finished	Sep 24 03:48:52 PM UTC 24
Peak memory	260728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632976196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1632976196
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.1056192429
Short name	T108
Test name
Test status
Simulation time	2584512487 ps
CPU time	115.11 seconds
Started	Sep 24 03:48:33 PM UTC 24
Finished	Sep 24 03:50:30 PM UTC 24
Peak memory	266744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056192429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1056192429
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.1706048845
Short name	T325
Test name
Test status
Simulation time	821121744 ps
CPU time	29.54 seconds
Started	Sep 24 03:48:53 PM UTC 24
Finished	Sep 24 03:49:24 PM UTC 24
Peak memory	260428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706048845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1706048845
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.2066544691
Short name	T515
Test name
Test status
Simulation time	104541380 ps
CPU time	7.41 seconds
Started	Sep 24 03:48:23 PM UTC 24
Finished	Sep 24 03:48:32 PM UTC 24
Peak memory	262560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066544691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2066544691
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.2996917898
Short name	T608
Test name
Test status
Simulation time	20947119997 ps
CPU time	1858.88 seconds
Started	Sep 24 03:49:28 PM UTC 24
Finished	Sep 24 04:20:50 PM UTC 24
Peak memory	283164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996917898 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.2996917898
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all_with_rand_reset.1700550050
Short name	T539
Test name
Test status
Simulation time	8394394024 ps
CPU time	354.67 seconds
Started	Sep 24 03:49:51 PM UTC 24
Finished	Sep 24 03:55:52 PM UTC 24
Peak memory	277144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1700550050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.a lert_handler_stress_all_with_rand_reset.1700550050
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.1989497476
Short name	T609
Test name
Test status
Simulation time	115520222333 ps
CPU time	1774.66 seconds
Started	Sep 24 03:51:10 PM UTC 24
Finished	Sep 24 04:21:06 PM UTC 24
Peak memory	283088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989497476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1989497476
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.1543612652
Short name	T530
Test name
Test status
Simulation time	19154996914 ps
CPU time	188.85 seconds
Started	Sep 24 03:50:59 PM UTC 24
Finished	Sep 24 03:54:11 PM UTC 24
Peak memory	267028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543612652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1543612652
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.3816468017
Short name	T323
Test name
Test status
Simulation time	527974409 ps
CPU time	30.29 seconds
Started	Sep 24 03:50:50 PM UTC 24
Finished	Sep 24 03:51:22 PM UTC 24
Peak memory	266576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816468017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3816468017
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.3362348798
Short name	T391
Test name
Test status
Simulation time	61133535409 ps
CPU time	2161.64 seconds
Started	Sep 24 03:51:25 PM UTC 24
Finished	Sep 24 04:27:53 PM UTC 24
Peak memory	300268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362348798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3362348798
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.2527033347
Short name	T594
Test name
Test status
Simulation time	50918083286 ps
CPU time	1462.95 seconds
Started	Sep 24 03:51:25 PM UTC 24
Finished	Sep 24 04:16:07 PM UTC 24
Peak memory	283100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527033347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2527033347
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.2337271778
Short name	T362
Test name
Test status
Simulation time	54575642995 ps
CPU time	691.65 seconds
Started	Sep 24 03:51:23 PM UTC 24
Finished	Sep 24 04:03:03 PM UTC 24
Peak memory	266712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337271778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2337271778
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.2982077640
Short name	T522
Test name
Test status
Simulation time	708244095 ps
CPU time	48.87 seconds
Started	Sep 24 03:50:32 PM UTC 24
Finished	Sep 24 03:51:22 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982077640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2982077640
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.2185975522
Short name	T294
Test name
Test status
Simulation time	2300370908 ps
CPU time	65.16 seconds
Started	Sep 24 03:50:44 PM UTC 24
Finished	Sep 24 03:51:51 PM UTC 24
Peak memory	266672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185975522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2185975522
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.1064557974
Short name	T125
Test name
Test status
Simulation time	8553085338 ps
CPU time	60.26 seconds
Started	Sep 24 03:51:01 PM UTC 24
Finished	Sep 24 03:52:03 PM UTC 24
Peak memory	266700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064557974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1064557974
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.4048885856
Short name	T296
Test name
Test status
Simulation time	159254559 ps
CPU time	22.63 seconds
Started	Sep 24 03:50:26 PM UTC 24
Finished	Sep 24 03:50:50 PM UTC 24
Peak memory	266584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048885856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.4048885856
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.986926468
Short name	T309
Test name
Test status
Simulation time	67123266548 ps
CPU time	1747.38 seconds
Started	Sep 24 03:51:42 PM UTC 24
Finished	Sep 24 04:21:09 PM UTC 24
Peak memory	313876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986926468 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.986926468
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all_with_rand_reset.2999915350
Short name	T130
Test name
Test status
Simulation time	5417515613 ps
CPU time	470.1 seconds
Started	Sep 24 03:51:52 PM UTC 24
Finished	Sep 24 03:59:49 PM UTC 24
Peak memory	281240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2999915350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.a lert_handler_stress_all_with_rand_reset.2999915350
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.3454591215
Short name	T46
Test name
Test status
Simulation time	43047812 ps
CPU time	3.91 seconds
Started	Sep 24 02:57:23 PM UTC 24
Finished	Sep 24 02:57:28 PM UTC 24
Peak memory	260696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454591215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3454591215
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.3988636787
Short name	T467
Test name
Test status
Simulation time	55876338626 ps
CPU time	1699.99 seconds
Started	Sep 24 02:57:01 PM UTC 24
Finished	Sep 24 03:25:42 PM UTC 24
Peak memory	299748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988636787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3988636787
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.3217292875
Short name	T21
Test name
Test status
Simulation time	1370006272 ps
CPU time	67.21 seconds
Started	Sep 24 02:57:16 PM UTC 24
Finished	Sep 24 02:58:25 PM UTC 24
Peak memory	260700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217292875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3217292875
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.722554490
Short name	T51
Test name
Test status
Simulation time	21068896316 ps
CPU time	149.82 seconds
Started	Sep 24 02:56:54 PM UTC 24
Finished	Sep 24 02:59:27 PM UTC 24
Peak memory	266708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722554490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.722554490
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.3094709247
Short name	T78
Test name
Test status
Simulation time	319697594 ps
CPU time	44.05 seconds
Started	Sep 24 02:56:53 PM UTC 24
Finished	Sep 24 02:57:39 PM UTC 24
Peak memory	260792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094709247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3094709247
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.154783293
Short name	T329
Test name
Test status
Simulation time	10065531986 ps
CPU time	936.44 seconds
Started	Sep 24 02:57:06 PM UTC 24
Finished	Sep 24 03:12:54 PM UTC 24
Peak memory	283348 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154783293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.154783293
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.1420875992
Short name	T470
Test name
Test status
Simulation time	34107293925 ps
CPU time	1774.69 seconds
Started	Sep 24 02:57:07 PM UTC 24
Finished	Sep 24 03:27:04 PM UTC 24
Peak memory	297696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420875992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1420875992
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.1687265097
Short name	T17
Test name
Test status
Simulation time	3323174081 ps
CPU time	62.44 seconds
Started	Sep 24 02:57:06 PM UTC 24
Finished	Sep 24 02:58:10 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687265097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1687265097
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.3018415880
Short name	T241
Test name
Test status
Simulation time	1106862689 ps
CPU time	98.59 seconds
Started	Sep 24 02:56:45 PM UTC 24
Finished	Sep 24 02:58:26 PM UTC 24
Peak memory	266876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018415880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3018415880
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.5037537
Short name	T20
Test name
Test status
Simulation time	373082331 ps
CPU time	60.85 seconds
Started	Sep 24 02:56:52 PM UTC 24
Finished	Sep 24 02:57:55 PM UTC 24
Peak memory	260728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5037537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_rand om_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.5037537
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.671427353
Short name	T67
Test name
Test status
Simulation time	144948331 ps
CPU time	18.49 seconds
Started	Sep 24 02:56:45 PM UTC 24
Finished	Sep 24 02:57:05 PM UTC 24
Peak memory	260696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671427353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.671427353
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.155562714
Short name	T83
Test name
Test status
Simulation time	186612659 ps
CPU time	12.32 seconds
Started	Sep 24 02:57:20 PM UTC 24
Finished	Sep 24 02:57:34 PM UTC 24
Peak memory	266844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155562714 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.155562714
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all_with_rand_reset.176666857
Short name	T101
Test name
Test status
Simulation time	21821564892 ps
CPU time	510.38 seconds
Started	Sep 24 02:57:26 PM UTC 24
Finished	Sep 24 03:06:04 PM UTC 24
Peak memory	279120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=176666857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.ale rt_handler_stress_all_with_rand_reset.176666857
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.3241334291
Short name	T606
Test name
Test status
Simulation time	49832180060 ps
CPU time	1651.41 seconds
Started	Sep 24 03:52:56 PM UTC 24
Finished	Sep 24 04:20:48 PM UTC 24
Peak memory	299476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241334291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3241334291
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.3119525173
Short name	T546
Test name
Test status
Simulation time	4412213217 ps
CPU time	298.56 seconds
Started	Sep 24 03:52:41 PM UTC 24
Finished	Sep 24 03:57:45 PM UTC 24
Peak memory	266704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119525173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3119525173
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.551819227
Short name	T526
Test name
Test status
Simulation time	165527529 ps
CPU time	18.73 seconds
Started	Sep 24 03:52:37 PM UTC 24
Finished	Sep 24 03:52:57 PM UTC 24
Peak memory	260692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551819227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.551819227
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.1198517078
Short name	T388
Test name
Test status
Simulation time	67483541826 ps
CPU time	1588.93 seconds
Started	Sep 24 03:52:59 PM UTC 24
Finished	Sep 24 04:19:48 PM UTC 24
Peak memory	299476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198517078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1198517078
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.3328664874
Short name	T700
Test name
Test status
Simulation time	52738045201 ps
CPU time	3221.86 seconds
Started	Sep 24 03:53:30 PM UTC 24
Finished	Sep 24 04:47:50 PM UTC 24
Peak memory	302056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328664874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3328664874
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.3454145941
Short name	T361
Test name
Test status
Simulation time	9254015523 ps
CPU time	354.14 seconds
Started	Sep 24 03:52:58 PM UTC 24
Finished	Sep 24 03:58:57 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454145941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3454145941
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.209824003
Short name	T525
Test name
Test status
Simulation time	909662428 ps
CPU time	42.28 seconds
Started	Sep 24 03:52:11 PM UTC 24
Finished	Sep 24 03:52:55 PM UTC 24
Peak memory	260436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209824003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.209824003
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.1365940878
Short name	T527
Test name
Test status
Simulation time	364144909 ps
CPU time	38.19 seconds
Started	Sep 24 03:52:18 PM UTC 24
Finished	Sep 24 03:52:57 PM UTC 24
Peak memory	266680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365940878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1365940878
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.2190753404
Short name	T528
Test name
Test status
Simulation time	315974685 ps
CPU time	36.67 seconds
Started	Sep 24 03:52:51 PM UTC 24
Finished	Sep 24 03:53:29 PM UTC 24
Peak memory	260500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190753404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2190753404
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.2062958029
Short name	T524
Test name
Test status
Simulation time	272064608 ps
CPU time	4.29 seconds
Started	Sep 24 03:52:05 PM UTC 24
Finished	Sep 24 03:52:10 PM UTC 24
Peak memory	260512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062958029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2062958029
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/30.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.1775247909
Short name	T642
Test name
Test status
Simulation time	25599100573 ps
CPU time	1922.97 seconds
Started	Sep 24 03:54:43 PM UTC 24
Finished	Sep 24 04:27:09 PM UTC 24
Peak memory	284488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775247909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1775247909
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.2221745375
Short name	T540
Test name
Test status
Simulation time	19608647009 ps
CPU time	137.56 seconds
Started	Sep 24 03:54:24 PM UTC 24
Finished	Sep 24 03:56:44 PM UTC 24
Peak memory	260556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221745375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2221745375
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.1127845375
Short name	T532
Test name
Test status
Simulation time	143847113 ps
CPU time	13.82 seconds
Started	Sep 24 03:54:16 PM UTC 24
Finished	Sep 24 03:54:31 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127845375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1127845375
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.4265246568
Short name	T705
Test name
Test status
Simulation time	57490587820 ps
CPU time	3310.28 seconds
Started	Sep 24 03:55:21 PM UTC 24
Finished	Sep 24 04:51:09 PM UTC 24
Peak memory	302052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265246568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.4265246568
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.2279199847
Short name	T652
Test name
Test status
Simulation time	119363631730 ps
CPU time	2007.06 seconds
Started	Sep 24 03:55:24 PM UTC 24
Finished	Sep 24 04:29:15 PM UTC 24
Peak memory	283100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279199847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2279199847
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.1746207959
Short name	T533
Test name
Test status
Simulation time	1821845392 ps
CPU time	34.91 seconds
Started	Sep 24 03:54:06 PM UTC 24
Finished	Sep 24 03:54:42 PM UTC 24
Peak memory	266608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746207959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1746207959
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.3118314505
Short name	T534
Test name
Test status
Simulation time	776035139 ps
CPU time	50.23 seconds
Started	Sep 24 03:54:12 PM UTC 24
Finished	Sep 24 03:55:04 PM UTC 24
Peak memory	260728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118314505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3118314505
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.2778447371
Short name	T538
Test name
Test status
Simulation time	684936242 ps
CPU time	69.15 seconds
Started	Sep 24 03:54:32 PM UTC 24
Finished	Sep 24 03:55:43 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778447371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2778447371
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.1698611804
Short name	T536
Test name
Test status
Simulation time	3067697847 ps
CPU time	96.84 seconds
Started	Sep 24 03:53:54 PM UTC 24
Finished	Sep 24 03:55:33 PM UTC 24
Peak memory	266648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698611804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1698611804
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.1382566933
Short name	T320
Test name
Test status
Simulation time	28084391541 ps
CPU time	2126.21 seconds
Started	Sep 24 03:55:25 PM UTC 24
Finished	Sep 24 04:31:17 PM UTC 24
Peak memory	318432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382566933 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.1382566933
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all_with_rand_reset.2310976460
Short name	T317
Test name
Test status
Simulation time	17536119586 ps
CPU time	583.91 seconds
Started	Sep 24 03:55:34 PM UTC 24
Finished	Sep 24 04:05:26 PM UTC 24
Peak memory	283216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2310976460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.a lert_handler_stress_all_with_rand_reset.2310976460
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.2320896703
Short name	T633
Test name
Test status
Simulation time	15611266403 ps
CPU time	1686.63 seconds
Started	Sep 24 03:57:10 PM UTC 24
Finished	Sep 24 04:25:38 PM UTC 24
Peak memory	299472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320896703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2320896703
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.3865038499
Short name	T552
Test name
Test status
Simulation time	8453656129 ps
CPU time	171.11 seconds
Started	Sep 24 03:56:53 PM UTC 24
Finished	Sep 24 03:59:47 PM UTC 24
Peak memory	266964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865038499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3865038499
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.3885655206
Short name	T543
Test name
Test status
Simulation time	2905939430 ps
CPU time	21.04 seconds
Started	Sep 24 03:56:46 PM UTC 24
Finished	Sep 24 03:57:08 PM UTC 24
Peak memory	266904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885655206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3885655206
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.1116588747
Short name	T600
Test name
Test status
Simulation time	13494401291 ps
CPU time	1217.07 seconds
Started	Sep 24 03:57:16 PM UTC 24
Finished	Sep 24 04:17:49 PM UTC 24
Peak memory	299736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116588747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1116588747
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.3503544401
Short name	T631
Test name
Test status
Simulation time	42465113794 ps
CPU time	1661.41 seconds
Started	Sep 24 03:57:29 PM UTC 24
Finished	Sep 24 04:25:31 PM UTC 24
Peak memory	283172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503544401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3503544401
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.2049002225
Short name	T370
Test name
Test status
Simulation time	12705591500 ps
CPU time	309.71 seconds
Started	Sep 24 03:57:15 PM UTC 24
Finished	Sep 24 04:02:29 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049002225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2049002225
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.371219103
Short name	T541
Test name
Test status
Simulation time	2778230240 ps
CPU time	65.99 seconds
Started	Sep 24 03:55:44 PM UTC 24
Finished	Sep 24 03:56:52 PM UTC 24
Peak memory	266640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371219103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.371219103
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.1433679074
Short name	T542
Test name
Test status
Simulation time	3019219354 ps
CPU time	67.14 seconds
Started	Sep 24 03:55:52 PM UTC 24
Finished	Sep 24 03:57:01 PM UTC 24
Peak memory	266872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433679074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1433679074
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.4262747786
Short name	T545
Test name
Test status
Simulation time	212013395 ps
CPU time	23.52 seconds
Started	Sep 24 03:57:02 PM UTC 24
Finished	Sep 24 03:57:28 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262747786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4262747786
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.2840720489
Short name	T544
Test name
Test status
Simulation time	1087412087 ps
CPU time	92.88 seconds
Started	Sep 24 03:55:39 PM UTC 24
Finished	Sep 24 03:57:14 PM UTC 24
Peak memory	266584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840720489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2840720489
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.4178979581
Short name	T559
Test name
Test status
Simulation time	10971499538 ps
CPU time	208.43 seconds
Started	Sep 24 03:57:46 PM UTC 24
Finished	Sep 24 04:01:18 PM UTC 24
Peak memory	266780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178979581 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.4178979581
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/32.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.2113334306
Short name	T614
Test name
Test status
Simulation time	145219895821 ps
CPU time	1339.95 seconds
Started	Sep 24 03:59:34 PM UTC 24
Finished	Sep 24 04:22:11 PM UTC 24
Peak memory	277020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113334306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2113334306
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.287480936
Short name	T555
Test name
Test status
Simulation time	5258587619 ps
CPU time	75.96 seconds
Started	Sep 24 03:59:10 PM UTC 24
Finished	Sep 24 04:00:28 PM UTC 24
Peak memory	267060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287480936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.287480936
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.2433151984
Short name	T324
Test name
Test status
Simulation time	640845170 ps
CPU time	49.48 seconds
Started	Sep 24 03:59:09 PM UTC 24
Finished	Sep 24 04:00:00 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433151984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2433151984
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.2292348830
Short name	T392
Test name
Test status
Simulation time	72712850818 ps
CPU time	1755.82 seconds
Started	Sep 24 03:59:49 PM UTC 24
Finished	Sep 24 04:29:26 PM UTC 24
Peak memory	299484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292348830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2292348830
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.2485830273
Short name	T676
Test name
Test status
Simulation time	217066578107 ps
CPU time	1981.05 seconds
Started	Sep 24 03:59:51 PM UTC 24
Finished	Sep 24 04:33:17 PM UTC 24
Peak memory	281652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485830273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2485830273
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.3447495686
Short name	T350
Test name
Test status
Simulation time	7084922178 ps
CPU time	102.45 seconds
Started	Sep 24 03:59:37 PM UTC 24
Finished	Sep 24 04:01:21 PM UTC 24
Peak memory	260572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447495686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3447495686
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.1072290923
Short name	T548
Test name
Test status
Simulation time	282649162 ps
CPU time	24.79 seconds
Started	Sep 24 03:58:41 PM UTC 24
Finished	Sep 24 03:59:08 PM UTC 24
Peak memory	260792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072290923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1072290923
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.4041977546
Short name	T549
Test name
Test status
Simulation time	98020402 ps
CPU time	10.87 seconds
Started	Sep 24 03:58:58 PM UTC 24
Finished	Sep 24 03:59:10 PM UTC 24
Peak memory	260724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041977546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.4041977546
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.1744704422
Short name	T554
Test name
Test status
Simulation time	537531383 ps
CPU time	42.55 seconds
Started	Sep 24 03:59:25 PM UTC 24
Finished	Sep 24 04:00:09 PM UTC 24
Peak memory	260428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744704422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1744704422
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.2803799688
Short name	T547
Test name
Test status
Simulation time	1758613781 ps
CPU time	21.33 seconds
Started	Sep 24 03:58:18 PM UTC 24
Finished	Sep 24 03:58:41 PM UTC 24
Peak memory	266912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803799688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2803799688
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.237058781
Short name	T692
Test name
Test status
Simulation time	143458205158 ps
CPU time	2580.33 seconds
Started	Sep 24 04:00:04 PM UTC 24
Finished	Sep 24 04:43:37 PM UTC 24
Peak memory	302040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237058781 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.237058781
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/33.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.2318345666
Short name	T697
Test name
Test status
Simulation time	130849839244 ps
CPU time	2585.85 seconds
Started	Sep 24 04:01:23 PM UTC 24
Finished	Sep 24 04:45:01 PM UTC 24
Peak memory	302048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318345666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2318345666
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.1408786608
Short name	T563
Test name
Test status
Simulation time	3223606301 ps
CPU time	93.5 seconds
Started	Sep 24 04:01:12 PM UTC 24
Finished	Sep 24 04:02:48 PM UTC 24
Peak memory	266632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408786608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1408786608
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.3361564191
Short name	T560
Test name
Test status
Simulation time	543193035 ps
CPU time	59.22 seconds
Started	Sep 24 04:01:02 PM UTC 24
Finished	Sep 24 04:02:04 PM UTC 24
Peak memory	260432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361564191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3361564191
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.1284886986
Short name	T645
Test name
Test status
Simulation time	12689719707 ps
CPU time	1507.85 seconds
Started	Sep 24 04:01:54 PM UTC 24
Finished	Sep 24 04:27:21 PM UTC 24
Peak memory	299476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284886986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1284886986
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.1466633781
Short name	T596
Test name
Test status
Simulation time	17587824474 ps
CPU time	843.27 seconds
Started	Sep 24 04:02:01 PM UTC 24
Finished	Sep 24 04:16:15 PM UTC 24
Peak memory	283364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466633781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1466633781
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.3691484799
Short name	T258
Test name
Test status
Simulation time	19018043396 ps
CPU time	535.05 seconds
Started	Sep 24 04:01:27 PM UTC 24
Finished	Sep 24 04:10:30 PM UTC 24
Peak memory	266980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691484799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3691484799
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.3506328466
Short name	T556
Test name
Test status
Simulation time	369117409 ps
CPU time	28.79 seconds
Started	Sep 24 04:00:29 PM UTC 24
Finished	Sep 24 04:01:00 PM UTC 24
Peak memory	266872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506328466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3506328466
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.3028005530
Short name	T558
Test name
Test status
Simulation time	191920263 ps
CPU time	9.06 seconds
Started	Sep 24 04:01:01 PM UTC 24
Finished	Sep 24 04:01:11 PM UTC 24
Peak memory	264824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028005530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3028005530
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.1320355988
Short name	T561
Test name
Test status
Simulation time	695884864 ps
CPU time	47.26 seconds
Started	Sep 24 04:01:19 PM UTC 24
Finished	Sep 24 04:02:08 PM UTC 24
Peak memory	260428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320355988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1320355988
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.3559422050
Short name	T557
Test name
Test status
Simulation time	1858124620 ps
CPU time	50.05 seconds
Started	Sep 24 04:00:10 PM UTC 24
Finished	Sep 24 04:01:02 PM UTC 24
Peak memory	266656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559422050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3559422050
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/34.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.4270554729
Short name	T699
Test name
Test status
Simulation time	156410278424 ps
CPU time	2558.31 seconds
Started	Sep 24 04:03:29 PM UTC 24
Finished	Sep 24 04:46:38 PM UTC 24
Peak memory	302048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270554729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4270554729
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.2737926368
Short name	T576
Test name
Test status
Simulation time	12327225925 ps
CPU time	194.48 seconds
Started	Sep 24 04:03:15 PM UTC 24
Finished	Sep 24 04:06:33 PM UTC 24
Peak memory	262600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737926368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2737926368
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.99132840
Short name	T565
Test name
Test status
Simulation time	553149557 ps
CPU time	39.32 seconds
Started	Sep 24 04:03:05 PM UTC 24
Finished	Sep 24 04:03:46 PM UTC 24
Peak memory	260432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99132840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc _intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.99132840
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.4182448585
Short name	T629
Test name
Test status
Simulation time	26420824537 ps
CPU time	1234.1 seconds
Started	Sep 24 04:03:54 PM UTC 24
Finished	Sep 24 04:24:43 PM UTC 24
Peak memory	297692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182448585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4182448585
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.793395113
Short name	T710
Test name
Test status
Simulation time	170522608475 ps
CPU time	3140.95 seconds
Started	Sep 24 04:03:55 PM UTC 24
Finished	Sep 24 04:56:53 PM UTC 24
Peak memory	302052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793395113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.793395113
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.1950254961
Short name	T577
Test name
Test status
Simulation time	31195559573 ps
CPU time	169.16 seconds
Started	Sep 24 04:03:48 PM UTC 24
Finished	Sep 24 04:06:40 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950254961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1950254961
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.1317134224
Short name	T567
Test name
Test status
Simulation time	6915240240 ps
CPU time	68.22 seconds
Started	Sep 24 04:02:43 PM UTC 24
Finished	Sep 24 04:03:53 PM UTC 24
Peak memory	266808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317134224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1317134224
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.250322420
Short name	T291
Test name
Test status
Simulation time	1015949280 ps
CPU time	33.86 seconds
Started	Sep 24 04:02:50 PM UTC 24
Finished	Sep 24 04:03:25 PM UTC 24
Peak memory	266576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250322420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.250322420
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.991821003
Short name	T566
Test name
Test status
Simulation time	563206801 ps
CPU time	23.45 seconds
Started	Sep 24 04:03:27 PM UTC 24
Finished	Sep 24 04:03:52 PM UTC 24
Peak memory	266872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991821003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.991821003
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.1891299273
Short name	T562
Test name
Test status
Simulation time	565383284 ps
CPU time	9.42 seconds
Started	Sep 24 04:02:31 PM UTC 24
Finished	Sep 24 04:02:41 PM UTC 24
Peak memory	262560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891299273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1891299273
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.1117902505
Short name	T688
Test name
Test status
Simulation time	155391090720 ps
CPU time	2214.01 seconds
Started	Sep 24 04:04:00 PM UTC 24
Finished	Sep 24 04:41:22 PM UTC 24
Peak memory	314336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117902505 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.1117902505
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all_with_rand_reset.1618968370
Short name	T245
Test name
Test status
Simulation time	7994301288 ps
CPU time	185.23 seconds
Started	Sep 24 04:04:04 PM UTC 24
Finished	Sep 24 04:07:13 PM UTC 24
Peak memory	277072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1618968370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.a lert_handler_stress_all_with_rand_reset.1618968370
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.1066870090
Short name	T698
Test name
Test status
Simulation time	44823891728 ps
CPU time	2416.83 seconds
Started	Sep 24 04:05:48 PM UTC 24
Finished	Sep 24 04:46:31 PM UTC 24
Peak memory	300000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066870090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1066870090
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.229883821
Short name	T588
Test name
Test status
Simulation time	53587756050 ps
CPU time	379.86 seconds
Started	Sep 24 04:05:37 PM UTC 24
Finished	Sep 24 04:12:04 PM UTC 24
Peak memory	266804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229883821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.229883821
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.380763178
Short name	T570
Test name
Test status
Simulation time	202934240 ps
CPU time	6.89 seconds
Started	Sep 24 04:05:28 PM UTC 24
Finished	Sep 24 04:05:36 PM UTC 24
Peak memory	250452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380763178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.380763178
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.3653536315
Short name	T384
Test name
Test status
Simulation time	31786637996 ps
CPU time	1891.05 seconds
Started	Sep 24 04:06:11 PM UTC 24
Finished	Sep 24 04:38:04 PM UTC 24
Peak memory	283356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653536315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3653536315
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.2200628432
Short name	T708
Test name
Test status
Simulation time	90791844068 ps
CPU time	2916.24 seconds
Started	Sep 24 04:06:15 PM UTC 24
Finished	Sep 24 04:55:27 PM UTC 24
Peak memory	302060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200628432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2200628432
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.626560576
Short name	T255
Test name
Test status
Simulation time	4538517469 ps
CPU time	184.64 seconds
Started	Sep 24 04:05:57 PM UTC 24
Finished	Sep 24 04:09:04 PM UTC 24
Peak memory	260568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626560576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.626560576
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.1962168418
Short name	T572
Test name
Test status
Simulation time	1193645098 ps
CPU time	37.64 seconds
Started	Sep 24 04:05:07 PM UTC 24
Finished	Sep 24 04:05:47 PM UTC 24
Peak memory	266744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962168418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1962168418
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.3920935513
Short name	T571
Test name
Test status
Simulation time	700881997 ps
CPU time	21.45 seconds
Started	Sep 24 04:05:15 PM UTC 24
Finished	Sep 24 04:05:38 PM UTC 24
Peak memory	260728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920935513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3920935513
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.1167270510
Short name	T142
Test name
Test status
Simulation time	675713431 ps
CPU time	32.06 seconds
Started	Sep 24 04:05:39 PM UTC 24
Finished	Sep 24 04:06:12 PM UTC 24
Peak memory	260500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167270510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1167270510
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.3005643668
Short name	T574
Test name
Test status
Simulation time	5090050213 ps
CPU time	59.73 seconds
Started	Sep 24 04:05:07 PM UTC 24
Finished	Sep 24 04:06:09 PM UTC 24
Peak memory	260568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005643668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3005643668
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/36.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.701522588
Short name	T659
Test name
Test status
Simulation time	11121452814 ps
CPU time	1370.75 seconds
Started	Sep 24 04:07:21 PM UTC 24
Finished	Sep 24 04:30:29 PM UTC 24
Peak memory	295456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701522588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.701522588
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.1526187739
Short name	T580
Test name
Test status
Simulation time	1724514861 ps
CPU time	207.36 seconds
Started	Sep 24 04:07:11 PM UTC 24
Finished	Sep 24 04:10:44 PM UTC 24
Peak memory	266708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526187739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1526187739
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.587088539
Short name	T253
Test name
Test status
Simulation time	522088949 ps
CPU time	39.4 seconds
Started	Sep 24 04:07:06 PM UTC 24
Finished	Sep 24 04:07:47 PM UTC 24
Peak memory	260428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587088539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.587088539
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.1044768495
Short name	T382
Test name
Test status
Simulation time	13772727264 ps
CPU time	1413.57 seconds
Started	Sep 24 04:07:35 PM UTC 24
Finished	Sep 24 04:31:26 PM UTC 24
Peak memory	299548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044768495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1044768495
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.1197727809
Short name	T356
Test name
Test status
Simulation time	40829062203 ps
CPU time	489.44 seconds
Started	Sep 24 04:07:25 PM UTC 24
Finished	Sep 24 04:15:40 PM UTC 24
Peak memory	266788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197727809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1197727809
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.1981574402
Short name	T578
Test name
Test status
Simulation time	214237448 ps
CPU time	19.17 seconds
Started	Sep 24 04:06:42 PM UTC 24
Finished	Sep 24 04:07:02 PM UTC 24
Peak memory	260728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981574402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1981574402
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.3610984681
Short name	T251
Test name
Test status
Simulation time	163484972 ps
CPU time	18.26 seconds
Started	Sep 24 04:07:04 PM UTC 24
Finished	Sep 24 04:07:23 PM UTC 24
Peak memory	266676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610984681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3610984681
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.3446240235
Short name	T579
Test name
Test status
Simulation time	1659993539 ps
CPU time	33.37 seconds
Started	Sep 24 04:06:35 PM UTC 24
Finished	Sep 24 04:07:10 PM UTC 24
Peak memory	266848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446240235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3446240235
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.3985225410
Short name	T261
Test name
Test status
Simulation time	2446890531 ps
CPU time	304.64 seconds
Started	Sep 24 04:08:54 PM UTC 24
Finished	Sep 24 04:14:04 PM UTC 24
Peak memory	266640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985225410 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.3985225410
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all_with_rand_reset.4255283545
Short name	T246
Test name
Test status
Simulation time	3004291368 ps
CPU time	214.12 seconds
Started	Sep 24 04:09:06 PM UTC 24
Finished	Sep 24 04:12:44 PM UTC 24
Peak memory	277080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4255283545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.a lert_handler_stress_all_with_rand_reset.4255283545
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.931253695
Short name	T621
Test name
Test status
Simulation time	7160619922 ps
CPU time	741.01 seconds
Started	Sep 24 04:10:59 PM UTC 24
Finished	Sep 24 04:23:30 PM UTC 24
Peak memory	283092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931253695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.931253695
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.2823653239
Short name	T585
Test name
Test status
Simulation time	4313458777 ps
CPU time	42.8 seconds
Started	Sep 24 04:10:42 PM UTC 24
Finished	Sep 24 04:11:26 PM UTC 24
Peak memory	260820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823653239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2823653239
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.4121065583
Short name	T582
Test name
Test status
Simulation time	1520348320 ps
CPU time	35.35 seconds
Started	Sep 24 04:10:38 PM UTC 24
Finished	Sep 24 04:11:15 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121065583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.4121065583
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.444253450
Short name	T383
Test name
Test status
Simulation time	61358008057 ps
CPU time	3501.59 seconds
Started	Sep 24 04:11:17 PM UTC 24
Finished	Sep 24 05:10:18 PM UTC 24
Peak memory	302120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444253450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.444253450
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.3220742183
Short name	T717
Test name
Test status
Simulation time	245475342938 ps
CPU time	3309.83 seconds
Started	Sep 24 04:11:17 PM UTC 24
Finished	Sep 24 05:07:06 PM UTC 24
Peak memory	300084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220742183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3220742183
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.2988889439
Short name	T598
Test name
Test status
Simulation time	7632664976 ps
CPU time	372.81 seconds
Started	Sep 24 04:11:01 PM UTC 24
Finished	Sep 24 04:17:19 PM UTC 24
Peak memory	260836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988889439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2988889439
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.1674897583
Short name	T583
Test name
Test status
Simulation time	1026875616 ps
CPU time	40.6 seconds
Started	Sep 24 04:10:33 PM UTC 24
Finished	Sep 24 04:11:15 PM UTC 24
Peak memory	260728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674897583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1674897583
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.2813081174
Short name	T581
Test name
Test status
Simulation time	884533730 ps
CPU time	24.01 seconds
Started	Sep 24 04:10:34 PM UTC 24
Finished	Sep 24 04:11:00 PM UTC 24
Peak memory	266576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813081174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2813081174
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.3633172022
Short name	T66
Test name
Test status
Simulation time	366597387 ps
CPU time	41.72 seconds
Started	Sep 24 04:10:46 PM UTC 24
Finished	Sep 24 04:11:29 PM UTC 24
Peak memory	266572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633172022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3633172022
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.1107258888
Short name	T584
Test name
Test status
Simulation time	833289609 ps
CPU time	71.89 seconds
Started	Sep 24 04:10:09 PM UTC 24
Finished	Sep 24 04:11:23 PM UTC 24
Peak memory	266656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107258888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1107258888
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.3253836776
Short name	T287
Test name
Test status
Simulation time	544799293297 ps
CPU time	3466.21 seconds
Started	Sep 24 04:11:25 PM UTC 24
Finished	Sep 24 05:09:52 PM UTC 24
Peak memory	312364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253836776 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.3253836776
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all_with_rand_reset.617258054
Short name	T601
Test name
Test status
Simulation time	18168342988 ps
CPU time	381.58 seconds
Started	Sep 24 04:11:28 PM UTC 24
Finished	Sep 24 04:17:56 PM UTC 24
Peak memory	279120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=617258054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.al ert_handler_stress_all_with_rand_reset.617258054
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.25716604
Short name	T114
Test name
Test status
Simulation time	100804929554 ps
CPU time	1756.22 seconds
Started	Sep 24 04:12:16 PM UTC 24
Finished	Sep 24 04:41:53 PM UTC 24
Peak memory	299476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25716604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.25716604
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.4176949966
Short name	T267
Test name
Test status
Simulation time	13414206895 ps
CPU time	197.67 seconds
Started	Sep 24 04:12:06 PM UTC 24
Finished	Sep 24 04:15:27 PM UTC 24
Peak memory	266704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176949966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.4176949966
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.3303070518
Short name	T590
Test name
Test status
Simulation time	540399243 ps
CPU time	13.68 seconds
Started	Sep 24 04:11:59 PM UTC 24
Finished	Sep 24 04:12:13 PM UTC 24
Peak memory	260432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303070518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3303070518
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.3185998131
Short name	T394
Test name
Test status
Simulation time	119484370181 ps
CPU time	1722.99 seconds
Started	Sep 24 04:12:39 PM UTC 24
Finished	Sep 24 04:41:45 PM UTC 24
Peak memory	299476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185998131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3185998131
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.3035735593
Short name	T666
Test name
Test status
Simulation time	8023425431 ps
CPU time	1108.99 seconds
Started	Sep 24 04:12:46 PM UTC 24
Finished	Sep 24 04:31:29 PM UTC 24
Peak memory	299556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035735593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3035735593
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.2604118614
Short name	T595
Test name
Test status
Simulation time	7698055193 ps
CPU time	216.85 seconds
Started	Sep 24 04:12:27 PM UTC 24
Finished	Sep 24 04:16:08 PM UTC 24
Peak memory	260568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604118614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2604118614
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.2587065248
Short name	T589
Test name
Test status
Simulation time	1736638775 ps
CPU time	34.46 seconds
Started	Sep 24 04:11:34 PM UTC 24
Finished	Sep 24 04:12:10 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587065248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2587065248
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.1778141344
Short name	T592
Test name
Test status
Simulation time	594419037 ps
CPU time	41.06 seconds
Started	Sep 24 04:11:55 PM UTC 24
Finished	Sep 24 04:12:38 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778141344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1778141344
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.4019411027
Short name	T591
Test name
Test status
Simulation time	99997147 ps
CPU time	12.57 seconds
Started	Sep 24 04:12:12 PM UTC 24
Finished	Sep 24 04:12:26 PM UTC 24
Peak memory	260628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019411027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.4019411027
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.2973873460
Short name	T587
Test name
Test status
Simulation time	206857657 ps
CPU time	22.12 seconds
Started	Sep 24 04:11:34 PM UTC 24
Finished	Sep 24 04:11:57 PM UTC 24
Peak memory	266848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973873460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2973873460
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.2957616829
Short name	T695
Test name
Test status
Simulation time	429393828518 ps
CPU time	1854.44 seconds
Started	Sep 24 04:13:10 PM UTC 24
Finished	Sep 24 04:44:27 PM UTC 24
Peak memory	283088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957616829 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.2957616829
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all_with_rand_reset.1825512923
Short name	T247
Test name
Test status
Simulation time	2291505638 ps
CPU time	246.78 seconds
Started	Sep 24 04:13:10 PM UTC 24
Finished	Sep 24 04:17:21 PM UTC 24
Peak memory	277012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1825512923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.a lert_handler_stress_all_with_rand_reset.1825512923
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.2654268578
Short name	T135
Test name
Test status
Simulation time	44630641 ps
CPU time	4.06 seconds
Started	Sep 24 02:58:18 PM UTC 24
Finished	Sep 24 02:58:23 PM UTC 24
Peak memory	260700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654268578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2654268578
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.729602044
Short name	T335
Test name
Test status
Simulation time	31401286120 ps
CPU time	1195.36 seconds
Started	Sep 24 02:57:56 PM UTC 24
Finished	Sep 24 03:18:05 PM UTC 24
Peak memory	299552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729602044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.729602044
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.4064711569
Short name	T22
Test name
Test status
Simulation time	1961113796 ps
CPU time	45.79 seconds
Started	Sep 24 02:58:09 PM UTC 24
Finished	Sep 24 02:58:56 PM UTC 24
Peak memory	260436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064711569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4064711569
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.4190040592
Short name	T48
Test name
Test status
Simulation time	716962175 ps
CPU time	19.1 seconds
Started	Sep 24 02:57:40 PM UTC 24
Finished	Sep 24 02:58:00 PM UTC 24
Peak memory	266572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190040592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4190040592
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.768757682
Short name	T82
Test name
Test status
Simulation time	1040385491 ps
CPU time	49.1 seconds
Started	Sep 24 02:57:35 PM UTC 24
Finished	Sep 24 02:58:26 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768757682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.768757682
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.2289730132
Short name	T374
Test name
Test status
Simulation time	180757071998 ps
CPU time	2540.37 seconds
Started	Sep 24 02:58:02 PM UTC 24
Finished	Sep 24 03:40:52 PM UTC 24
Peak memory	302120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289730132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2289730132
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.2743468337
Short name	T397
Test name
Test status
Simulation time	40480530764 ps
CPU time	2662.17 seconds
Started	Sep 24 02:58:06 PM UTC 24
Finished	Sep 24 03:43:01 PM UTC 24
Peak memory	302128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743468337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2743468337
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.938980827
Short name	T240
Test name
Test status
Simulation time	192557281 ps
CPU time	31.58 seconds
Started	Sep 24 02:57:35 PM UTC 24
Finished	Sep 24 02:58:08 PM UTC 24
Peak memory	266872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938980827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.938980827
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.1404966448
Short name	T121
Test name
Test status
Simulation time	631040660 ps
CPU time	66.41 seconds
Started	Sep 24 02:57:35 PM UTC 24
Finished	Sep 24 02:58:44 PM UTC 24
Peak memory	266936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404966448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1404966448
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.2681841280
Short name	T41
Test name
Test status
Simulation time	1578676559 ps
CPU time	39.07 seconds
Started	Sep 24 02:58:24 PM UTC 24
Finished	Sep 24 02:59:04 PM UTC 24
Peak memory	292804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681841280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2681841280
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.960826749
Short name	T28
Test name
Test status
Simulation time	171116775 ps
CPU time	22.26 seconds
Started	Sep 24 02:57:29 PM UTC 24
Finished	Sep 24 02:57:53 PM UTC 24
Peak memory	266652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960826749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.960826749
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all_with_rand_reset.3890768113
Short name	T35
Test name
Test status
Simulation time	1784868216 ps
CPU time	87.23 seconds
Started	Sep 24 02:58:23 PM UTC 24
Finished	Sep 24 02:59:52 PM UTC 24
Peak memory	277012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3890768113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.al ert_handler_stress_all_with_rand_reset.3890768113
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.773420182
Short name	T681
Test name
Test status
Simulation time	38927457770 ps
CPU time	1125 seconds
Started	Sep 24 04:15:29 PM UTC 24
Finished	Sep 24 04:34:28 PM UTC 24
Peak memory	283168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773420182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.773420182
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.1747922265
Short name	T616
Test name
Test status
Simulation time	5038122015 ps
CPU time	436.48 seconds
Started	Sep 24 04:14:57 PM UTC 24
Finished	Sep 24 04:22:20 PM UTC 24
Peak memory	266696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747922265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1747922265
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.1866954516
Short name	T266
Test name
Test status
Simulation time	222365244 ps
CPU time	26.42 seconds
Started	Sep 24 04:14:32 PM UTC 24
Finished	Sep 24 04:14:59 PM UTC 24
Peak memory	260632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866954516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1866954516
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.890142554
Short name	T665
Test name
Test status
Simulation time	21198769851 ps
CPU time	926.18 seconds
Started	Sep 24 04:15:42 PM UTC 24
Finished	Sep 24 04:31:20 PM UTC 24
Peak memory	283088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890142554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.890142554
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.1865689454
Short name	T713
Test name
Test status
Simulation time	39493996578 ps
CPU time	2751.29 seconds
Started	Sep 24 04:15:56 PM UTC 24
Finished	Sep 24 05:02:25 PM UTC 24
Peak memory	295916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865689454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1865689454
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.1821008914
Short name	T604
Test name
Test status
Simulation time	5523484318 ps
CPU time	240.39 seconds
Started	Sep 24 04:15:42 PM UTC 24
Finished	Sep 24 04:19:46 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821008914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1821008914
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.3754352932
Short name	T265
Test name
Test status
Simulation time	1029031115 ps
CPU time	30.82 seconds
Started	Sep 24 04:14:23 PM UTC 24
Finished	Sep 24 04:14:56 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754352932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3754352932
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.3628286717
Short name	T308
Test name
Test status
Simulation time	1576947131 ps
CPU time	81.26 seconds
Started	Sep 24 04:14:32 PM UTC 24
Finished	Sep 24 04:15:55 PM UTC 24
Peak memory	260464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628286717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3628286717
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.2167906095
Short name	T593
Test name
Test status
Simulation time	576475106 ps
CPU time	37.73 seconds
Started	Sep 24 04:15:01 PM UTC 24
Finished	Sep 24 04:15:41 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167906095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2167906095
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.947743623
Short name	T263
Test name
Test status
Simulation time	312275613 ps
CPU time	19.99 seconds
Started	Sep 24 04:14:06 PM UTC 24
Finished	Sep 24 04:14:27 PM UTC 24
Peak memory	260700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947743623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.947743623
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.3021437353
Short name	T611
Test name
Test status
Simulation time	10479793731 ps
CPU time	298.57 seconds
Started	Sep 24 04:16:11 PM UTC 24
Finished	Sep 24 04:21:14 PM UTC 24
Peak memory	266704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021437353 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.3021437353
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all_with_rand_reset.3487858935
Short name	T301
Test name
Test status
Simulation time	10897826318 ps
CPU time	489.53 seconds
Started	Sep 24 04:16:11 PM UTC 24
Finished	Sep 24 04:24:28 PM UTC 24
Peak memory	279384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3487858935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.a lert_handler_stress_all_with_rand_reset.3487858935
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.2759618634
Short name	T701
Test name
Test status
Simulation time	133414595631 ps
CPU time	1863.14 seconds
Started	Sep 24 04:17:52 PM UTC 24
Finished	Sep 24 04:49:17 PM UTC 24
Peak memory	299472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759618634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2759618634
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.2848076719
Short name	T613
Test name
Test status
Simulation time	4010749699 ps
CPU time	242.54 seconds
Started	Sep 24 04:17:24 PM UTC 24
Finished	Sep 24 04:21:30 PM UTC 24
Peak memory	262612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848076719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2848076719
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.3436581948
Short name	T603
Test name
Test status
Simulation time	523889711 ps
CPU time	55.57 seconds
Started	Sep 24 04:17:21 PM UTC 24
Finished	Sep 24 04:18:18 PM UTC 24
Peak memory	266576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436581948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3436581948
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.1863423396
Short name	T693
Test name
Test status
Simulation time	51050117835 ps
CPU time	1524.01 seconds
Started	Sep 24 04:18:00 PM UTC 24
Finished	Sep 24 04:43:43 PM UTC 24
Peak memory	283356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863423396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1863423396
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.12912807
Short name	T685
Test name
Test status
Simulation time	11781804794 ps
CPU time	1309.41 seconds
Started	Sep 24 04:18:00 PM UTC 24
Finished	Sep 24 04:40:07 PM UTC 24
Peak memory	283424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12912807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.12912807
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.1940841324
Short name	T619
Test name
Test status
Simulation time	15437419897 ps
CPU time	313.72 seconds
Started	Sep 24 04:17:56 PM UTC 24
Finished	Sep 24 04:23:15 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940841324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1940841324
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.4160100882
Short name	T602
Test name
Test status
Simulation time	1594080848 ps
CPU time	66.64 seconds
Started	Sep 24 04:16:49 PM UTC 24
Finished	Sep 24 04:17:57 PM UTC 24
Peak memory	266680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160100882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.4160100882
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.1283973865
Short name	T599
Test name
Test status
Simulation time	328695418 ps
CPU time	26.28 seconds
Started	Sep 24 04:17:12 PM UTC 24
Finished	Sep 24 04:17:40 PM UTC 24
Peak memory	266608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283973865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1283973865
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.967739184
Short name	T312
Test name
Test status
Simulation time	622242459 ps
CPU time	67.28 seconds
Started	Sep 24 04:17:42 PM UTC 24
Finished	Sep 24 04:18:51 PM UTC 24
Peak memory	266872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967739184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.967739184
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.3936251150
Short name	T597
Test name
Test status
Simulation time	922669966 ps
CPU time	27.96 seconds
Started	Sep 24 04:16:18 PM UTC 24
Finished	Sep 24 04:16:47 PM UTC 24
Peak memory	266584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936251150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3936251150
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.3896984687
Short name	T696
Test name
Test status
Simulation time	25079418737 ps
CPU time	1557.6 seconds
Started	Sep 24 04:18:20 PM UTC 24
Finished	Sep 24 04:44:37 PM UTC 24
Peak memory	299476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896984687 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.3896984687
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all_with_rand_reset.1780794834
Short name	T248
Test name
Test status
Simulation time	12698091185 ps
CPU time	231.55 seconds
Started	Sep 24 04:18:53 PM UTC 24
Finished	Sep 24 04:22:48 PM UTC 24
Peak memory	277072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1780794834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.a lert_handler_stress_all_with_rand_reset.1780794834
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.127749574
Short name	T709
Test name
Test status
Simulation time	91615555886 ps
CPU time	2091.24 seconds
Started	Sep 24 04:20:56 PM UTC 24
Finished	Sep 24 04:56:14 PM UTC 24
Peak memory	295916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127749574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.127749574
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.534503931
Short name	T636
Test name
Test status
Simulation time	41473490481 ps
CPU time	327.65 seconds
Started	Sep 24 04:20:53 PM UTC 24
Finished	Sep 24 04:26:25 PM UTC 24
Peak memory	266732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534503931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.534503931
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.1996423987
Short name	T610
Test name
Test status
Simulation time	954919068 ps
CPU time	38.15 seconds
Started	Sep 24 04:20:32 PM UTC 24
Finished	Sep 24 04:21:12 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996423987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1996423987
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.307183408
Short name	T707
Test name
Test status
Simulation time	45901731560 ps
CPU time	1879.95 seconds
Started	Sep 24 04:21:12 PM UTC 24
Finished	Sep 24 04:52:55 PM UTC 24
Peak memory	299476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307183408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.307183408
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.2799533556
Short name	T722
Test name
Test status
Simulation time	220541336272 ps
CPU time	3188.2 seconds
Started	Sep 24 04:21:14 PM UTC 24
Finished	Sep 24 05:14:59 PM UTC 24
Peak memory	302060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799533556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2799533556
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.1536033209
Short name	T624
Test name
Test status
Simulation time	4165195979 ps
CPU time	178.9 seconds
Started	Sep 24 04:21:12 PM UTC 24
Finished	Sep 24 04:24:15 PM UTC 24
Peak memory	260508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536033209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1536033209
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.2121694053
Short name	T612
Test name
Test status
Simulation time	3965206371 ps
CPU time	80.79 seconds
Started	Sep 24 04:19:51 PM UTC 24
Finished	Sep 24 04:21:15 PM UTC 24
Peak memory	266744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121694053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2121694053
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.3368537696
Short name	T605
Test name
Test status
Simulation time	318040328 ps
CPU time	36.72 seconds
Started	Sep 24 04:19:52 PM UTC 24
Finished	Sep 24 04:20:30 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368537696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3368537696
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.3896827644
Short name	T318
Test name
Test status
Simulation time	249255483 ps
CPU time	29.56 seconds
Started	Sep 24 04:20:56 PM UTC 24
Finished	Sep 24 04:21:27 PM UTC 24
Peak memory	260428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896827644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3896827644
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.3299276911
Short name	T607
Test name
Test status
Simulation time	1735507344 ps
CPU time	73.2 seconds
Started	Sep 24 04:19:34 PM UTC 24
Finished	Sep 24 04:20:49 PM UTC 24
Peak memory	260440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299276911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3299276911
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.2493122739
Short name	T625
Test name
Test status
Simulation time	10859168604 ps
CPU time	182.82 seconds
Started	Sep 24 04:21:19 PM UTC 24
Finished	Sep 24 04:24:25 PM UTC 24
Peak memory	266704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493122739 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.2493122739
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all_with_rand_reset.538112727
Short name	T639
Test name
Test status
Simulation time	2065199583 ps
CPU time	328.92 seconds
Started	Sep 24 04:21:19 PM UTC 24
Finished	Sep 24 04:26:53 PM UTC 24
Peak memory	276944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=538112727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.al ert_handler_stress_all_with_rand_reset.538112727
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.4217771155
Short name	T687
Test name
Test status
Simulation time	9534406430 ps
CPU time	1046.21 seconds
Started	Sep 24 04:22:46 PM UTC 24
Finished	Sep 24 04:40:26 PM UTC 24
Peak memory	283356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217771155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.4217771155
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.1135123060
Short name	T307
Test name
Test status
Simulation time	22492910133 ps
CPU time	376.99 seconds
Started	Sep 24 04:22:23 PM UTC 24
Finished	Sep 24 04:28:45 PM UTC 24
Peak memory	267028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135123060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1135123060
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.3002986823
Short name	T622
Test name
Test status
Simulation time	833394766 ps
CPU time	76.03 seconds
Started	Sep 24 04:22:20 PM UTC 24
Finished	Sep 24 04:23:39 PM UTC 24
Peak memory	266576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002986823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3002986823
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.3932806047
Short name	T691
Test name
Test status
Simulation time	80950162389 ps
CPU time	1197.63 seconds
Started	Sep 24 04:22:52 PM UTC 24
Finished	Sep 24 04:43:05 PM UTC 24
Peak memory	283352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932806047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3932806047
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.3538800911
Short name	T712
Test name
Test status
Simulation time	109190375051 ps
CPU time	2103.47 seconds
Started	Sep 24 04:23:17 PM UTC 24
Finished	Sep 24 04:58:46 PM UTC 24
Peak memory	302060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538800911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3538800911
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.4041149078
Short name	T653
Test name
Test status
Simulation time	9076215235 ps
CPU time	407.73 seconds
Started	Sep 24 04:22:50 PM UTC 24
Finished	Sep 24 04:29:43 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041149078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.4041149078
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.4010314450
Short name	T615
Test name
Test status
Simulation time	1691883183 ps
CPU time	43.33 seconds
Started	Sep 24 04:21:33 PM UTC 24
Finished	Sep 24 04:22:18 PM UTC 24
Peak memory	266872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010314450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.4010314450
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.1883261712
Short name	T620
Test name
Test status
Simulation time	1094983691 ps
CPU time	66.83 seconds
Started	Sep 24 04:22:14 PM UTC 24
Finished	Sep 24 04:23:23 PM UTC 24
Peak memory	266872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883261712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1883261712
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.328782769
Short name	T618
Test name
Test status
Simulation time	116336579 ps
CPU time	7.45 seconds
Started	Sep 24 04:22:36 PM UTC 24
Finished	Sep 24 04:22:45 PM UTC 24
Peak memory	260464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328782769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.328782769
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.3044342803
Short name	T617
Test name
Test status
Simulation time	4064588591 ps
CPU time	61.54 seconds
Started	Sep 24 04:21:30 PM UTC 24
Finished	Sep 24 04:22:34 PM UTC 24
Peak memory	266912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044342803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3044342803
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.2348217094
Short name	T632
Test name
Test status
Simulation time	5071104145 ps
CPU time	127.28 seconds
Started	Sep 24 04:23:25 PM UTC 24
Finished	Sep 24 04:25:35 PM UTC 24
Peak memory	266780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348217094 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.2348217094
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all_with_rand_reset.1607653545
Short name	T638
Test name
Test status
Simulation time	3992424162 ps
CPU time	183.52 seconds
Started	Sep 24 04:23:33 PM UTC 24
Finished	Sep 24 04:26:40 PM UTC 24
Peak memory	277008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1607653545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.a lert_handler_stress_all_with_rand_reset.1607653545
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.376316704
Short name	T627
Test name
Test status
Simulation time	27764710643 ps
CPU time	916.93 seconds
Started	Sep 24 04:24:48 PM UTC 24
Finished	Sep 24 04:40:16 PM UTC 24
Peak memory	283092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376316704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.376316704
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.1359729436
Short name	T651
Test name
Test status
Simulation time	11404047562 ps
CPU time	261.71 seconds
Started	Sep 24 04:24:31 PM UTC 24
Finished	Sep 24 04:28:57 PM UTC 24
Peak memory	266772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359729436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1359729436
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.661204204
Short name	T630
Test name
Test status
Simulation time	1812320756 ps
CPU time	30.53 seconds
Started	Sep 24 04:24:27 PM UTC 24
Finished	Sep 24 04:24:59 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661204204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.661204204
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.1023533474
Short name	T726
Test name
Test status
Simulation time	213121545877 ps
CPU time	3200.68 seconds
Started	Sep 24 04:24:53 PM UTC 24
Finished	Sep 24 05:18:52 PM UTC 24
Peak memory	302184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023533474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1023533474
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.1990352050
Short name	T725
Test name
Test status
Simulation time	110076166577 ps
CPU time	3094.28 seconds
Started	Sep 24 04:25:01 PM UTC 24
Finished	Sep 24 05:17:11 PM UTC 24
Peak memory	302056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990352050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1990352050
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.2625239406
Short name	T371
Test name
Test status
Simulation time	49742961030 ps
CPU time	345.9 seconds
Started	Sep 24 04:24:48 PM UTC 24
Finished	Sep 24 04:30:38 PM UTC 24
Peak memory	260572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625239406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2625239406
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.1990868664
Short name	T628
Test name
Test status
Simulation time	434576196 ps
CPU time	43.13 seconds
Started	Sep 24 04:23:58 PM UTC 24
Finished	Sep 24 04:24:43 PM UTC 24
Peak memory	266680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990868664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1990868664
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.1048415855
Short name	T626
Test name
Test status
Simulation time	1463549582 ps
CPU time	22.78 seconds
Started	Sep 24 04:24:16 PM UTC 24
Finished	Sep 24 04:24:40 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048415855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1048415855
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.897991807
Short name	T313
Test name
Test status
Simulation time	123688301 ps
CPU time	9.1 seconds
Started	Sep 24 04:24:41 PM UTC 24
Finished	Sep 24 04:24:52 PM UTC 24
Peak memory	260664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897991807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.897991807
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.3428517113
Short name	T623
Test name
Test status
Simulation time	117569081 ps
CPU time	14.09 seconds
Started	Sep 24 04:23:41 PM UTC 24
Finished	Sep 24 04:23:56 PM UTC 24
Peak memory	266584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428517113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3428517113
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.1721834712
Short name	T680
Test name
Test status
Simulation time	30611780947 ps
CPU time	512.44 seconds
Started	Sep 24 04:25:34 PM UTC 24
Finished	Sep 24 04:34:13 PM UTC 24
Peak memory	277020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721834712 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.1721834712
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/44.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.849583869
Short name	T704
Test name
Test status
Simulation time	12395499210 ps
CPU time	1427.27 seconds
Started	Sep 24 04:26:41 PM UTC 24
Finished	Sep 24 04:50:47 PM UTC 24
Peak memory	295380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849583869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.849583869
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.1726088005
Short name	T656
Test name
Test status
Simulation time	10589192019 ps
CPU time	221.21 seconds
Started	Sep 24 04:26:27 PM UTC 24
Finished	Sep 24 04:30:12 PM UTC 24
Peak memory	260552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726088005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1726088005
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.4167706379
Short name	T643
Test name
Test status
Simulation time	1324920545 ps
CPU time	45.5 seconds
Started	Sep 24 04:26:24 PM UTC 24
Finished	Sep 24 04:27:11 PM UTC 24
Peak memory	266840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167706379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.4167706379
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.2821386536
Short name	T719
Test name
Test status
Simulation time	48090427849 ps
CPU time	2584.32 seconds
Started	Sep 24 04:26:59 PM UTC 24
Finished	Sep 24 05:10:33 PM UTC 24
Peak memory	296236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821386536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2821386536
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.1077723782
Short name	T694
Test name
Test status
Simulation time	36877782318 ps
CPU time	1005.49 seconds
Started	Sep 24 04:27:04 PM UTC 24
Finished	Sep 24 04:44:03 PM UTC 24
Peak memory	283172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077723782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1077723782
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.3656736794
Short name	T657
Test name
Test status
Simulation time	20774359806 ps
CPU time	195.37 seconds
Started	Sep 24 04:26:56 PM UTC 24
Finished	Sep 24 04:30:14 PM UTC 24
Peak memory	260572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656736794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3656736794
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.815959767
Short name	T635
Test name
Test status
Simulation time	2298209188 ps
CPU time	18.75 seconds
Started	Sep 24 04:26:02 PM UTC 24
Finished	Sep 24 04:26:22 PM UTC 24
Peak memory	260604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815959767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.815959767
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.3563957836
Short name	T637
Test name
Test status
Simulation time	799221929 ps
CPU time	31.41 seconds
Started	Sep 24 04:26:06 PM UTC 24
Finished	Sep 24 04:26:39 PM UTC 24
Peak memory	266680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563957836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3563957836
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.4265839199
Short name	T640
Test name
Test status
Simulation time	477791905 ps
CPU time	16.46 seconds
Started	Sep 24 04:26:39 PM UTC 24
Finished	Sep 24 04:26:57 PM UTC 24
Peak memory	260692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265839199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.4265839199
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.3121630586
Short name	T644
Test name
Test status
Simulation time	7424279932 ps
CPU time	90.04 seconds
Started	Sep 24 04:25:40 PM UTC 24
Finished	Sep 24 04:27:13 PM UTC 24
Peak memory	266976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121630586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3121630586
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.3699553816
Short name	T326
Test name
Test status
Simulation time	16143512622 ps
CPU time	1507.18 seconds
Started	Sep 24 04:27:12 PM UTC 24
Finished	Sep 24 04:52:37 PM UTC 24
Peak memory	299548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699553816 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.3699553816
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all_with_rand_reset.2941573094
Short name	T668
Test name
Test status
Simulation time	2227838488 ps
CPU time	258.18 seconds
Started	Sep 24 04:27:14 PM UTC 24
Finished	Sep 24 04:31:36 PM UTC 24
Peak memory	283224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2941573094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.a lert_handler_stress_all_with_rand_reset.2941573094
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.1327194054
Short name	T714
Test name
Test status
Simulation time	29718119459 ps
CPU time	2135.92 seconds
Started	Sep 24 04:28:06 PM UTC 24
Finished	Sep 24 05:04:08 PM UTC 24
Peak memory	295904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327194054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1327194054
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.3586171009
Short name	T658
Test name
Test status
Simulation time	1759113621 ps
CPU time	149.08 seconds
Started	Sep 24 04:27:48 PM UTC 24
Finished	Sep 24 04:30:19 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586171009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3586171009
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.3812078801
Short name	T648
Test name
Test status
Simulation time	268294199 ps
CPU time	17.34 seconds
Started	Sep 24 04:27:45 PM UTC 24
Finished	Sep 24 04:28:04 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812078801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3812078801
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.680661838
Short name	T686
Test name
Test status
Simulation time	9009645694 ps
CPU time	686.07 seconds
Started	Sep 24 04:28:47 PM UTC 24
Finished	Sep 24 04:40:21 PM UTC 24
Peak memory	277020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680661838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.680661838
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.1546286944
Short name	T368
Test name
Test status
Simulation time	12169598888 ps
CPU time	717.37 seconds
Started	Sep 24 04:28:13 PM UTC 24
Finished	Sep 24 04:40:20 PM UTC 24
Peak memory	266716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546286944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1546286944
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.1849198272
Short name	T649
Test name
Test status
Simulation time	795625834 ps
CPU time	52.66 seconds
Started	Sep 24 04:27:17 PM UTC 24
Finished	Sep 24 04:28:11 PM UTC 24
Peak memory	266608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849198272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1849198272
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.179579416
Short name	T647
Test name
Test status
Simulation time	343761753 ps
CPU time	17.07 seconds
Started	Sep 24 04:27:25 PM UTC 24
Finished	Sep 24 04:27:43 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179579416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.179579416
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.311945868
Short name	T107
Test name
Test status
Simulation time	482516259 ps
CPU time	51.09 seconds
Started	Sep 24 04:27:56 PM UTC 24
Finished	Sep 24 04:28:48 PM UTC 24
Peak memory	260728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311945868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.311945868
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.299694800
Short name	T650
Test name
Test status
Simulation time	1325373611 ps
CPU time	70.58 seconds
Started	Sep 24 04:27:17 PM UTC 24
Finished	Sep 24 04:28:29 PM UTC 24
Peak memory	260508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299694800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.299694800
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/46.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.3243651708
Short name	T720
Test name
Test status
Simulation time	43482712017 ps
CPU time	2501.4 seconds
Started	Sep 24 04:30:15 PM UTC 24
Finished	Sep 24 05:12:25 PM UTC 24
Peak memory	302316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243651708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3243651708
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.1897215069
Short name	T663
Test name
Test status
Simulation time	3133317369 ps
CPU time	73.61 seconds
Started	Sep 24 04:29:59 PM UTC 24
Finished	Sep 24 04:31:14 PM UTC 24
Peak memory	260068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897215069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1897215069
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.3344244302
Short name	T655
Test name
Test status
Simulation time	145882138 ps
CPU time	7.71 seconds
Started	Sep 24 04:29:59 PM UTC 24
Finished	Sep 24 04:30:07 PM UTC 24
Peak memory	264168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344244302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3344244302
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.1534206603
Short name	T395
Test name
Test status
Simulation time	40367867900 ps
CPU time	2308.36 seconds
Started	Sep 24 04:30:22 PM UTC 24
Finished	Sep 24 05:09:16 PM UTC 24
Peak memory	285932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534206603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1534206603
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.3199809254
Short name	T703
Test name
Test status
Simulation time	42053267787 ps
CPU time	1168.45 seconds
Started	Sep 24 04:30:32 PM UTC 24
Finished	Sep 24 04:50:15 PM UTC 24
Peak memory	299480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199809254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3199809254
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.2792765468
Short name	T683
Test name
Test status
Simulation time	9251956516 ps
CPU time	488.84 seconds
Started	Sep 24 04:30:17 PM UTC 24
Finished	Sep 24 04:38:32 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792765468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2792765468
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.3049193785
Short name	T654
Test name
Test status
Simulation time	1990407445 ps
CPU time	22.94 seconds
Started	Sep 24 04:29:30 PM UTC 24
Finished	Sep 24 04:29:54 PM UTC 24
Peak memory	260536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049193785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3049193785
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.3600913042
Short name	T660
Test name
Test status
Simulation time	668206056 ps
CPU time	58.2 seconds
Started	Sep 24 04:29:45 PM UTC 24
Finished	Sep 24 04:30:46 PM UTC 24
Peak memory	266604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600913042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3600913042
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.925179337
Short name	T316
Test name
Test status
Simulation time	744918418 ps
CPU time	40.69 seconds
Started	Sep 24 04:30:08 PM UTC 24
Finished	Sep 24 04:30:50 PM UTC 24
Peak memory	260432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925179337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.925179337
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.1320257551
Short name	T661
Test name
Test status
Simulation time	1084826092 ps
CPU time	85.32 seconds
Started	Sep 24 04:29:19 PM UTC 24
Finished	Sep 24 04:30:46 PM UTC 24
Peak memory	260440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320257551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1320257551
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.4230370249
Short name	T715
Test name
Test status
Simulation time	216506827716 ps
CPU time	2107.98 seconds
Started	Sep 24 04:30:40 PM UTC 24
Finished	Sep 24 05:06:13 PM UTC 24
Peak memory	299472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230370249 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.4230370249
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all_with_rand_reset.2091520644
Short name	T322
Test name
Test status
Simulation time	10083532003 ps
CPU time	404.95 seconds
Started	Sep 24 04:30:49 PM UTC 24
Finished	Sep 24 04:37:40 PM UTC 24
Peak memory	277144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2091520644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.a lert_handler_stress_all_with_rand_reset.2091520644
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.1364649628
Short name	T721
Test name
Test status
Simulation time	173994964405 ps
CPU time	2508.21 seconds
Started	Sep 24 04:31:21 PM UTC 24
Finished	Sep 24 05:13:38 PM UTC 24
Peak memory	302124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364649628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1364649628
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.761074326
Short name	T670
Test name
Test status
Simulation time	511700919 ps
CPU time	29.55 seconds
Started	Sep 24 04:31:16 PM UTC 24
Finished	Sep 24 04:31:47 PM UTC 24
Peak memory	266676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761074326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.761074326
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.453549652
Short name	T667
Test name
Test status
Simulation time	321677310 ps
CPU time	25.99 seconds
Started	Sep 24 04:31:07 PM UTC 24
Finished	Sep 24 04:31:34 PM UTC 24
Peak memory	260692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453549652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.453549652
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.2526618496
Short name	T724
Test name
Test status
Simulation time	174915071313 ps
CPU time	2675.03 seconds
Started	Sep 24 04:31:29 PM UTC 24
Finished	Sep 24 05:16:33 PM UTC 24
Peak memory	302124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526618496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2526618496
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.741292715
Short name	T716
Test name
Test status
Simulation time	39985394891 ps
CPU time	2100.8 seconds
Started	Sep 24 04:31:33 PM UTC 24
Finished	Sep 24 05:07:00 PM UTC 24
Peak memory	293408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741292715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.741292715
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.672653279
Short name	T690
Test name
Test status
Simulation time	21694185907 ps
CPU time	685.68 seconds
Started	Sep 24 04:31:24 PM UTC 24
Finished	Sep 24 04:42:59 PM UTC 24
Peak memory	260568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672653279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.672653279
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.2276858205
Short name	T662
Test name
Test status
Simulation time	75249838 ps
CPU time	13.43 seconds
Started	Sep 24 04:30:49 PM UTC 24
Finished	Sep 24 04:31:05 PM UTC 24
Peak memory	264632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276858205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2276858205
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.1140349524
Short name	T664
Test name
Test status
Simulation time	660520082 ps
CPU time	23.19 seconds
Started	Sep 24 04:30:51 PM UTC 24
Finished	Sep 24 04:31:17 PM UTC 24
Peak memory	260464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140349524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1140349524
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.466756335
Short name	T671
Test name
Test status
Simulation time	813405070 ps
CPU time	26.74 seconds
Started	Sep 24 04:31:21 PM UTC 24
Finished	Sep 24 04:31:49 PM UTC 24
Peak memory	260472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466756335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.466756335
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.316591681
Short name	T669
Test name
Test status
Simulation time	3377801776 ps
CPU time	50.1 seconds
Started	Sep 24 04:30:49 PM UTC 24
Finished	Sep 24 04:31:42 PM UTC 24
Peak memory	266640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316591681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.316591681
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.2283198922
Short name	T702
Test name
Test status
Simulation time	40761932215 ps
CPU time	1086.51 seconds
Started	Sep 24 04:31:35 PM UTC 24
Finished	Sep 24 04:49:55 PM UTC 24
Peak memory	293332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283198922 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.2283198922
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/48.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.849068329
Short name	T718
Test name
Test status
Simulation time	28762554471 ps
CPU time	2121.16 seconds
Started	Sep 24 04:32:47 PM UTC 24
Finished	Sep 24 05:08:35 PM UTC 24
Peak memory	293408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849068329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.849068329
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.3516652884
Short name	T677
Test name
Test status
Simulation time	13329996615 ps
CPU time	76.3 seconds
Started	Sep 24 04:32:11 PM UTC 24
Finished	Sep 24 04:33:30 PM UTC 24
Peak memory	260564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516652884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3516652884
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.945028128
Short name	T679
Test name
Test status
Simulation time	1896117027 ps
CPU time	96.23 seconds
Started	Sep 24 04:32:00 PM UTC 24
Finished	Sep 24 04:33:38 PM UTC 24
Peak memory	266572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945028128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.945028128
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.301910274
Short name	T706
Test name
Test status
Simulation time	42365519534 ps
CPU time	1063.17 seconds
Started	Sep 24 04:33:20 PM UTC 24
Finished	Sep 24 04:51:17 PM UTC 24
Peak memory	283416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301910274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.301910274
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.2583639141
Short name	T711
Test name
Test status
Simulation time	50180316070 ps
CPU time	1476.68 seconds
Started	Sep 24 04:33:34 PM UTC 24
Finished	Sep 24 04:58:30 PM UTC 24
Peak memory	295460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583639141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2583639141
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.4191856566
Short name	T684
Test name
Test status
Simulation time	18054889912 ps
CPU time	405.37 seconds
Started	Sep 24 04:33:06 PM UTC 24
Finished	Sep 24 04:39:57 PM UTC 24
Peak memory	260644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191856566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.4191856566
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.2077487389
Short name	T672
Test name
Test status
Simulation time	243316073 ps
CPU time	19.86 seconds
Started	Sep 24 04:31:49 PM UTC 24
Finished	Sep 24 04:32:10 PM UTC 24
Peak memory	260464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077487389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2077487389
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.1630205950
Short name	T673
Test name
Test status
Simulation time	2296597747 ps
CPU time	49.45 seconds
Started	Sep 24 04:31:52 PM UTC 24
Finished	Sep 24 04:32:43 PM UTC 24
Peak memory	266640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630205950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1630205950
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.2124129440
Short name	T675
Test name
Test status
Simulation time	167265108 ps
CPU time	18.66 seconds
Started	Sep 24 04:32:45 PM UTC 24
Finished	Sep 24 04:33:04 PM UTC 24
Peak memory	264524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124129440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2124129440
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.20687129
Short name	T674
Test name
Test status
Simulation time	2323678586 ps
CPU time	59.63 seconds
Started	Sep 24 04:31:43 PM UTC 24
Finished	Sep 24 04:32:44 PM UTC 24
Peak memory	260496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20687129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.20687129
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.3090813259
Short name	T328
Test name
Test status
Simulation time	94261518257 ps
CPU time	2624.8 seconds
Started	Sep 24 04:33:34 PM UTC 24
Finished	Sep 24 05:17:50 PM UTC 24
Peak memory	302060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090813259 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.3090813259
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.1878388929
Short name	T249
Test name
Test status
Simulation time	1986456881 ps
CPU time	126.42 seconds
Started	Sep 24 04:33:40 PM UTC 24
Finished	Sep 24 04:35:49 PM UTC 24
Peak memory	276944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1878388929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.a lert_handler_stress_all_with_rand_reset.1878388929
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.356201481
Short name	T50
Test name
Test status
Simulation time	132075871 ps
CPU time	5.69 seconds
Started	Sep 24 02:59:05 PM UTC 24
Finished	Sep 24 02:59:12 PM UTC 24
Peak memory	260704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356201481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.356201481
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.672791505
Short name	T503
Test name
Test status
Simulation time	76613465986 ps
CPU time	2650.48 seconds
Started	Sep 24 02:58:56 PM UTC 24
Finished	Sep 24 03:43:38 PM UTC 24
Peak memory	295984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672791505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.672791505
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.1911548579
Short name	T23
Test name
Test status
Simulation time	2300832082 ps
CPU time	46.97 seconds
Started	Sep 24 02:59:02 PM UTC 24
Finished	Sep 24 02:59:50 PM UTC 24
Peak memory	260504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911548579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1911548579
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.2846002976
Short name	T225
Test name
Test status
Simulation time	1638382126 ps
CPU time	83.56 seconds
Started	Sep 24 02:58:45 PM UTC 24
Finished	Sep 24 03:00:10 PM UTC 24
Peak memory	266640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846002976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2846002976
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.4176059476
Short name	T85
Test name
Test status
Simulation time	419819490 ps
CPU time	36.62 seconds
Started	Sep 24 02:58:35 PM UTC 24
Finished	Sep 24 02:59:13 PM UTC 24
Peak memory	260472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176059476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.4176059476
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.697410606
Short name	T330
Test name
Test status
Simulation time	24080353000 ps
CPU time	1037.35 seconds
Started	Sep 24 02:58:57 PM UTC 24
Finished	Sep 24 03:16:28 PM UTC 24
Peak memory	283084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697410606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.697410606
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.2761266370
Short name	T480
Test name
Test status
Simulation time	81641441858 ps
CPU time	1999.81 seconds
Started	Sep 24 02:58:59 PM UTC 24
Finished	Sep 24 03:32:44 PM UTC 24
Peak memory	299480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761266370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2761266370
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.87114414
Short name	T19
Test name
Test status
Simulation time	33677573215 ps
CPU time	129.48 seconds
Started	Sep 24 02:58:57 PM UTC 24
Finished	Sep 24 03:01:09 PM UTC 24
Peak memory	260828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87114414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.87114414
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.3737887465
Short name	T153
Test name
Test status
Simulation time	1817366269 ps
CPU time	60.27 seconds
Started	Sep 24 02:58:27 PM UTC 24
Finished	Sep 24 02:59:29 PM UTC 24
Peak memory	260500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737887465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3737887465
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.3110505367
Short name	T52
Test name
Test status
Simulation time	2791448569 ps
CPU time	65.59 seconds
Started	Sep 24 02:58:27 PM UTC 24
Finished	Sep 24 02:59:35 PM UTC 24
Peak memory	260600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110505367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3110505367
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.3871525825
Short name	T49
Test name
Test status
Simulation time	152038356 ps
CPU time	19.04 seconds
Started	Sep 24 02:58:50 PM UTC 24
Finished	Sep 24 02:59:10 PM UTC 24
Peak memory	260728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871525825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3871525825
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.1806855134
Short name	T227
Test name
Test status
Simulation time	632187018 ps
CPU time	20.47 seconds
Started	Sep 24 02:58:27 PM UTC 24
Finished	Sep 24 02:58:49 PM UTC 24
Peak memory	266836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806855134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1806855134
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.580615866
Short name	T311
Test name
Test status
Simulation time	176780693719 ps
CPU time	3446.49 seconds
Started	Sep 24 02:59:05 PM UTC 24
Finished	Sep 24 03:57:12 PM UTC 24
Peak memory	312288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580615866 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.580615866
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all_with_rand_reset.2547150091
Short name	T92
Test name
Test status
Simulation time	3209508276 ps
CPU time	575.03 seconds
Started	Sep 24 02:59:08 PM UTC 24
Finished	Sep 24 03:08:51 PM UTC 24
Peak memory	279124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2547150091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.al ert_handler_stress_all_with_rand_reset.2547150091
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.301487176
Short name	T143
Test name
Test status
Simulation time	182115198 ps
CPU time	6.59 seconds
Started	Sep 24 02:59:52 PM UTC 24
Finished	Sep 24 03:00:00 PM UTC 24
Peak memory	260776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301487176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.301487176
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.2604331938
Short name	T305
Test name
Test status
Simulation time	15885810836 ps
CPU time	1460.09 seconds
Started	Sep 24 02:59:30 PM UTC 24
Finished	Sep 24 03:24:09 PM UTC 24
Peak memory	276948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604331938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2604331938
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.1582937328
Short name	T24
Test name
Test status
Simulation time	232707388 ps
CPU time	18.86 seconds
Started	Sep 24 02:59:49 PM UTC 24
Finished	Sep 24 03:00:10 PM UTC 24
Peak memory	260440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582937328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1582937328
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.1047567889
Short name	T226
Test name
Test status
Simulation time	4653907961 ps
CPU time	51.77 seconds
Started	Sep 24 02:59:24 PM UTC 24
Finished	Sep 24 03:00:18 PM UTC 24
Peak memory	266768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047567889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1047567889
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.18051673
Short name	T86
Test name
Test status
Simulation time	1572131543 ps
CPU time	55.62 seconds
Started	Sep 24 02:59:14 PM UTC 24
Finished	Sep 24 03:00:11 PM UTC 24
Peak memory	266868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18051673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc _intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.18051673
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.3181700625
Short name	T502
Test name
Test status
Simulation time	39377586538 ps
CPU time	2567.97 seconds
Started	Sep 24 02:59:46 PM UTC 24
Finished	Sep 24 03:43:06 PM UTC 24
Peak memory	285744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181700625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3181700625
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.2899952691
Short name	T336
Test name
Test status
Simulation time	9228716801 ps
CPU time	184.02 seconds
Started	Sep 24 02:59:32 PM UTC 24
Finished	Sep 24 03:02:39 PM UTC 24
Peak memory	260640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899952691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2899952691
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.3643925228
Short name	T79
Test name
Test status
Simulation time	209136211 ps
CPU time	32.71 seconds
Started	Sep 24 02:59:11 PM UTC 24
Finished	Sep 24 02:59:45 PM UTC 24
Peak memory	260732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643925228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3643925228
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.3174150578
Short name	T90
Test name
Test status
Simulation time	723264728 ps
CPU time	38.28 seconds
Started	Sep 24 02:59:13 PM UTC 24
Finished	Sep 24 02:59:53 PM UTC 24
Peak memory	260444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174150578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3174150578
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.3229432623
Short name	T80
Test name
Test status
Simulation time	513071774 ps
CPU time	39.13 seconds
Started	Sep 24 02:59:10 PM UTC 24
Finished	Sep 24 02:59:50 PM UTC 24
Peak memory	266836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229432623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3229432623
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.3837445535
Short name	T136
Test name
Test status
Simulation time	581762094 ps
CPU time	22.25 seconds
Started	Sep 24 02:59:52 PM UTC 24
Finished	Sep 24 03:00:16 PM UTC 24
Peak memory	260428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837445535 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.3837445535
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.171972051
Short name	T228
Test name
Test status
Simulation time	163624643 ps
CPU time	5.79 seconds
Started	Sep 24 03:00:46 PM UTC 24
Finished	Sep 24 03:00:53 PM UTC 24
Peak memory	260776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171972051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.171972051
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.352753036
Short name	T25
Test name
Test status
Simulation time	761114306 ps
CPU time	21.38 seconds
Started	Sep 24 03:00:31 PM UTC 24
Finished	Sep 24 03:00:54 PM UTC 24
Peak memory	260436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352753036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.352753036
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.2612262720
Short name	T146
Test name
Test status
Simulation time	5900544851 ps
CPU time	156.7 seconds
Started	Sep 24 03:00:11 PM UTC 24
Finished	Sep 24 03:02:52 PM UTC 24
Peak memory	262600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612262720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2612262720
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.799816207
Short name	T87
Test name
Test status
Simulation time	2532685451 ps
CPU time	62.63 seconds
Started	Sep 24 03:00:11 PM UTC 24
Finished	Sep 24 03:01:17 PM UTC 24
Peak memory	260756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799816207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.799816207
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.1164298760
Short name	T332
Test name
Test status
Simulation time	27434857793 ps
CPU time	1606.26 seconds
Started	Sep 24 03:00:18 PM UTC 24
Finished	Sep 24 03:27:25 PM UTC 24
Peak memory	299548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164298760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1164298760
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.4150206539
Short name	T380
Test name
Test status
Simulation time	12944102102 ps
CPU time	823.96 seconds
Started	Sep 24 03:00:21 PM UTC 24
Finished	Sep 24 03:14:16 PM UTC 24
Peak memory	277024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150206539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.4150206539
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.1728604475
Short name	T340
Test name
Test status
Simulation time	15190575897 ps
CPU time	600.2 seconds
Started	Sep 24 03:00:17 PM UTC 24
Finished	Sep 24 03:10:25 PM UTC 24
Peak memory	260832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728604475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1728604475
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.1186588711
Short name	T144
Test name
Test status
Simulation time	956661292 ps
CPU time	15.2 seconds
Started	Sep 24 02:59:54 PM UTC 24
Finished	Sep 24 03:00:10 PM UTC 24
Peak memory	266684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186588711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1186588711
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.2140403496
Short name	T112
Test name
Test status
Simulation time	298549188 ps
CPU time	21.26 seconds
Started	Sep 24 03:00:02 PM UTC 24
Finished	Sep 24 03:00:30 PM UTC 24
Peak memory	266608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140403496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2140403496
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.1290803626
Short name	T88
Test name
Test status
Simulation time	686116680 ps
CPU time	77.21 seconds
Started	Sep 24 03:00:12 PM UTC 24
Finished	Sep 24 03:01:32 PM UTC 24
Peak memory	260464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290803626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1290803626
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.3581586620
Short name	T420
Test name
Test status
Simulation time	684792661 ps
CPU time	62.24 seconds
Started	Sep 24 02:59:53 PM UTC 24
Finished	Sep 24 03:00:58 PM UTC 24
Peak memory	266836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581586620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3581586620
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.3266943616
Short name	T422
Test name
Test status
Simulation time	555376324 ps
CPU time	54.64 seconds
Started	Sep 24 03:00:42 PM UTC 24
Finished	Sep 24 03:01:39 PM UTC 24
Peak memory	266772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266943616 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.3266943616
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/7.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.2460751478
Short name	T229
Test name
Test status
Simulation time	35792969 ps
CPU time	5.37 seconds
Started	Sep 24 03:01:51 PM UTC 24
Finished	Sep 24 03:01:57 PM UTC 24
Peak memory	260692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460751478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2460751478
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.754215600
Short name	T32
Test name
Test status
Simulation time	7898428125 ps
CPU time	1155.06 seconds
Started	Sep 24 03:01:17 PM UTC 24
Finished	Sep 24 03:20:50 PM UTC 24
Peak memory	299556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754215600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.754215600
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.1316508613
Short name	T149
Test name
Test status
Simulation time	919258468 ps
CPU time	56.01 seconds
Started	Sep 24 03:01:36 PM UTC 24
Finished	Sep 24 03:02:33 PM UTC 24
Peak memory	260436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316508613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1316508613
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.2728925508
Short name	T280
Test name
Test status
Simulation time	1990570788 ps
CPU time	78.45 seconds
Started	Sep 24 03:01:10 PM UTC 24
Finished	Sep 24 03:02:30 PM UTC 24
Peak memory	260624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728925508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2728925508
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.1976522896
Short name	T423
Test name
Test status
Simulation time	1732018391 ps
CPU time	46.13 seconds
Started	Sep 24 03:01:02 PM UTC 24
Finished	Sep 24 03:01:50 PM UTC 24
Peak memory	260464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976522896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1976522896
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.1242056064
Short name	T286
Test name
Test status
Simulation time	291252939094 ps
CPU time	3101.73 seconds
Started	Sep 24 03:01:33 PM UTC 24
Finished	Sep 24 03:53:51 PM UTC 24
Peak memory	302044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242056064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1242056064
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.6870447
Short name	T337
Test name
Test status
Simulation time	20006422668 ps
CPU time	504.71 seconds
Started	Sep 24 03:01:25 PM UTC 24
Finished	Sep 24 03:09:57 PM UTC 24
Peak memory	260640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6870447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test + UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.6870447
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.1636192790
Short name	T421
Test name
Test status
Simulation time	59781266 ps
CPU time	4.89 seconds
Started	Sep 24 03:00:55 PM UTC 24
Finished	Sep 24 03:01:01 PM UTC 24
Peak memory	250188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636192790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1636192790
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.854861782
Short name	T137
Test name
Test status
Simulation time	868645453 ps
CPU time	55.57 seconds
Started	Sep 24 03:00:59 PM UTC 24
Finished	Sep 24 03:01:56 PM UTC 24
Peak memory	260756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854861782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.854861782
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.2814233547
Short name	T297
Test name
Test status
Simulation time	1246963982 ps
CPU time	64.39 seconds
Started	Sep 24 03:00:54 PM UTC 24
Finished	Sep 24 03:02:00 PM UTC 24
Peak memory	266572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814233547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2814233547
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.3638581108
Short name	T120
Test name
Test status
Simulation time	12240119462 ps
CPU time	568.88 seconds
Started	Sep 24 03:01:40 PM UTC 24
Finished	Sep 24 03:11:17 PM UTC 24
Peak memory	266900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638581108 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.3638581108
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all_with_rand_reset.4159728398
Short name	T119
Test name
Test status
Simulation time	54637170853 ps
CPU time	490.97 seconds
Started	Sep 24 03:01:57 PM UTC 24
Finished	Sep 24 03:10:15 PM UTC 24
Peak memory	283212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4159728398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.al ert_handler_stress_all_with_rand_reset.4159728398
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.3598556949
Short name	T230
Test name
Test status
Simulation time	43656379 ps
CPU time	3.73 seconds
Started	Sep 24 03:02:55 PM UTC 24
Finished	Sep 24 03:02:59 PM UTC 24
Peak memory	260692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598556949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3598556949
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.4202739048
Short name	T277
Test name
Test status
Simulation time	119477312805 ps
CPU time	919.81 seconds
Started	Sep 24 03:02:32 PM UTC 24
Finished	Sep 24 03:18:03 PM UTC 24
Peak memory	283168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202739048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.4202739048
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_entropy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.3391976750
Short name	T150
Test name
Test status
Simulation time	183343131 ps
CPU time	9.63 seconds
Started	Sep 24 03:02:52 PM UTC 24
Finished	Sep 24 03:03:03 PM UTC 24
Peak memory	260436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391976750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3391976750
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.10335811
Short name	T99
Test name
Test status
Simulation time	1473306698 ps
CPU time	183.3 seconds
Started	Sep 24 03:02:26 PM UTC 24
Finished	Sep 24 03:05:32 PM UTC 24
Peak memory	266580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10335811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc _alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.10335811
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.2180196212
Short name	T89
Test name
Test status
Simulation time	116143889 ps
CPU time	7.36 seconds
Started	Sep 24 03:02:16 PM UTC 24
Finished	Sep 24 03:02:24 PM UTC 24
Peak memory	260432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180196212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2180196212
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.3689203257
Short name	T333
Test name
Test status
Simulation time	32829536162 ps
CPU time	1696.11 seconds
Started	Sep 24 03:02:36 PM UTC 24
Finished	Sep 24 03:31:15 PM UTC 24
Peak memory	299472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689203257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3689203257
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_lpg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.4141922043
Short name	T134
Test name
Test status
Simulation time	74705562633 ps
CPU time	2697.24 seconds
Started	Sep 24 03:02:40 PM UTC 24
Finished	Sep 24 03:48:10 PM UTC 24
Peak memory	302048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141922043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.4141922043
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.1358882771
Short name	T341
Test name
Test status
Simulation time	8458438342 ps
CPU time	347.49 seconds
Started	Sep 24 03:02:34 PM UTC 24
Finished	Sep 24 03:08:26 PM UTC 24
Peak memory	260640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358882771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1358882771
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.2166127473
Short name	T53
Test name
Test status
Simulation time	448281384 ps
CPU time	21.38 seconds
Started	Sep 24 03:02:00 PM UTC 24
Finished	Sep 24 03:02:23 PM UTC 24
Peak memory	260428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166127473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2166127473
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.1734547180
Short name	T81
Test name
Test status
Simulation time	782219998 ps
CPU time	48.79 seconds
Started	Sep 24 03:02:02 PM UTC 24
Finished	Sep 24 03:02:52 PM UTC 24
Peak memory	260464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734547180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1734547180
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_random_classes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.345947278
Short name	T145
Test name
Test status
Simulation time	732787174 ps
CPU time	7.72 seconds
Started	Sep 24 03:02:26 PM UTC 24
Finished	Sep 24 03:02:35 PM UTC 24
Peak memory	250260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345947278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.345947278
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.3570304315
Short name	T424
Test name
Test status
Simulation time	372950857 ps
CPU time	53.57 seconds
Started	Sep 24 03:01:58 PM UTC 24
Finished	Sep 24 03:02:54 PM UTC 24
Peak memory	266644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570304315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3570304315
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.206355922
Short name	T68
Test name
Test status
Simulation time	859027260 ps
CPU time	68.04 seconds
Started	Sep 24 03:02:55 PM UTC 24
Finished	Sep 24 03:04:05 PM UTC 24
Peak memory	266648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206355922 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.206355922
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_stress_all/latest