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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed.CheckSwAccessIsLegal_A	0	0	822	822	0	0
tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed.MubiIsNotYetSupported_A	0	0	561845997	561212097	0	0
tb.dut.u_reg_wrap.u_reg.u_reg_if.AllowedLatency_A	0	0	822	822	0	0
tb.dut.u_reg_wrap.u_reg.u_reg_if.MatchedWidthAssert	0	0	822	822	0	0
tb.dut.u_reg_wrap.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	822	822	0	0
tb.dut.u_reg_wrap.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	822	822	0	0
tb.dut.u_reg_wrap.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	822	822	0	0
tb.dut.u_reg_wrap.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	822	822	0	0
tb.dut.u_reg_wrap.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	822	822	0	0
tb.dut.u_reg_wrap.u_reg.wePulse	0	0	561845997	61586166	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	538552980	538374817	0	1851
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	538552980	0	0	617

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	561846492	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	561846492	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	561846492	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	561846492	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	561846492	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	561846492	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	561846492	137720	137720	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	561846492	48638	48638	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	561846492	1408420	1408420	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	561846492	37518432	37518432	775

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	561846492	137720	137720	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	561846492	48638	48638	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	561846492	1408420	1408420	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	561846492	37518432	37518432	775