Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	538552980	0	0	617
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	538552980	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	538552980	538382136	0	0
tb.dut.CheckAccuCntDw	0	0	617	617	0	0
tb.dut.CheckEscCntDw	0	0	617	617	0	0
tb.dut.CheckNAlerts	0	0	617	617	0	0
tb.dut.CheckNClasses	0	0	617	617	0	0
tb.dut.CheckNEscSev	0	0	617	617	0	0
tb.dut.CrashdumpKnownO_A	0	0	538552980	538382136	0	0
tb.dut.EdnKnownO_A	0	0	538552980	538382136	0	0
tb.dut.EscPKnownO_A	0	0	538552980	538382136	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	538552980	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	538552980	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	538552980	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	538552980	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	538552980	80	0	0
tb.dut.IrqAKnownO_A	0	0	538552980	538382136	0	0
tb.dut.IrqBKnownO_A	0	0	538552980	538382136	0	0
tb.dut.IrqCKnownO_A	0	0	538552980	538382136	0	0
tb.dut.IrqDKnownO_A	0	0	538552980	538382136	0	0
tb.dut.TlAReadyKnownO_A	0	0	538552980	538382136	0	0
tb.dut.TlDValidKnownO_A	0	0	538552980	538382136	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	561845997	205975	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	561845997	10441	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	561845997	11767	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	561845997	10646	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	561845997	11474	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	561845997	12750	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	561845997	10403	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	561845997	10471	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	561845997	11616	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	561845997	10255	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	561845997	10447	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	561845997	11633	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	561845997	14027	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	561845997	11560	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	561845997	11581	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	561845997	13551	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	561845997	12822	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	561845997	12688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	561845997	10557	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	561845997	12878	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	561845997	10624	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	561845997	11535	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	561845997	11545	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	561845997	12851	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	561845997	12911	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	561845997	11446	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	561845997	11568	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	561845997	11627	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	561845997	11400	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	561845997	11699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	561845997	12790	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	561845997	10445	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	561845997	12844	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	561845997	11800	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	561845997	12960	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	561845997	11605	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	561845997	11328	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	561845997	10411	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	561845997	11532	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	561845997	12527	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	561845997	12567	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	561845997	11580	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	561845997	11264	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	561845997	11562	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	561845997	14995	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	561845997	11427	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	561845997	13564	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	561845997	10540	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	561845997	10321	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	561845997	13993	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	561845997	13810	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	561845997	12975	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	561845997	13836	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	561845997	10359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	561845997	10520	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	561845997	10393	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	561845997	10221	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	561845997	11649	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	561845997	11699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	561845997	11674	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	561845997	12745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	561845997	13922	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	561845997	11592	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	561845997	11339	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	561845997	10686	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	561845997	10380	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	561845997	12519	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	561845997	12626	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	561845997	11670	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	561845997	11389	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	561845997	19388	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	561845997	10505	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	561845997	12787	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	561845997	13851	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	561845997	11634	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	561845997	12982	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	561845997	11529	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	561845997	12803	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	561845997	11405	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	538552980	2619	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	538552980	198912	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	538552980	240471078	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	538552980	236	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	538552980	797	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	538552980	52	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	538552980	390	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	538398130	175212524	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	538552980	884	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	538552980	860	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	538552980	842	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	538552980	826	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	538552980	552	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	538552980	70460	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	538552980	438	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	538552980	60	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	538552980	1322	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	538552980	1082	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	538397058	538328675	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	538552980	538382136	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	538552980	4112	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	538552980	152622	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	538552980	306810257	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	538552980	214	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	538552980	441	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	538552980	23	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	538552980	214	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	538398130	251358770	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	538552980	498	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	538552980	485	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	538552980	473	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	538552980	463	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	538552980	445	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	538552980	58080	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	538552980	380	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	538552980	40	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	538552980	1276	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	538552980	1036	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	538397058	538328675	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	538552980	538382136	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	538552980	5087	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	538552980	167668	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	538552980	314202493	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	538552980	279	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	538552980	460	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	538552980	26	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	538552980	205	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	538398130	219699249	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	538552980	510	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	538552980	500	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	538552980	491	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	538552980	482	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	538552980	465	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	538552980	47703	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	538552980	401	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	538552980	36	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	538552980	1303	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	538552980	1063	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	538397058	538328675	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	538552980	538382136	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	538552980	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	538552980	4204	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	538552980	160029	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	538552980	308537116	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	538552980	213	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	538552980	443	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	538552980	22	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	538552980	194	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	538398130	248518880	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	538552980	494	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	538552980	483	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	538552980	475	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	538552980	465	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	538552980	518	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	538552980	62419	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	538552980	453	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	538552980	40	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	538552980	1268	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	538552980	1028	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	538397058	538328675	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	538552980	538382136	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	561845997	78458513	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	561845997	561212097	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	561845997	561212097	0	0
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