Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	56411	1			T46	7		T96	7		T57	11
class_i[0x1]	52510	1			T46	535		T120	13		T57	2
class_i[0x2]	49459	1			T47	113		T96	169		T57	7
class_i[0x3]	44492	1			T18	216		T32	415		T96	411

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	48120	1			T32	196		T47	18		T46	24
alert[0x1]	51401	1			T32	178		T47	16		T46	18
alert[0x2]	53571	1			T18	216		T32	26		T47	33
alert[0x3]	49780	1			T32	15		T47	46		T46	220

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

202591

1

T18

216

T32

415

T47

113

esc_ping_fail

281

1

T19

4

T20

4

T21

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	48028	1			T32	196		T47	18		T46	24
esc_integrity_fail	alert[0x1]	51327	1			T32	178		T47	16		T46	18
esc_integrity_fail	alert[0x2]	53514	1			T18	216		T32	26		T47	33
esc_integrity_fail	alert[0x3]	49722	1			T32	15		T47	46		T46	220
esc_ping_fail	alert[0x0]	92	1			T19	1		T20	1		T265	1
esc_ping_fail	alert[0x1]	74	1			T19	1		T20	1		T265	2
esc_ping_fail	alert[0x2]	57	1			T19	2		T20	1		T21	1
esc_ping_fail	alert[0x3]	58	1			T20	1		T21	1		T265	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	56331	1			T46	7		T96	7		T57	11
esc_integrity_fail	class_i[0x1]	52462	1			T46	535		T120	13		T57	2
esc_integrity_fail	class_i[0x2]	49392	1			T47	113		T96	169		T57	7
esc_integrity_fail	class_i[0x3]	44406	1			T18	216		T32	415		T96	411
esc_ping_fail	class_i[0x0]	80	1			T155	11		T335	5		T333	8
esc_ping_fail	class_i[0x1]	48	1			T20	3		T335	1		T102	3
esc_ping_fail	class_i[0x2]	67	1			T21	2		T155	1		T102	1
esc_ping_fail	class_i[0x3]	86	1			T19	4		T20	1		T265	7