Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	171	1			T28	1		T47	1		T165	1
index[0x1]	135	1			T16	1		T18	1		T44	1
index[0x2]	139	1			T32	1		T47	1		T95	1
index[0x3]	134	1			T29	2		T165	1		T96	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	189	1			T18	1		T32	1		T165	1
lens_less_than_1000[1]	114	1			T28	1		T16	1		T44	1
lens_less_than_1000[2]	75	1			T46	1		T56	3		T57	1
lens_less_than_1000[3]	51	1			T47	1		T97	1		T57	1
lens_less_than_1000[4]	46	1			T143	1		T43	1		T70	1
lens_less_than_1000[5]	50	1			T29	2		T47	1		T103	3
lens_less_than_1000[6]	17	1			T111	1		T67	1		T286	1
lens_less_than_1000[7]	15	1			T42	1		T136	1		T122	1
lens_less_than_1000[8]	4	1			T287	1		T140	1		T288	1
lens_less_than_1000[9]	3	1			T100	1		T289	1		T78	1
len_2	15	1			T100	2		T290	7		T291	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1]]	[lens_less_than_1000[8] , lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	53	1			T165	1		T292	1		T92	1
index[0x0]	lens_less_than_1000[1]	40	1			T28	1		T96	1		T110	1
index[0x0]	lens_less_than_1000[2]	25	1			T57	1		T89	1		T91	1
index[0x0]	lens_less_than_1000[3]	14	1			T97	1		T42	1		T88	1
index[0x0]	lens_less_than_1000[4]	14	1			T116	1		T38	1		T147	1
index[0x0]	lens_less_than_1000[5]	15	1			T47	1		T73	1		T293	1
index[0x0]	lens_less_than_1000[6]	1	1			T286	1		-	-		-	-
index[0x0]	lens_less_than_1000[7]	5	1			T294	1		T295	1		T296	1
index[0x0]	lens_less_than_1000[8]	1	1			T297	1		-	-		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T78	1		-	-		-	-
index[0x0]	len_2	2	1			T298	1		T299	1		-	-
index[0x1]	lens_less_than_1000[0]	47	1			T18	1		T42	1		T67	1
index[0x1]	lens_less_than_1000[1]	25	1			T16	1		T44	1		T56	1
index[0x1]	lens_less_than_1000[2]	18	1			T46	1		T300	1		T126	1
index[0x1]	lens_less_than_1000[3]	12	1			T57	1		T136	1		T301	1
index[0x1]	lens_less_than_1000[4]	7	1			T302	5		T303	1		T304	1
index[0x1]	lens_less_than_1000[5]	10	1			T103	3		T305	1		T306	1
index[0x1]	lens_less_than_1000[6]	3	1			T67	1		T307	1		T276	1
index[0x1]	lens_less_than_1000[7]	2	1			T308	1		T309	1		-	-
index[0x1]	len_2	11	1			T100	2		T290	7		T310	1
index[0x2]	lens_less_than_1000[0]	47	1			T32	1		T56	1		T143	1
index[0x2]	lens_less_than_1000[1]	28	1			T95	1		T51	1		T74	1
index[0x2]	lens_less_than_1000[2]	17	1			T56	1		T42	1		T74	1
index[0x2]	lens_less_than_1000[3]	14	1			T47	1		T69	1		T311	1
index[0x2]	lens_less_than_1000[4]	11	1			T70	1		T75	1		T312	1
index[0x2]	lens_less_than_1000[5]	15	1			T94	1		T129	1		T313	1
index[0x2]	lens_less_than_1000[6]	3	1			T111	1		T314	1		T315	1
index[0x2]	lens_less_than_1000[7]	1	1			T278	1		-	-		-	-
index[0x2]	lens_less_than_1000[8]	1	1			T288	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T100	1		-	-		-	-
index[0x2]	len_2	1	1			T316	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	42	1			T56	1		T99	1		T42	2
index[0x3]	lens_less_than_1000[1]	21	1			T165	1		T96	1		T100	1
index[0x3]	lens_less_than_1000[2]	15	1			T56	2		T35	1		T134	1
index[0x3]	lens_less_than_1000[3]	11	1			T51	1		T40	1		T117	1
index[0x3]	lens_less_than_1000[4]	14	1			T143	1		T43	1		T124	1
index[0x3]	lens_less_than_1000[5]	10	1			T29	2		T317	1		T318	1
index[0x3]	lens_less_than_1000[6]	10	1			T147	4		T319	1		T320	1
index[0x3]	lens_less_than_1000[7]	7	1			T42	1		T136	1		T122	1
index[0x3]	lens_less_than_1000[8]	2	1			T287	1		T140	1		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T289	1		-	-		-	-
index[0x3]	len_2	1	1			T291	1		-	-		-	-