Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	60	1			T46	3		T107	1		T110	1
class_index[0x1]	40	1			T11	1		T32	1		T100	2
class_index[0x2]	36	1			T107	1		T110	1		T104	1
class_index[0x3]	40	1			T47	1		T107	2		T99	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	72	1			T107	1		T110	2		T113	1
intr_timeout_cnt[1]	37	1			T11	1		T99	1		T104	1
intr_timeout_cnt[2]	24	1			T46	3		T107	1		T100	1
intr_timeout_cnt[3]	8	1			T107	2		T75	1		T121	1
intr_timeout_cnt[4]	5	1			T32	1		T117	1		T163	1
intr_timeout_cnt[5]	6	1			T121	1		T164	1		T135	1
intr_timeout_cnt[6]	8	1			T94	1		T75	1		T164	1
intr_timeout_cnt[7]	3	1			T266	1		T267	1		T268	1
intr_timeout_cnt[8]	5	1			T161	2		T122	1		T269	1
intr_timeout_cnt[9]	8	1			T47	1		T100	1		T270	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6] , intr_timeout_cnt[7]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	25	1			T107	1		T110	1		T67	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T91	1		T116	1		T35	1
class_index[0x0]	intr_timeout_cnt[2]	9	1			T46	3		T118	2		T121	1
class_index[0x0]	intr_timeout_cnt[3]	1	1			T271	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[4]	1	1			T117	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	3	1			T121	1		T164	1		T78	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T94	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T266	1		T268	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T161	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T270	1		T272	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	16	1			T113	1		T114	1		T67	1
class_index[0x1]	intr_timeout_cnt[1]	10	1			T11	1		T40	1		T273	2
class_index[0x1]	intr_timeout_cnt[2]	4	1			T100	1		T91	1		T266	1
class_index[0x1]	intr_timeout_cnt[3]	1	1			T121	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	1	1			T32	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T135	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	4	1			T75	1		T141	2		T274	1
class_index[0x1]	intr_timeout_cnt[7]	1	1			T267	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T100	1		T275	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	15	1			T110	1		T89	1		T116	1
class_index[0x2]	intr_timeout_cnt[1]	9	1			T104	1		T115	1		T75	1
class_index[0x2]	intr_timeout_cnt[2]	6	1			T107	1		T40	1		T142	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T276	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	2	1			T277	1		T278	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T279	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T280	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T281	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	16	1			T116	1		T130	2		T282	1
class_index[0x3]	intr_timeout_cnt[1]	3	1			T99	1		T266	1		T283	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T94	1		T116	1		T162	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T107	2		T75	1		T284	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T163	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T283	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	3	1			T164	1		T278	1		T285	1
class_index[0x3]	intr_timeout_cnt[8]	3	1			T161	1		T122	1		T269	1
class_index[0x3]	intr_timeout_cnt[9]	3	1			T47	1		T278	1		T285	1