Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	280676	1			T1	3		T2	5		T10	21
all_values[1]	280676	1			T1	3		T2	5		T10	21
all_values[2]	280676	1			T1	3		T2	5		T10	21
all_values[3]	280676	1			T1	3		T2	5		T10	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

557258

1

T1

12

T2

7

T10

36

auto[1]

565446

1

T2

13

T10

48

T28

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

669277

1

T1

8

T2

18

T10

44

auto[1]

453427

1

T1

4

T2

2

T10

40

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	80958	1			T1	2		T10	4		T28	6
all_values[0]	auto[0]	auto[1]	58406	1			T1	1		T10	4		T28	3
all_values[0]	auto[1]	auto[0]	82226	1			T2	3		T10	7		T28	6
all_values[0]	auto[1]	auto[1]	59086	1			T2	2		T10	6		T28	2
all_values[1]	auto[0]	auto[0]	83466	1			T1	2		T2	2		T10	7
all_values[1]	auto[0]	auto[1]	55366	1			T1	1		T10	7		T11	8
all_values[1]	auto[1]	auto[0]	85735	1			T2	3		T10	4		T28	9
all_values[1]	auto[1]	auto[1]	56109	1			T10	3		T11	6		T16	12
all_values[2]	auto[0]	auto[0]	83331	1			T1	2		T2	2		T10	2
all_values[2]	auto[0]	auto[1]	56575	1			T1	1		T10	2		T11	8
all_values[2]	auto[1]	auto[0]	84513	1			T2	3		T10	9		T28	8
all_values[2]	auto[1]	auto[1]	56257	1			T10	8		T11	6		T16	14
all_values[3]	auto[0]	auto[0]	83638	1			T1	2		T2	3		T10	5
all_values[3]	auto[0]	auto[1]	55518	1			T1	1		T10	5		T11	10
all_values[3]	auto[1]	auto[0]	85410	1			T2	2		T10	6		T28	7
all_values[3]	auto[1]	auto[1]	56110	1			T10	5		T11	4		T16	13