Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	280676	1			T1	3		T2	5		T10	21
all_pins[1]	280676	1			T1	3		T2	5		T10	21
all_pins[2]	280676	1			T1	3		T2	5		T10	21
all_pins[3]	280676	1			T1	3		T2	5		T10	21

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	895142	1			T1	12		T2	18		T10	62
values[0x1]	227562	1			T2	2		T10	22		T28	2
transitions[0x0=>0x1]	150688	1			T2	1		T10	13		T28	2
transitions[0x1=>0x0]	150949	1			T2	2		T10	14		T28	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	221590	1			T1	3		T2	3		T10	15
all_pins[0]	values[0x1]	59086	1			T2	2		T10	6		T28	2
all_pins[0]	transitions[0x0=>0x1]	58533	1			T2	1		T10	5		T28	2
all_pins[0]	transitions[0x1=>0x0]	55818	1			T10	5		T11	4		T16	13
all_pins[1]	values[0x0]	224567	1			T1	3		T2	5		T10	18
all_pins[1]	values[0x1]	56109	1			T10	3		T11	6		T16	12
all_pins[1]	transitions[0x0=>0x1]	30745	1			T10	1		T11	3		T16	8
all_pins[1]	transitions[0x1=>0x0]	33722	1			T2	2		T10	4		T28	2
all_pins[2]	values[0x0]	224419	1			T1	3		T2	5		T10	13
all_pins[2]	values[0x1]	56257	1			T10	8		T11	6		T16	14
all_pins[2]	transitions[0x0=>0x1]	30722	1			T10	6		T11	4		T16	5
all_pins[2]	transitions[0x1=>0x0]	30574	1			T10	1		T11	4		T16	3
all_pins[3]	values[0x0]	224566	1			T1	3		T2	5		T10	16
all_pins[3]	values[0x1]	56110	1			T10	5		T11	4		T16	13
all_pins[3]	transitions[0x0=>0x1]	30688	1			T10	1		T16	3		T13	4
all_pins[3]	transitions[0x1=>0x0]	30835	1			T10	4		T11	2		T16	4